8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 load_addr_mask=1099511627775
24 memories=system.physmem
28 work_begin_ckpt_count=0
29 work_begin_cpu_id_exit=-1
30 work_begin_exit_count=0
31 work_cpus_ckpt_count=0
35 system_port=system.membus.slave[0]
41 voltage_domain=system.voltage_domain
45 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
54 branchPred=system.cpu.branchPred
57 clk_domain=system.cpu_clk_domain
68 do_checkpoint_insts=true
70 do_statistics_insts=true
71 dstage2_mmu=system.cpu.dstage2_mmu
79 fuPool=system.cpu.fuPool
81 function_trace_start=0
86 interrupts=system.cpu.interrupts
90 istage2_mmu=system.cpu.istage2_mmu
92 max_insts_all_threads=0
93 max_insts_any_thread=0
94 max_loads_all_threads=0
95 max_loads_any_thread=0
106 renameToDecodeDelay=1
111 simpoint_start_insts=
112 smtCommitPolicy=RoundRobin
113 smtFetchPolicy=SingleThread
114 smtIQPolicy=Partitioned
116 smtLSQPolicy=Partitioned
118 smtNumFetchingThreads=1
119 smtROBPolicy=Partitioned
122 store_set_clear_period=250000
125 tracer=system.cpu.tracer
129 workload=system.cpu.workload
130 dcache_port=system.cpu.dcache.cpu_side
131 icache_port=system.cpu.icache.cpu_side
133 [system.cpu.branchPred]
139 choicePredictorSize=8192
142 globalPredictorSize=8192
145 localHistoryTableSize=2048
146 localPredictorSize=2048
153 addr_ranges=0:18446744073709551615
155 clk_domain=system.cpu_clk_domain
162 prefetch_on_access=false
165 sequential_access=false
168 tags=system.cpu.dcache.tags
172 cpu_side=system.cpu.dcache_port
173 mem_side=system.cpu.toL2Bus.slave[1]
175 [system.cpu.dcache.tags]
179 clk_domain=system.cpu_clk_domain
182 sequential_access=false
185 [system.cpu.dstage2_mmu]
189 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
192 [system.cpu.dstage2_mmu.stage2_tlb]
198 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
200 [system.cpu.dstage2_mmu.stage2_tlb.walker]
202 clk_domain=system.cpu_clk_domain
205 num_squash_per_cycle=2
207 port=system.cpu.toL2Bus.slave[5]
215 walker=system.cpu.dtb.walker
217 [system.cpu.dtb.walker]
219 clk_domain=system.cpu_clk_domain
222 num_squash_per_cycle=2
224 port=system.cpu.toL2Bus.slave[3]
228 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
229 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
232 [system.cpu.fuPool.FUList0]
237 opList=system.cpu.fuPool.FUList0.opList
239 [system.cpu.fuPool.FUList0.opList]
246 [system.cpu.fuPool.FUList1]
248 children=opList0 opList1
251 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
253 [system.cpu.fuPool.FUList1.opList0]
260 [system.cpu.fuPool.FUList1.opList1]
267 [system.cpu.fuPool.FUList2]
269 children=opList0 opList1 opList2
272 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
274 [system.cpu.fuPool.FUList2.opList0]
281 [system.cpu.fuPool.FUList2.opList1]
288 [system.cpu.fuPool.FUList2.opList2]
295 [system.cpu.fuPool.FUList3]
297 children=opList0 opList1 opList2
300 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
302 [system.cpu.fuPool.FUList3.opList0]
309 [system.cpu.fuPool.FUList3.opList1]
316 [system.cpu.fuPool.FUList3.opList2]
323 [system.cpu.fuPool.FUList4]
328 opList=system.cpu.fuPool.FUList4.opList
330 [system.cpu.fuPool.FUList4.opList]
337 [system.cpu.fuPool.FUList5]
339 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
342 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
344 [system.cpu.fuPool.FUList5.opList00]
351 [system.cpu.fuPool.FUList5.opList01]
358 [system.cpu.fuPool.FUList5.opList02]
365 [system.cpu.fuPool.FUList5.opList03]
372 [system.cpu.fuPool.FUList5.opList04]
379 [system.cpu.fuPool.FUList5.opList05]
386 [system.cpu.fuPool.FUList5.opList06]
393 [system.cpu.fuPool.FUList5.opList07]
400 [system.cpu.fuPool.FUList5.opList08]
407 [system.cpu.fuPool.FUList5.opList09]
414 [system.cpu.fuPool.FUList5.opList10]
421 [system.cpu.fuPool.FUList5.opList11]
428 [system.cpu.fuPool.FUList5.opList12]
435 [system.cpu.fuPool.FUList5.opList13]
442 [system.cpu.fuPool.FUList5.opList14]
449 [system.cpu.fuPool.FUList5.opList15]
456 [system.cpu.fuPool.FUList5.opList16]
460 opClass=SimdFloatMisc
463 [system.cpu.fuPool.FUList5.opList17]
467 opClass=SimdFloatMult
470 [system.cpu.fuPool.FUList5.opList18]
474 opClass=SimdFloatMultAcc
477 [system.cpu.fuPool.FUList5.opList19]
481 opClass=SimdFloatSqrt
484 [system.cpu.fuPool.FUList6]
489 opList=system.cpu.fuPool.FUList6.opList
491 [system.cpu.fuPool.FUList6.opList]
498 [system.cpu.fuPool.FUList7]
500 children=opList0 opList1
503 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
505 [system.cpu.fuPool.FUList7.opList0]
512 [system.cpu.fuPool.FUList7.opList1]
519 [system.cpu.fuPool.FUList8]
524 opList=system.cpu.fuPool.FUList8.opList
526 [system.cpu.fuPool.FUList8.opList]
536 addr_ranges=0:18446744073709551615
538 clk_domain=system.cpu_clk_domain
545 prefetch_on_access=false
548 sequential_access=false
551 tags=system.cpu.icache.tags
555 cpu_side=system.cpu.icache_port
556 mem_side=system.cpu.toL2Bus.slave[0]
558 [system.cpu.icache.tags]
562 clk_domain=system.cpu_clk_domain
565 sequential_access=false
568 [system.cpu.interrupts]
578 id_aa64dfr0_el1=1052678
582 id_aa64mmfr0_el1=15728642
601 [system.cpu.istage2_mmu]
605 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
608 [system.cpu.istage2_mmu.stage2_tlb]
614 walker=system.cpu.istage2_mmu.stage2_tlb.walker
616 [system.cpu.istage2_mmu.stage2_tlb.walker]
618 clk_domain=system.cpu_clk_domain
621 num_squash_per_cycle=2
623 port=system.cpu.toL2Bus.slave[4]
631 walker=system.cpu.itb.walker
633 [system.cpu.itb.walker]
635 clk_domain=system.cpu_clk_domain
638 num_squash_per_cycle=2
640 port=system.cpu.toL2Bus.slave[2]
645 addr_ranges=0:18446744073709551615
647 clk_domain=system.cpu_clk_domain
654 prefetch_on_access=false
657 sequential_access=false
660 tags=system.cpu.l2cache.tags
664 cpu_side=system.cpu.toL2Bus.master[0]
665 mem_side=system.membus.slave[1]
667 [system.cpu.l2cache.tags]
671 clk_domain=system.cpu_clk_domain
674 sequential_access=false
679 clk_domain=system.cpu_clk_domain
683 use_default_range=false
685 master=system.cpu.l2cache.cpu_side
686 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
692 [system.cpu.workload]
701 executable=/dist/test-progs/hello/bin/arm/linux/hello
704 max_stack_size=67108864
712 [system.cpu_clk_domain]
716 voltage_domain=system.voltage_domain
720 clk_domain=system.clk_domain
724 use_default_range=false
726 master=system.physmem.port
727 slave=system.system_port system.cpu.l2cache.mem_side
732 addr_mapping=RaBaChCo
736 clk_domain=system.clk_domain
737 conf_table_reported=true
739 device_rowbuffer_size=1024
743 mem_sched_policy=frfcfs
749 static_backend_latency=10000
750 static_frontend_latency=10000
762 write_high_thresh_perc=70
763 write_low_thresh_perc=0
764 port=system.membus.master[0]
766 [system.voltage_domain]