2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000012 # Number of seconds simulated
4 sim_ticks 11859500 # Number of ticks simulated
5 final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 50616 # Simulator instruction rate (inst/s)
8 host_op_rate 59274 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 130716325 # Simulator tick rate (ticks/s)
10 host_mem_usage 300356 # Number of bytes of host memory used
11 host_seconds 0.09 # Real time elapsed on the host
12 sim_insts 4591 # Number of instructions simulated
13 sim_ops 5377 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 46848 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 732 # Number of read requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.readReqs 733 # Number of read requests accepted
37 system.physmem.writeReqs 0 # Number of write requests accepted
38 system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue
39 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
40 system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM
41 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
42 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
43 system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side
44 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
45 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
46 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
47 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
48 system.physmem.perBankRdBursts::0 143 # Per bank write bursts
49 system.physmem.perBankRdBursts::1 90 # Per bank write bursts
50 system.physmem.perBankRdBursts::2 40 # Per bank write bursts
51 system.physmem.perBankRdBursts::3 73 # Per bank write bursts
52 system.physmem.perBankRdBursts::4 58 # Per bank write bursts
53 system.physmem.perBankRdBursts::5 88 # Per bank write bursts
54 system.physmem.perBankRdBursts::6 52 # Per bank write bursts
55 system.physmem.perBankRdBursts::7 18 # Per bank write bursts
56 system.physmem.perBankRdBursts::8 12 # Per bank write bursts
57 system.physmem.perBankRdBursts::9 28 # Per bank write bursts
58 system.physmem.perBankRdBursts::10 34 # Per bank write bursts
59 system.physmem.perBankRdBursts::11 47 # Per bank write bursts
60 system.physmem.perBankRdBursts::12 17 # Per bank write bursts
61 system.physmem.perBankRdBursts::13 19 # Per bank write bursts
62 system.physmem.perBankRdBursts::14 0 # Per bank write bursts
63 system.physmem.perBankRdBursts::15 14 # Per bank write bursts
64 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
77 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
78 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
79 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
80 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
81 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
82 system.physmem.totGap 11846500 # Total gap between requests
83 system.physmem.readPktSize::0 0 # Read request sizes (log2)
84 system.physmem.readPktSize::1 0 # Read request sizes (log2)
85 system.physmem.readPktSize::2 0 # Read request sizes (log2)
86 system.physmem.readPktSize::3 0 # Read request sizes (log2)
87 system.physmem.readPktSize::4 0 # Read request sizes (log2)
88 system.physmem.readPktSize::5 0 # Read request sizes (log2)
89 system.physmem.readPktSize::6 733 # Read request sizes (log2)
90 system.physmem.writePktSize::0 0 # Write request sizes (log2)
91 system.physmem.writePktSize::1 0 # Write request sizes (log2)
92 system.physmem.writePktSize::2 0 # Write request sizes (log2)
93 system.physmem.writePktSize::3 0 # Write request sizes (log2)
94 system.physmem.writePktSize::4 0 # Write request sizes (log2)
95 system.physmem.writePktSize::5 0 # Write request sizes (log2)
96 system.physmem.writePktSize::6 0 # Write request sizes (log2)
97 system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
129 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
193 system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation
207 system.physmem.totQLat 17284989 # Total ticks spent queuing
208 system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM
209 system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers
210 system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst
211 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
212 system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst
213 system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s
214 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
215 system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s
216 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
217 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
218 system.physmem.busUtil 30.90 # Data bus utilization in percentage
219 system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads
220 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
221 system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing
222 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
223 system.physmem.readRowHits 662 # Number of row buffer hits during reads
224 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
225 system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads
226 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
227 system.physmem.avgGap 16161.66 # Average gap between requests
228 system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined
229 system.physmem.memoryStateTime::IDLE 6500 # Time in different power states
230 system.physmem.memoryStateTime::REF 260000 # Time in different power states
231 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
232 system.physmem.memoryStateTime::ACT 7800750 # Time in different power states
233 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
234 system.membus.trans_dist::ReadReq 704 # Transaction distribution
235 system.membus.trans_dist::ReadResp 702 # Transaction distribution
236 system.membus.trans_dist::ReadExReq 29 # Transaction distribution
237 system.membus.trans_dist::ReadExResp 29 # Transaction distribution
238 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes)
239 system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes)
240 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes)
241 system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes)
242 system.membus.snoops 0 # Total snoops (count)
243 system.membus.snoop_fanout::samples 733 # Request fanout histogram
244 system.membus.snoop_fanout::mean 0 # Request fanout histogram
245 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
246 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
247 system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram
248 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
249 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
250 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
251 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
252 system.membus.snoop_fanout::total 733 # Request fanout histogram
253 system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks)
254 system.membus.reqLayer0.utilization 6.8 # Layer utilization (%)
255 system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks)
256 system.membus.respLayer1.utilization 55.9 # Layer utilization (%)
257 system.cpu_clk_domain.clock 500 # Clock period in ticks
258 system.cpu.branchPred.lookups 2560 # Number of BP lookups
259 system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted
260 system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect
261 system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups
262 system.cpu.branchPred.BTBHits 497 # Number of BTB hits
263 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
264 system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage
265 system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target.
266 system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions.
267 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
268 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
269 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
270 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
271 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
272 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
273 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
274 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
275 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
276 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
277 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
278 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
279 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
280 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
281 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
282 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
283 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
284 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
285 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
286 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
287 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
288 system.cpu.dtb.inst_hits 0 # ITB inst hits
289 system.cpu.dtb.inst_misses 0 # ITB inst misses
290 system.cpu.dtb.read_hits 0 # DTB read hits
291 system.cpu.dtb.read_misses 0 # DTB read misses
292 system.cpu.dtb.write_hits 0 # DTB write hits
293 system.cpu.dtb.write_misses 0 # DTB write misses
294 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
295 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
296 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
297 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
298 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
299 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
300 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
301 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
302 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
303 system.cpu.dtb.read_accesses 0 # DTB read accesses
304 system.cpu.dtb.write_accesses 0 # DTB write accesses
305 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
306 system.cpu.dtb.hits 0 # DTB hits
307 system.cpu.dtb.misses 0 # DTB misses
308 system.cpu.dtb.accesses 0 # DTB accesses
309 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
310 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
311 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
312 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
313 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
314 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
315 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
316 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
317 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
318 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
319 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
320 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
321 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
322 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
323 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
324 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
325 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
326 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
327 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
328 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
329 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
330 system.cpu.itb.inst_hits 0 # ITB inst hits
331 system.cpu.itb.inst_misses 0 # ITB inst misses
332 system.cpu.itb.read_hits 0 # DTB read hits
333 system.cpu.itb.read_misses 0 # DTB read misses
334 system.cpu.itb.write_hits 0 # DTB write hits
335 system.cpu.itb.write_misses 0 # DTB write misses
336 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
337 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
338 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
339 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
340 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
341 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
342 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
343 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
344 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
345 system.cpu.itb.read_accesses 0 # DTB read accesses
346 system.cpu.itb.write_accesses 0 # DTB write accesses
347 system.cpu.itb.inst_accesses 0 # ITB inst accesses
348 system.cpu.itb.hits 0 # DTB hits
349 system.cpu.itb.misses 0 # DTB misses
350 system.cpu.itb.accesses 0 # DTB accesses
351 system.cpu.workload.num_syscalls 13 # Number of system calls
352 system.cpu.numCycles 23720 # number of cpu cycles simulated
353 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
354 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
355 system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss
356 system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed
357 system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered
358 system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken
359 system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked
360 system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing
361 system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
362 system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps
363 system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR
364 system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched
365 system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed
366 system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
375 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
376 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
377 system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total)
378 system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle
379 system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle
380 system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle
381 system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked
382 system.cpu.decode.RunCycles 5106 # Number of cycles decode is running
383 system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking
384 system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing
385 system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch
386 system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction
387 system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode
388 system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode
389 system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing
390 system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle
391 system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking
392 system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst
393 system.cpu.rename.RunCycles 4105 # Number of cycles rename is running
394 system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking
395 system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename
396 system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename
397 system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
398 system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
399 system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full
400 system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full
401 system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed
402 system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made
403 system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups
404 system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups
405 system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
406 system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing
407 system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
408 system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
409 system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer
410 system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit.
411 system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit.
412 system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
413 system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
414 system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec)
415 system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ
416 system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued
417 system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued
418 system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling
419 system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph
420 system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
421 system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
431 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
432 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
433 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
434 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
435 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
436 system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
437 system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle
438 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
439 system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available
440 system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available
441 system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available
442 system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available
443 system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available
444 system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available
445 system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available
446 system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available
447 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available
463 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available
464 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available
465 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available
466 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available
467 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available
468 system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available
469 system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available
470 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
471 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
472 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
473 system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued
474 system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued
475 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued
476 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued
477 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued
478 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued
479 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued
480 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued
481 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued
497 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued
498 system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued
499 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued
500 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued
501 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued
502 system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued
503 system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued
504 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
505 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
506 system.cpu.iq.FU_type_0::total 7242 # Type of FU issued
507 system.cpu.iq.rate 0.305312 # Inst issue rate
508 system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested
509 system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst)
510 system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads
511 system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes
512 system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses
513 system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads
514 system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes
515 system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
516 system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses
517 system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses
518 system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores
519 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
520 system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed
521 system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
522 system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
523 system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed
524 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
525 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
526 system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
527 system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked
528 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
529 system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing
530 system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking
531 system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking
532 system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ
533 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
534 system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions
535 system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions
536 system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
537 system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
538 system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall
539 system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
540 system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly
541 system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
542 system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute
543 system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions
544 system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed
545 system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute
546 system.cpu.iew.exec_swp 0 # number of swp insts executed
547 system.cpu.iew.exec_nop 14 # number of nop insts executed
548 system.cpu.iew.exec_refs 2449 # number of memory reference insts executed
549 system.cpu.iew.exec_branches 1283 # Number of branches executed
550 system.cpu.iew.exec_stores 1021 # Number of stores executed
551 system.cpu.iew.exec_rate 0.287858 # Inst execution rate
552 system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit
553 system.cpu.iew.wb_count 6654 # cumulative count of insts written-back
554 system.cpu.iew.wb_producers 3045 # num instructions producing a value
555 system.cpu.iew.wb_consumers 5519 # num instructions consuming a value
556 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
557 system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle
558 system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back
559 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
560 system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit
561 system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
562 system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted
563 system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle
574 system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle
575 system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle
576 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
577 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
578 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
579 system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle
580 system.cpu.commit.committedInsts 4591 # Number of instructions committed
581 system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed
582 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
583 system.cpu.commit.refs 1965 # Number of memory references committed
584 system.cpu.commit.loads 1027 # Number of loads committed
585 system.cpu.commit.membars 12 # Number of memory barriers committed
586 system.cpu.commit.branches 1007 # Number of branches committed
587 system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
588 system.cpu.commit.int_insts 4624 # Number of committed integer instructions.
589 system.cpu.commit.function_calls 82 # Number of function calls committed.
590 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
591 system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction
592 system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction
593 system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction
594 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction
595 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction
596 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction
597 system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction
598 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction
599 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction
600 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction
601 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction
602 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction
603 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction
604 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction
605 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction
606 system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction
607 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction
608 system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction
609 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction
610 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction
611 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction
612 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction
613 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction
614 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction
615 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction
616 system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction
617 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
618 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
619 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
620 system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
621 system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
622 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
623 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
624 system.cpu.commit.op_class_0::total 5377 # Class of committed instruction
625 system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached
626 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
627 system.cpu.rob.rob_reads 24066 # The number of ROB reads
628 system.cpu.rob.rob_writes 16749 # The number of ROB writes
629 system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself
630 system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling
631 system.cpu.committedInsts 4591 # Number of Instructions Simulated
632 system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated
633 system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction
634 system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads
635 system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle
636 system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads
637 system.cpu.int_regfile_reads 6786 # number of integer regfile reads
638 system.cpu.int_regfile_writes 3839 # number of integer regfile writes
639 system.cpu.fp_regfile_reads 16 # number of floating regfile reads
640 system.cpu.cc_regfile_reads 24301 # number of cc regfile reads
641 system.cpu.cc_regfile_writes 2919 # number of cc regfile writes
642 system.cpu.misc_regfile_reads 2642 # number of misc regfile reads
643 system.cpu.misc_regfile_writes 24 # number of misc regfile writes
644 system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution
645 system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
646 system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution
647 system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution
648 system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution
649 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes)
650 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
651 system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes)
652 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes)
653 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
654 system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
655 system.cpu.toL2Bus.snoops 1026 # Total snoops (count)
656 system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram
657 system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram
658 system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram
659 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
660 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
661 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
662 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
663 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
664 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
665 system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram
666 system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram
667 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
668 system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
669 system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
670 system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram
671 system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks)
672 system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
673 system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks)
674 system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%)
675 system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks)
676 system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
677 system.cpu.icache.tags.replacements 47 # number of replacements
678 system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use
679 system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks.
680 system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks.
681 system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks.
682 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
683 system.cpu.icache.tags.occ_blocks::cpu.inst 138.950029 # Average occupied blocks per requestor
684 system.cpu.icache.tags.occ_percent::cpu.inst 0.271387 # Average percentage of cache occupancy
685 system.cpu.icache.tags.occ_percent::total 0.271387 # Average percentage of cache occupancy
686 system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
687 system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
688 system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
689 system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id
690 system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses
691 system.cpu.icache.tags.data_accesses 8536 # Number of data accesses
692 system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits
693 system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits
694 system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits
695 system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits
696 system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits
697 system.cpu.icache.overall_hits::total 3784 # number of overall hits
698 system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses
699 system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses
700 system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses
701 system.cpu.icache.demand_misses::total 332 # number of demand (read+write) misses
702 system.cpu.icache.overall_misses::cpu.inst 332 # number of overall misses
703 system.cpu.icache.overall_misses::total 332 # number of overall misses
704 system.cpu.icache.ReadReq_miss_latency::cpu.inst 7426247 # number of ReadReq miss cycles
705 system.cpu.icache.ReadReq_miss_latency::total 7426247 # number of ReadReq miss cycles
706 system.cpu.icache.demand_miss_latency::cpu.inst 7426247 # number of demand (read+write) miss cycles
707 system.cpu.icache.demand_miss_latency::total 7426247 # number of demand (read+write) miss cycles
708 system.cpu.icache.overall_miss_latency::cpu.inst 7426247 # number of overall miss cycles
709 system.cpu.icache.overall_miss_latency::total 7426247 # number of overall miss cycles
710 system.cpu.icache.ReadReq_accesses::cpu.inst 4116 # number of ReadReq accesses(hits+misses)
711 system.cpu.icache.ReadReq_accesses::total 4116 # number of ReadReq accesses(hits+misses)
712 system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses
713 system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses
714 system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses
715 system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses
716 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses
717 system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses
718 system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses
719 system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses
720 system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses
721 system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses
722 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency
723 system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency
724 system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency
725 system.cpu.icache.demand_avg_miss_latency::total 22368.213855 # average overall miss latency
726 system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency
727 system.cpu.icache.overall_avg_miss_latency::total 22368.213855 # average overall miss latency
728 system.cpu.icache.blocked_cycles::no_mshrs 1112 # number of cycles access was blocked
729 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
730 system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked
731 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
732 system.cpu.icache.avg_blocked_cycles::no_mshrs 16.848485 # average number of cycles each access was blocked
733 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
734 system.cpu.icache.fast_writes 0 # number of fast writes performed
735 system.cpu.icache.cache_copies 0 # number of cache copies performed
736 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits
737 system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
738 system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits
739 system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
740 system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits
741 system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits
742 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
743 system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
744 system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
745 system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
746 system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
747 system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
748 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6489997 # number of ReadReq MSHR miss cycles
749 system.cpu.icache.ReadReq_mshr_miss_latency::total 6489997 # number of ReadReq MSHR miss cycles
750 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6489997 # number of demand (read+write) MSHR miss cycles
751 system.cpu.icache.demand_mshr_miss_latency::total 6489997 # number of demand (read+write) MSHR miss cycles
752 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6489997 # number of overall MSHR miss cycles
753 system.cpu.icache.overall_mshr_miss_latency::total 6489997 # number of overall MSHR miss cycles
754 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for ReadReq accesses
755 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.073858 # mshr miss rate for ReadReq accesses
756 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for demand accesses
757 system.cpu.icache.demand_mshr_miss_rate::total 0.073858 # mshr miss rate for demand accesses
758 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for overall accesses
759 system.cpu.icache.overall_mshr_miss_rate::total 0.073858 # mshr miss rate for overall accesses
760 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342 # average ReadReq mshr miss latency
761 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342 # average ReadReq mshr miss latency
762 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency
763 system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency
764 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency
765 system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency
766 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
767 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified
768 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr
769 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache
770 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue
771 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
772 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated
773 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # number of hwpf issued
774 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 198 # number of hwpf spanning a virtual page
775 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
776 system.cpu.l2cache.tags.replacements 0 # number of replacements
777 system.cpu.l2cache.tags.tagsinuse 370.948422 # Cycle average of tags in use
778 system.cpu.l2cache.tags.total_refs 270 # Total number of references to valid blocks.
779 system.cpu.l2cache.tags.sampled_refs 691 # Sample count of references to valid blocks.
780 system.cpu.l2cache.tags.avg_refs 0.390738 # Average number of references to valid blocks.
781 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
782 system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.449811 # Average occupied blocks per requestor
783 system.cpu.l2cache.tags.occ_blocks::cpu.data 36.598805 # Average occupied blocks per requestor
784 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 303.899806 # Average occupied blocks per requestor
785 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001859 # Average percentage of cache occupancy
786 system.cpu.l2cache.tags.occ_percent::cpu.data 0.002234 # Average percentage of cache occupancy
787 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.018549 # Average percentage of cache occupancy
788 system.cpu.l2cache.tags.occ_percent::total 0.022641 # Average percentage of cache occupancy
789 system.cpu.l2cache.tags.occ_task_id_blocks::1022 570 # Occupied blocks per task id
790 system.cpu.l2cache.tags.occ_task_id_blocks::1024 121 # Occupied blocks per task id
791 system.cpu.l2cache.tags.age_task_id_blocks_1022::0 471 # Occupied blocks per task id
792 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 99 # Occupied blocks per task id
793 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
794 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
795 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id
796 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id
797 system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses
798 system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses
799 system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits
800 system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits
801 system.cpu.l2cache.ReadReq_hits::total 269 # number of ReadReq hits
802 system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits
803 system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits
804 system.cpu.l2cache.demand_hits::cpu.inst 234 # number of demand (read+write) hits
805 system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits
806 system.cpu.l2cache.demand_hits::total 280 # number of demand (read+write) hits
807 system.cpu.l2cache.overall_hits::cpu.inst 234 # number of overall hits
808 system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits
809 system.cpu.l2cache.overall_hits::total 280 # number of overall hits
810 system.cpu.l2cache.ReadReq_misses::cpu.inst 70 # number of ReadReq misses
811 system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses
812 system.cpu.l2cache.ReadReq_misses::total 139 # number of ReadReq misses
813 system.cpu.l2cache.ReadExReq_misses::cpu.data 29 # number of ReadExReq misses
814 system.cpu.l2cache.ReadExReq_misses::total 29 # number of ReadExReq misses
815 system.cpu.l2cache.demand_misses::cpu.inst 70 # number of demand (read+write) misses
816 system.cpu.l2cache.demand_misses::cpu.data 98 # number of demand (read+write) misses
817 system.cpu.l2cache.demand_misses::total 168 # number of demand (read+write) misses
818 system.cpu.l2cache.overall_misses::cpu.inst 70 # number of overall misses
819 system.cpu.l2cache.overall_misses::cpu.data 98 # number of overall misses
820 system.cpu.l2cache.overall_misses::total 168 # number of overall misses
821 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 4724750 # number of ReadReq miss cycles
822 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5170750 # number of ReadReq miss cycles
823 system.cpu.l2cache.ReadReq_miss_latency::total 9895500 # number of ReadReq miss cycles
824 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2577500 # number of ReadExReq miss cycles
825 system.cpu.l2cache.ReadExReq_miss_latency::total 2577500 # number of ReadExReq miss cycles
826 system.cpu.l2cache.demand_miss_latency::cpu.inst 4724750 # number of demand (read+write) miss cycles
827 system.cpu.l2cache.demand_miss_latency::cpu.data 7748250 # number of demand (read+write) miss cycles
828 system.cpu.l2cache.demand_miss_latency::total 12473000 # number of demand (read+write) miss cycles
829 system.cpu.l2cache.overall_miss_latency::cpu.inst 4724750 # number of overall miss cycles
830 system.cpu.l2cache.overall_miss_latency::cpu.data 7748250 # number of overall miss cycles
831 system.cpu.l2cache.overall_miss_latency::total 12473000 # number of overall miss cycles
832 system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
833 system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
834 system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses)
835 system.cpu.l2cache.ReadExReq_accesses::cpu.data 40 # number of ReadExReq accesses(hits+misses)
836 system.cpu.l2cache.ReadExReq_accesses::total 40 # number of ReadExReq accesses(hits+misses)
837 system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
838 system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
839 system.cpu.l2cache.demand_accesses::total 448 # number of demand (read+write) accesses
840 system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
841 system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
842 system.cpu.l2cache.overall_accesses::total 448 # number of overall (read+write) accesses
843 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.230263 # miss rate for ReadReq accesses
844 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.663462 # miss rate for ReadReq accesses
845 system.cpu.l2cache.ReadReq_miss_rate::total 0.340686 # miss rate for ReadReq accesses
846 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.725000 # miss rate for ReadExReq accesses
847 system.cpu.l2cache.ReadExReq_miss_rate::total 0.725000 # miss rate for ReadExReq accesses
848 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.230263 # miss rate for demand accesses
849 system.cpu.l2cache.demand_miss_rate::cpu.data 0.680556 # miss rate for demand accesses
850 system.cpu.l2cache.demand_miss_rate::total 0.375000 # miss rate for demand accesses
851 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.230263 # miss rate for overall accesses
852 system.cpu.l2cache.overall_miss_rate::cpu.data 0.680556 # miss rate for overall accesses
853 system.cpu.l2cache.overall_miss_rate::total 0.375000 # miss rate for overall accesses
854 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67496.428571 # average ReadReq miss latency
855 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74938.405797 # average ReadReq miss latency
856 system.cpu.l2cache.ReadReq_avg_miss_latency::total 71190.647482 # average ReadReq miss latency
857 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88879.310345 # average ReadExReq miss latency
858 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88879.310345 # average ReadExReq miss latency
859 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency
860 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency
861 system.cpu.l2cache.demand_avg_miss_latency::total 74244.047619 # average overall miss latency
862 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency
863 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency
864 system.cpu.l2cache.overall_avg_miss_latency::total 74244.047619 # average overall miss latency
865 system.cpu.l2cache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked
866 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
867 system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked
868 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
869 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.823529 # average number of cycles each access was blocked
870 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
871 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
872 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
873 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
874 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
875 system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
876 system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
877 system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
878 system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
879 system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
880 system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
881 system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
882 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 59 # number of ReadReq MSHR misses
883 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
884 system.cpu.l2cache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses
885 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 603 # number of HardPFReq MSHR misses
886 system.cpu.l2cache.HardPFReq_mshr_misses::total 603 # number of HardPFReq MSHR misses
887 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29 # number of ReadExReq MSHR misses
888 system.cpu.l2cache.ReadExReq_mshr_misses::total 29 # number of ReadExReq MSHR misses
889 system.cpu.l2cache.demand_mshr_misses::cpu.inst 59 # number of demand (read+write) MSHR misses
890 system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses
891 system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses
892 system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses
893 system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses
894 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses
895 system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses
896 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles
897 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # number of ReadReq MSHR miss cycles
898 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8457000 # number of ReadReq MSHR miss cycles
899 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of HardPFReq MSHR miss cycles
900 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 49457864 # number of HardPFReq MSHR miss cycles
901 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2337500 # number of ReadExReq MSHR miss cycles
902 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2337500 # number of ReadExReq MSHR miss cycles
903 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3978500 # number of demand (read+write) MSHR miss cycles
904 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6816000 # number of demand (read+write) MSHR miss cycles
905 system.cpu.l2cache.demand_mshr_miss_latency::total 10794500 # number of demand (read+write) MSHR miss cycles
906 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3978500 # number of overall MSHR miss cycles
907 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6816000 # number of overall MSHR miss cycles
908 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles
909 system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles
910 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses
911 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses
912 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses
913 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
914 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
915 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses
916 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses
917 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses
918 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses
919 system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses
920 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses
921 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses
922 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
923 system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses
924 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency
925 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency
926 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency
927 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency
928 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency
929 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency
930 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency
931 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency
932 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency
933 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency
934 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency
935 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency
936 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency
937 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency
938 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
939 system.cpu.dcache.tags.replacements 1 # number of replacements
940 system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use
941 system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks.
942 system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
943 system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks.
944 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
945 system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor
946 system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy
947 system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy
948 system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
949 system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
950 system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
951 system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id
952 system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses
953 system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses
954 system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits
955 system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits
956 system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
957 system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
958 system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
959 system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
960 system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
961 system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
962 system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits
963 system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits
964 system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits
965 system.cpu.dcache.overall_hits::total 1873 # number of overall hits
966 system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses
967 system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses
968 system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses
969 system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses
970 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
971 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
972 system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses
973 system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses
974 system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses
975 system.cpu.dcache.overall_misses::total 392 # number of overall misses
976 system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles
977 system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles
978 system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles
979 system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles
980 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles
981 system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles
982 system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles
983 system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles
984 system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles
985 system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles
986 system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses)
987 system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses)
988 system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
989 system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
990 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
991 system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
992 system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
993 system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
994 system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses
995 system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses
996 system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses
997 system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses
998 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses
999 system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses
1000 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses
1001 system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses
1002 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
1003 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
1004 system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses
1005 system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses
1006 system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses
1007 system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses
1008 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency
1009 system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency
1010 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency
1011 system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency
1012 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency
1013 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency
1014 system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency
1015 system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency
1016 system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency
1017 system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency
1018 system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked
1019 system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked
1020 system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
1021 system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
1022 system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked
1023 system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked
1024 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1025 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1026 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits
1027 system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits
1028 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits
1029 system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits
1030 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
1031 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
1032 system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits
1033 system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
1034 system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits
1035 system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits
1036 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
1037 system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
1038 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses
1039 system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses
1040 system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
1041 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
1042 system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
1043 system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
1044 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles
1045 system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles
1046 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles
1047 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles
1048 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles
1049 system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles
1050 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles
1051 system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles
1052 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses
1053 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses
1054 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses
1055 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses
1056 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses
1057 system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses
1058 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses
1059 system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses
1060 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency
1061 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency
1062 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency
1063 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency
1064 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency
1065 system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency
1066 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency
1067 system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency
1068 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1070 ---------- End Simulation Statistics ----------
projects / gem5.git / blob