tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 init_param=0
  14 kernel=
  15 load_addr_mask=1099511627775
  16 mem_mode=atomic
  17 memories=system.physmem
  18 num_work_ids=16
  19 physmem=system.physmem
  20 readfile=
  21 symbolfile=
  22 work_begin_ckpt_count=0
  23 work_begin_cpu_id_exit=-1
  24 work_begin_exit_count=0
  25 work_cpus_ckpt_count=0
  26 work_end_ckpt_count=0
  27 work_end_exit_count=0
  28 work_item_id=-1
  29 system_port=system.membus.slave[0]
  30
  31 [system.cpu]
  32 type=DerivO3CPU
  33 children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
  34 BTBEntries=4096
  35 BTBTagSize=16
  36 LFSTSize=1024
  37 LQEntries=32
  38 LSQCheckLoads=true
  39 LSQDepCheckShift=4
  40 RASSize=16
  41 SQEntries=32
  42 SSITSize=1024
  43 activity=0
  44 backComSize=5
  45 cachePorts=200
  46 checker=system.cpu.checker
  47 choiceCtrBits=2
  48 choicePredictorSize=8192
  49 clock=500
  50 commitToDecodeDelay=1
  51 commitToFetchDelay=1
  52 commitToIEWDelay=1
  53 commitToRenameDelay=1
  54 commitWidth=8
  55 cpu_id=0
  56 decodeToFetchDelay=1
  57 decodeToRenameDelay=1
  58 decodeWidth=8
  59 defer_registration=false
  60 dispatchWidth=8
  61 do_checkpoint_insts=true
  62 do_quiesce=true
  63 do_statistics_insts=true
  64 dtb=system.cpu.dtb
  65 fetchToDecodeDelay=1
  66 fetchTrapLatency=1
  67 fetchWidth=8
  68 forwardComSize=5
  69 fuPool=system.cpu.fuPool
  70 function_trace=false
  71 function_trace_start=0
  72 globalCtrBits=2
  73 globalHistoryBits=13
  74 globalPredictorSize=8192
  75 iewToCommitDelay=1
  76 iewToDecodeDelay=1
  77 iewToFetchDelay=1
  78 iewToRenameDelay=1
  79 instShiftAmt=2
  80 interrupts=system.cpu.interrupts
  81 issueToExecuteDelay=1
  82 issueWidth=8
  83 itb=system.cpu.itb
  84 localCtrBits=2
  85 localHistoryBits=11
  86 localHistoryTableSize=2048
  87 localPredictorSize=2048
  88 max_insts_all_threads=0
  89 max_insts_any_thread=0
  90 max_loads_all_threads=0
  91 max_loads_any_thread=0
  92 needsTSO=false
  93 numIQEntries=64
  94 numPhysFloatRegs=256
  95 numPhysIntRegs=256
  96 numROBEntries=192
  97 numRobs=1
  98 numThreads=1
  99 phase=0
 100 predType=tournament
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 smtCommitPolicy=RoundRobin
 109 smtFetchPolicy=SingleThread
 110 smtIQPolicy=Partitioned
 111 smtIQThreshold=100
 112 smtLSQPolicy=Partitioned
 113 smtLSQThreshold=100
 114 smtNumFetchingThreads=1
 115 smtROBPolicy=Partitioned
 116 smtROBThreshold=100
 117 squashWidth=8
 118 store_set_clear_period=250000
 119 system=system
 120 tracer=system.cpu.tracer
 121 trapLatency=13
 122 wbDepth=1
 123 wbWidth=8
 124 workload=system.cpu.workload
 125 dcache_port=system.cpu.dcache.cpu_side
 126 icache_port=system.cpu.icache.cpu_side
 127
 128 [system.cpu.checker]
 129 type=O3Checker
 130 children=dtb itb tracer
 131 checker=Null
 132 clock=1
 133 cpu_id=-1
 134 defer_registration=false
 135 do_checkpoint_insts=true
 136 do_quiesce=true
 137 do_statistics_insts=true
 138 dtb=system.cpu.checker.dtb
 139 exitOnError=false
 140 function_trace=false
 141 function_trace_start=0
 142 interrupts=Null
 143 itb=system.cpu.checker.itb
 144 max_insts_all_threads=0
 145 max_insts_any_thread=0
 146 max_loads_all_threads=0
 147 max_loads_any_thread=0
 148 numThreads=1
 149 phase=0
 150 profile=0
 151 progress_interval=0
 152 system=system
 153 tracer=system.cpu.checker.tracer
 154 updateOnError=true
 155 warnOnlyOnLoadError=true
 156 workload=system.cpu.workload
 157
 158 [system.cpu.checker.dtb]
 159 type=ArmTLB
 160 children=walker
 161 size=64
 162 walker=system.cpu.checker.dtb.walker
 163
 164 [system.cpu.checker.dtb.walker]
 165 type=ArmTableWalker
 166 max_backoff=100000
 167 min_backoff=0
 168 sys=system
 169 port=system.cpu.toL2Bus.slave[5]
 170
 171 [system.cpu.checker.itb]
 172 type=ArmTLB
 173 children=walker
 174 size=64
 175 walker=system.cpu.checker.itb.walker
 176
 177 [system.cpu.checker.itb.walker]
 178 type=ArmTableWalker
 179 max_backoff=100000
 180 min_backoff=0
 181 sys=system
 182 port=system.cpu.toL2Bus.slave[4]
 183
 184 [system.cpu.checker.tracer]
 185 type=ExeTracer
 186
 187 [system.cpu.dcache]
 188 type=BaseCache
 189 addr_ranges=0:18446744073709551615
 190 assoc=2
 191 block_size=64
 192 forward_snoops=true
 193 hash_delay=1
 194 is_top_level=true
 195 latency=1000
 196 max_miss_count=0
 197 mshrs=10
 198 prefetch_on_access=false
 199 prefetcher=Null
 200 prioritizeRequests=false
 201 repl=Null
 202 size=262144
 203 subblock_size=0
 204 system=system
 205 tgts_per_mshr=20
 206 trace_addr=0
 207 two_queue=false
 208 write_buffers=8
 209 cpu_side=system.cpu.dcache_port
 210 mem_side=system.cpu.toL2Bus.slave[1]
 211
 212 [system.cpu.dtb]
 213 type=ArmTLB
 214 children=walker
 215 size=64
 216 walker=system.cpu.dtb.walker
 217
 218 [system.cpu.dtb.walker]
 219 type=ArmTableWalker
 220 max_backoff=100000
 221 min_backoff=0
 222 sys=system
 223 port=system.cpu.toL2Bus.slave[3]
 224
 225 [system.cpu.fuPool]
 226 type=FUPool
 227 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 228 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 229
 230 [system.cpu.fuPool.FUList0]
 231 type=FUDesc
 232 children=opList
 233 count=6
 234 opList=system.cpu.fuPool.FUList0.opList
 235
 236 [system.cpu.fuPool.FUList0.opList]
 237 type=OpDesc
 238 issueLat=1
 239 opClass=IntAlu
 240 opLat=1
 241
 242 [system.cpu.fuPool.FUList1]
 243 type=FUDesc
 244 children=opList0 opList1
 245 count=2
 246 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 247
 248 [system.cpu.fuPool.FUList1.opList0]
 249 type=OpDesc
 250 issueLat=1
 251 opClass=IntMult
 252 opLat=3
 253
 254 [system.cpu.fuPool.FUList1.opList1]
 255 type=OpDesc
 256 issueLat=19
 257 opClass=IntDiv
 258 opLat=20
 259
 260 [system.cpu.fuPool.FUList2]
 261 type=FUDesc
 262 children=opList0 opList1 opList2
 263 count=4
 264 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 265
 266 [system.cpu.fuPool.FUList2.opList0]
 267 type=OpDesc
 268 issueLat=1
 269 opClass=FloatAdd
 270 opLat=2
 271
 272 [system.cpu.fuPool.FUList2.opList1]
 273 type=OpDesc
 274 issueLat=1
 275 opClass=FloatCmp
 276 opLat=2
 277
 278 [system.cpu.fuPool.FUList2.opList2]
 279 type=OpDesc
 280 issueLat=1
 281 opClass=FloatCvt
 282 opLat=2
 283
 284 [system.cpu.fuPool.FUList3]
 285 type=FUDesc
 286 children=opList0 opList1 opList2
 287 count=2
 288 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 289
 290 [system.cpu.fuPool.FUList3.opList0]
 291 type=OpDesc
 292 issueLat=1
 293 opClass=FloatMult
 294 opLat=4
 295
 296 [system.cpu.fuPool.FUList3.opList1]
 297 type=OpDesc
 298 issueLat=12
 299 opClass=FloatDiv
 300 opLat=12
 301
 302 [system.cpu.fuPool.FUList3.opList2]
 303 type=OpDesc
 304 issueLat=24
 305 opClass=FloatSqrt
 306 opLat=24
 307
 308 [system.cpu.fuPool.FUList4]
 309 type=FUDesc
 310 children=opList
 311 count=0
 312 opList=system.cpu.fuPool.FUList4.opList
 313
 314 [system.cpu.fuPool.FUList4.opList]
 315 type=OpDesc
 316 issueLat=1
 317 opClass=MemRead
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5]
 321 type=FUDesc
 322 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 323 count=4
 324 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 325
 326 [system.cpu.fuPool.FUList5.opList00]
 327 type=OpDesc
 328 issueLat=1
 329 opClass=SimdAdd
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList01]
 333 type=OpDesc
 334 issueLat=1
 335 opClass=SimdAddAcc
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList02]
 339 type=OpDesc
 340 issueLat=1
 341 opClass=SimdAlu
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList03]
 345 type=OpDesc
 346 issueLat=1
 347 opClass=SimdCmp
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList04]
 351 type=OpDesc
 352 issueLat=1
 353 opClass=SimdCvt
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList05]
 357 type=OpDesc
 358 issueLat=1
 359 opClass=SimdMisc
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList06]
 363 type=OpDesc
 364 issueLat=1
 365 opClass=SimdMult
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList07]
 369 type=OpDesc
 370 issueLat=1
 371 opClass=SimdMultAcc
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList5.opList08]
 375 type=OpDesc
 376 issueLat=1
 377 opClass=SimdShift
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList09]
 381 type=OpDesc
 382 issueLat=1
 383 opClass=SimdShiftAcc
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList5.opList10]
 387 type=OpDesc
 388 issueLat=1
 389 opClass=SimdSqrt
 390 opLat=1
 391
 392 [system.cpu.fuPool.FUList5.opList11]
 393 type=OpDesc
 394 issueLat=1
 395 opClass=SimdFloatAdd
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList5.opList12]
 399 type=OpDesc
 400 issueLat=1
 401 opClass=SimdFloatAlu
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList5.opList13]
 405 type=OpDesc
 406 issueLat=1
 407 opClass=SimdFloatCmp
 408 opLat=1
 409
 410 [system.cpu.fuPool.FUList5.opList14]
 411 type=OpDesc
 412 issueLat=1
 413 opClass=SimdFloatCvt
 414 opLat=1
 415
 416 [system.cpu.fuPool.FUList5.opList15]
 417 type=OpDesc
 418 issueLat=1
 419 opClass=SimdFloatDiv
 420 opLat=1
 421
 422 [system.cpu.fuPool.FUList5.opList16]
 423 type=OpDesc
 424 issueLat=1
 425 opClass=SimdFloatMisc
 426 opLat=1
 427
 428 [system.cpu.fuPool.FUList5.opList17]
 429 type=OpDesc
 430 issueLat=1
 431 opClass=SimdFloatMult
 432 opLat=1
 433
 434 [system.cpu.fuPool.FUList5.opList18]
 435 type=OpDesc
 436 issueLat=1
 437 opClass=SimdFloatMultAcc
 438 opLat=1
 439
 440 [system.cpu.fuPool.FUList5.opList19]
 441 type=OpDesc
 442 issueLat=1
 443 opClass=SimdFloatSqrt
 444 opLat=1
 445
 446 [system.cpu.fuPool.FUList6]
 447 type=FUDesc
 448 children=opList
 449 count=0
 450 opList=system.cpu.fuPool.FUList6.opList
 451
 452 [system.cpu.fuPool.FUList6.opList]
 453 type=OpDesc
 454 issueLat=1
 455 opClass=MemWrite
 456 opLat=1
 457
 458 [system.cpu.fuPool.FUList7]
 459 type=FUDesc
 460 children=opList0 opList1
 461 count=4
 462 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 463
 464 [system.cpu.fuPool.FUList7.opList0]
 465 type=OpDesc
 466 issueLat=1
 467 opClass=MemRead
 468 opLat=1
 469
 470 [system.cpu.fuPool.FUList7.opList1]
 471 type=OpDesc
 472 issueLat=1
 473 opClass=MemWrite
 474 opLat=1
 475
 476 [system.cpu.fuPool.FUList8]
 477 type=FUDesc
 478 children=opList
 479 count=1
 480 opList=system.cpu.fuPool.FUList8.opList
 481
 482 [system.cpu.fuPool.FUList8.opList]
 483 type=OpDesc
 484 issueLat=3
 485 opClass=IprAccess
 486 opLat=3
 487
 488 [system.cpu.icache]
 489 type=BaseCache
 490 addr_ranges=0:18446744073709551615
 491 assoc=2
 492 block_size=64
 493 forward_snoops=true
 494 hash_delay=1
 495 is_top_level=true
 496 latency=1000
 497 max_miss_count=0
 498 mshrs=10
 499 prefetch_on_access=false
 500 prefetcher=Null
 501 prioritizeRequests=false
 502 repl=Null
 503 size=131072
 504 subblock_size=0
 505 system=system
 506 tgts_per_mshr=20
 507 trace_addr=0
 508 two_queue=false
 509 write_buffers=8
 510 cpu_side=system.cpu.icache_port
 511 mem_side=system.cpu.toL2Bus.slave[0]
 512
 513 [system.cpu.interrupts]
 514 type=ArmInterrupts
 515
 516 [system.cpu.itb]
 517 type=ArmTLB
 518 children=walker
 519 size=64
 520 walker=system.cpu.itb.walker
 521
 522 [system.cpu.itb.walker]
 523 type=ArmTableWalker
 524 max_backoff=100000
 525 min_backoff=0
 526 sys=system
 527 port=system.cpu.toL2Bus.slave[2]
 528
 529 [system.cpu.l2cache]
 530 type=BaseCache
 531 addr_ranges=0:18446744073709551615
 532 assoc=2
 533 block_size=64
 534 forward_snoops=true
 535 hash_delay=1
 536 is_top_level=false
 537 latency=1000
 538 max_miss_count=0
 539 mshrs=10
 540 prefetch_on_access=false
 541 prefetcher=Null
 542 prioritizeRequests=false
 543 repl=Null
 544 size=2097152
 545 subblock_size=0
 546 system=system
 547 tgts_per_mshr=5
 548 trace_addr=0
 549 two_queue=false
 550 write_buffers=8
 551 cpu_side=system.cpu.toL2Bus.master[0]
 552 mem_side=system.membus.slave[1]
 553
 554 [system.cpu.toL2Bus]
 555 type=Bus
 556 block_size=64
 557 bus_id=0
 558 clock=1000
 559 header_cycles=1
 560 use_default_range=false
 561 width=64
 562 master=system.cpu.l2cache.cpu_side
 563 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 564
 565 [system.cpu.tracer]
 566 type=ExeTracer
 567
 568 [system.cpu.workload]
 569 type=LiveProcess
 570 cmd=hello
 571 cwd=
 572 egid=100
 573 env=
 574 errout=cerr
 575 euid=100
 576 executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
 577 gid=100
 578 input=cin
 579 max_stack_size=67108864
 580 output=cout
 581 pid=100
 582 ppid=99
 583 simpoint=0
 584 system=system
 585 uid=100
 586
 587 [system.membus]
 588 type=Bus
 589 block_size=64
 590 bus_id=0
 591 clock=1000
 592 header_cycles=1
 593 use_default_range=false
 594 width=64
 595 master=system.physmem.port[0]
 596 slave=system.system_port system.cpu.l2cache.mem_side
 597
 598 [system.physmem]
 599 type=PhysicalMemory
 600 file=
 601 latency=30000
 602 latency_var=0
 603 null=false
 604 range=0:134217727
 605 zero=false
 606 port=system.membus.master[0]
 607