tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 multi_thread=false
  28 num_work_ids=16
  29 readfile=
  30 symbolfile=
  31 work_begin_ckpt_count=0
  32 work_begin_cpu_id_exit=-1
  33 work_begin_exit_count=0
  34 work_cpus_ckpt_count=0
  35 work_end_ckpt_count=0
  36 work_end_exit_count=0
  37 work_item_id=-1
  38 system_port=system.membus.slave[0]
  39
  40 [system.clk_domain]
  41 type=SrcClockDomain
  42 clock=1000
  43 domain_id=-1
  44 eventq_index=0
  45 init_perf_level=0
  46 voltage_domain=system.voltage_domain
  47
  48 [system.cpu]
  49 type=DerivO3CPU
  50 children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  51 LFSTSize=1024
  52 LQEntries=32
  53 LSQCheckLoads=true
  54 LSQDepCheckShift=4
  55 SQEntries=32
  56 SSITSize=1024
  57 activity=0
  58 backComSize=5
  59 branchPred=system.cpu.branchPred
  60 cachePorts=200
  61 checker=system.cpu.checker
  62 clk_domain=system.cpu_clk_domain
  63 commitToDecodeDelay=1
  64 commitToFetchDelay=1
  65 commitToIEWDelay=1
  66 commitToRenameDelay=1
  67 commitWidth=8
  68 cpu_id=0
  69 decodeToFetchDelay=1
  70 decodeToRenameDelay=1
  71 decodeWidth=8
  72 dispatchWidth=8
  73 do_checkpoint_insts=true
  74 do_quiesce=true
  75 do_statistics_insts=true
  76 dstage2_mmu=system.cpu.dstage2_mmu
  77 dtb=system.cpu.dtb
  78 eventq_index=0
  79 fetchBufferSize=64
  80 fetchQueueSize=32
  81 fetchToDecodeDelay=1
  82 fetchTrapLatency=1
  83 fetchWidth=8
  84 forwardComSize=5
  85 fuPool=system.cpu.fuPool
  86 function_trace=false
  87 function_trace_start=0
  88 iewToCommitDelay=1
  89 iewToDecodeDelay=1
  90 iewToFetchDelay=1
  91 iewToRenameDelay=1
  92 interrupts=system.cpu.interrupts
  93 isa=system.cpu.isa
  94 issueToExecuteDelay=1
  95 issueWidth=8
  96 istage2_mmu=system.cpu.istage2_mmu
  97 itb=system.cpu.itb
  98 max_insts_all_threads=0
  99 max_insts_any_thread=0
 100 max_loads_all_threads=0
 101 max_loads_any_thread=0
 102 needsTSO=false
 103 numIQEntries=64
 104 numPhysCCRegs=1280
 105 numPhysFloatRegs=256
 106 numPhysIntRegs=256
 107 numROBEntries=192
 108 numRobs=1
 109 numThreads=1
 110 profile=0
 111 progress_interval=0
 112 renameToDecodeDelay=1
 113 renameToFetchDelay=1
 114 renameToIEWDelay=2
 115 renameToROBDelay=1
 116 renameWidth=8
 117 simpoint_start_insts=
 118 smtCommitPolicy=RoundRobin
 119 smtFetchPolicy=SingleThread
 120 smtIQPolicy=Partitioned
 121 smtIQThreshold=100
 122 smtLSQPolicy=Partitioned
 123 smtLSQThreshold=100
 124 smtNumFetchingThreads=1
 125 smtROBPolicy=Partitioned
 126 smtROBThreshold=100
 127 socket_id=0
 128 squashWidth=8
 129 store_set_clear_period=250000
 130 switched_out=false
 131 system=system
 132 tracer=system.cpu.tracer
 133 trapLatency=13
 134 wbWidth=8
 135 workload=system.cpu.workload
 136 dcache_port=system.cpu.dcache.cpu_side
 137 icache_port=system.cpu.icache.cpu_side
 138
 139 [system.cpu.branchPred]
 140 type=TournamentBP
 141 BTBEntries=4096
 142 BTBTagSize=16
 143 RASSize=16
 144 choiceCtrBits=2
 145 choicePredictorSize=8192
 146 eventq_index=0
 147 globalCtrBits=2
 148 globalPredictorSize=8192
 149 instShiftAmt=2
 150 localCtrBits=2
 151 localHistoryTableSize=2048
 152 localPredictorSize=2048
 153 numThreads=1
 154
 155 [system.cpu.checker]
 156 type=O3Checker
 157 children=dstage2_mmu dtb isa istage2_mmu itb tracer
 158 checker=Null
 159 clk_domain=system.cpu_clk_domain
 160 cpu_id=0
 161 do_checkpoint_insts=true
 162 do_quiesce=true
 163 do_statistics_insts=true
 164 dstage2_mmu=system.cpu.checker.dstage2_mmu
 165 dtb=system.cpu.checker.dtb
 166 eventq_index=0
 167 exitOnError=false
 168 function_trace=false
 169 function_trace_start=0
 170 interrupts=
 171 isa=system.cpu.checker.isa
 172 istage2_mmu=system.cpu.checker.istage2_mmu
 173 itb=system.cpu.checker.itb
 174 max_insts_all_threads=0
 175 max_insts_any_thread=0
 176 max_loads_all_threads=0
 177 max_loads_any_thread=0
 178 numThreads=1
 179 profile=0
 180 progress_interval=0
 181 simpoint_start_insts=
 182 socket_id=0
 183 switched_out=false
 184 system=system
 185 tracer=system.cpu.checker.tracer
 186 updateOnError=true
 187 warnOnlyOnLoadError=true
 188 workload=system.cpu.workload
 189
 190 [system.cpu.checker.dstage2_mmu]
 191 type=ArmStage2MMU
 192 children=stage2_tlb
 193 eventq_index=0
 194 stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
 195 sys=system
 196 tlb=system.cpu.checker.dtb
 197
 198 [system.cpu.checker.dstage2_mmu.stage2_tlb]
 199 type=ArmTLB
 200 children=walker
 201 eventq_index=0
 202 is_stage2=true
 203 size=32
 204 walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
 205
 206 [system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
 207 type=ArmTableWalker
 208 clk_domain=system.cpu_clk_domain
 209 eventq_index=0
 210 is_stage2=true
 211 num_squash_per_cycle=2
 212 sys=system
 213
 214 [system.cpu.checker.dtb]
 215 type=ArmTLB
 216 children=walker
 217 eventq_index=0
 218 is_stage2=false
 219 size=64
 220 walker=system.cpu.checker.dtb.walker
 221
 222 [system.cpu.checker.dtb.walker]
 223 type=ArmTableWalker
 224 clk_domain=system.cpu_clk_domain
 225 eventq_index=0
 226 is_stage2=false
 227 num_squash_per_cycle=2
 228 sys=system
 229 port=system.cpu.toL2Bus.slave[5]
 230
 231 [system.cpu.checker.isa]
 232 type=ArmISA
 233 decoderFlavour=Generic
 234 eventq_index=0
 235 fpsid=1090793632
 236 id_aa64afr0_el1=0
 237 id_aa64afr1_el1=0
 238 id_aa64dfr0_el1=1052678
 239 id_aa64dfr1_el1=0
 240 id_aa64isar0_el1=0
 241 id_aa64isar1_el1=0
 242 id_aa64mmfr0_el1=15728642
 243 id_aa64mmfr1_el1=0
 244 id_aa64pfr0_el1=17
 245 id_aa64pfr1_el1=0
 246 id_isar0=34607377
 247 id_isar1=34677009
 248 id_isar2=555950401
 249 id_isar3=17899825
 250 id_isar4=268501314
 251 id_isar5=0
 252 id_mmfr0=270536963
 253 id_mmfr1=0
 254 id_mmfr2=19070976
 255 id_mmfr3=34611729
 256 id_pfr0=49
 257 id_pfr1=4113
 258 midr=1091551472
 259 pmu=Null
 260 system=system
 261
 262 [system.cpu.checker.istage2_mmu]
 263 type=ArmStage2MMU
 264 children=stage2_tlb
 265 eventq_index=0
 266 stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
 267 sys=system
 268 tlb=system.cpu.checker.itb
 269
 270 [system.cpu.checker.istage2_mmu.stage2_tlb]
 271 type=ArmTLB
 272 children=walker
 273 eventq_index=0
 274 is_stage2=true
 275 size=32
 276 walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker
 277
 278 [system.cpu.checker.istage2_mmu.stage2_tlb.walker]
 279 type=ArmTableWalker
 280 clk_domain=system.cpu_clk_domain
 281 eventq_index=0
 282 is_stage2=true
 283 num_squash_per_cycle=2
 284 sys=system
 285
 286 [system.cpu.checker.itb]
 287 type=ArmTLB
 288 children=walker
 289 eventq_index=0
 290 is_stage2=false
 291 size=64
 292 walker=system.cpu.checker.itb.walker
 293
 294 [system.cpu.checker.itb.walker]
 295 type=ArmTableWalker
 296 clk_domain=system.cpu_clk_domain
 297 eventq_index=0
 298 is_stage2=false
 299 num_squash_per_cycle=2
 300 sys=system
 301 port=system.cpu.toL2Bus.slave[4]
 302
 303 [system.cpu.checker.tracer]
 304 type=ExeTracer
 305 eventq_index=0
 306
 307 [system.cpu.dcache]
 308 type=Cache
 309 children=tags
 310 addr_ranges=0:18446744073709551615
 311 assoc=2
 312 clk_domain=system.cpu_clk_domain
 313 clusivity=mostly_incl
 314 demand_mshr_reserve=1
 315 eventq_index=0
 316 forward_snoops=true
 317 hit_latency=2
 318 is_read_only=false
 319 max_miss_count=0
 320 mshrs=4
 321 prefetch_on_access=false
 322 prefetcher=Null
 323 response_latency=2
 324 sequential_access=false
 325 size=262144
 326 system=system
 327 tags=system.cpu.dcache.tags
 328 tgts_per_mshr=20
 329 write_buffers=8
 330 writeback_clean=false
 331 cpu_side=system.cpu.dcache_port
 332 mem_side=system.cpu.toL2Bus.slave[1]
 333
 334 [system.cpu.dcache.tags]
 335 type=LRU
 336 assoc=2
 337 block_size=64
 338 clk_domain=system.cpu_clk_domain
 339 eventq_index=0
 340 hit_latency=2
 341 sequential_access=false
 342 size=262144
 343
 344 [system.cpu.dstage2_mmu]
 345 type=ArmStage2MMU
 346 children=stage2_tlb
 347 eventq_index=0
 348 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 349 sys=system
 350 tlb=system.cpu.dtb
 351
 352 [system.cpu.dstage2_mmu.stage2_tlb]
 353 type=ArmTLB
 354 children=walker
 355 eventq_index=0
 356 is_stage2=true
 357 size=32
 358 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 359
 360 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 361 type=ArmTableWalker
 362 clk_domain=system.cpu_clk_domain
 363 eventq_index=0
 364 is_stage2=true
 365 num_squash_per_cycle=2
 366 sys=system
 367
 368 [system.cpu.dtb]
 369 type=ArmTLB
 370 children=walker
 371 eventq_index=0
 372 is_stage2=false
 373 size=64
 374 walker=system.cpu.dtb.walker
 375
 376 [system.cpu.dtb.walker]
 377 type=ArmTableWalker
 378 clk_domain=system.cpu_clk_domain
 379 eventq_index=0
 380 is_stage2=false
 381 num_squash_per_cycle=2
 382 sys=system
 383 port=system.cpu.toL2Bus.slave[3]
 384
 385 [system.cpu.fuPool]
 386 type=FUPool
 387 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 388 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 389 eventq_index=0
 390
 391 [system.cpu.fuPool.FUList0]
 392 type=FUDesc
 393 children=opList
 394 count=6
 395 eventq_index=0
 396 opList=system.cpu.fuPool.FUList0.opList
 397
 398 [system.cpu.fuPool.FUList0.opList]
 399 type=OpDesc
 400 eventq_index=0
 401 opClass=IntAlu
 402 opLat=1
 403 pipelined=true
 404
 405 [system.cpu.fuPool.FUList1]
 406 type=FUDesc
 407 children=opList0 opList1
 408 count=2
 409 eventq_index=0
 410 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 411
 412 [system.cpu.fuPool.FUList1.opList0]
 413 type=OpDesc
 414 eventq_index=0
 415 opClass=IntMult
 416 opLat=3
 417 pipelined=true
 418
 419 [system.cpu.fuPool.FUList1.opList1]
 420 type=OpDesc
 421 eventq_index=0
 422 opClass=IntDiv
 423 opLat=20
 424 pipelined=false
 425
 426 [system.cpu.fuPool.FUList2]
 427 type=FUDesc
 428 children=opList0 opList1 opList2
 429 count=4
 430 eventq_index=0
 431 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 432
 433 [system.cpu.fuPool.FUList2.opList0]
 434 type=OpDesc
 435 eventq_index=0
 436 opClass=FloatAdd
 437 opLat=2
 438 pipelined=true
 439
 440 [system.cpu.fuPool.FUList2.opList1]
 441 type=OpDesc
 442 eventq_index=0
 443 opClass=FloatCmp
 444 opLat=2
 445 pipelined=true
 446
 447 [system.cpu.fuPool.FUList2.opList2]
 448 type=OpDesc
 449 eventq_index=0
 450 opClass=FloatCvt
 451 opLat=2
 452 pipelined=true
 453
 454 [system.cpu.fuPool.FUList3]
 455 type=FUDesc
 456 children=opList0 opList1 opList2
 457 count=2
 458 eventq_index=0
 459 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 460
 461 [system.cpu.fuPool.FUList3.opList0]
 462 type=OpDesc
 463 eventq_index=0
 464 opClass=FloatMult
 465 opLat=4
 466 pipelined=true
 467
 468 [system.cpu.fuPool.FUList3.opList1]
 469 type=OpDesc
 470 eventq_index=0
 471 opClass=FloatDiv
 472 opLat=12
 473 pipelined=false
 474
 475 [system.cpu.fuPool.FUList3.opList2]
 476 type=OpDesc
 477 eventq_index=0
 478 opClass=FloatSqrt
 479 opLat=24
 480 pipelined=false
 481
 482 [system.cpu.fuPool.FUList4]
 483 type=FUDesc
 484 children=opList
 485 count=0
 486 eventq_index=0
 487 opList=system.cpu.fuPool.FUList4.opList
 488
 489 [system.cpu.fuPool.FUList4.opList]
 490 type=OpDesc
 491 eventq_index=0
 492 opClass=MemRead
 493 opLat=1
 494 pipelined=true
 495
 496 [system.cpu.fuPool.FUList5]
 497 type=FUDesc
 498 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 499 count=4
 500 eventq_index=0
 501 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 502
 503 [system.cpu.fuPool.FUList5.opList00]
 504 type=OpDesc
 505 eventq_index=0
 506 opClass=SimdAdd
 507 opLat=1
 508 pipelined=true
 509
 510 [system.cpu.fuPool.FUList5.opList01]
 511 type=OpDesc
 512 eventq_index=0
 513 opClass=SimdAddAcc
 514 opLat=1
 515 pipelined=true
 516
 517 [system.cpu.fuPool.FUList5.opList02]
 518 type=OpDesc
 519 eventq_index=0
 520 opClass=SimdAlu
 521 opLat=1
 522 pipelined=true
 523
 524 [system.cpu.fuPool.FUList5.opList03]
 525 type=OpDesc
 526 eventq_index=0
 527 opClass=SimdCmp
 528 opLat=1
 529 pipelined=true
 530
 531 [system.cpu.fuPool.FUList5.opList04]
 532 type=OpDesc
 533 eventq_index=0
 534 opClass=SimdCvt
 535 opLat=1
 536 pipelined=true
 537
 538 [system.cpu.fuPool.FUList5.opList05]
 539 type=OpDesc
 540 eventq_index=0
 541 opClass=SimdMisc
 542 opLat=1
 543 pipelined=true
 544
 545 [system.cpu.fuPool.FUList5.opList06]
 546 type=OpDesc
 547 eventq_index=0
 548 opClass=SimdMult
 549 opLat=1
 550 pipelined=true
 551
 552 [system.cpu.fuPool.FUList5.opList07]
 553 type=OpDesc
 554 eventq_index=0
 555 opClass=SimdMultAcc
 556 opLat=1
 557 pipelined=true
 558
 559 [system.cpu.fuPool.FUList5.opList08]
 560 type=OpDesc
 561 eventq_index=0
 562 opClass=SimdShift
 563 opLat=1
 564 pipelined=true
 565
 566 [system.cpu.fuPool.FUList5.opList09]
 567 type=OpDesc
 568 eventq_index=0
 569 opClass=SimdShiftAcc
 570 opLat=1
 571 pipelined=true
 572
 573 [system.cpu.fuPool.FUList5.opList10]
 574 type=OpDesc
 575 eventq_index=0
 576 opClass=SimdSqrt
 577 opLat=1
 578 pipelined=true
 579
 580 [system.cpu.fuPool.FUList5.opList11]
 581 type=OpDesc
 582 eventq_index=0
 583 opClass=SimdFloatAdd
 584 opLat=1
 585 pipelined=true
 586
 587 [system.cpu.fuPool.FUList5.opList12]
 588 type=OpDesc
 589 eventq_index=0
 590 opClass=SimdFloatAlu
 591 opLat=1
 592 pipelined=true
 593
 594 [system.cpu.fuPool.FUList5.opList13]
 595 type=OpDesc
 596 eventq_index=0
 597 opClass=SimdFloatCmp
 598 opLat=1
 599 pipelined=true
 600
 601 [system.cpu.fuPool.FUList5.opList14]
 602 type=OpDesc
 603 eventq_index=0
 604 opClass=SimdFloatCvt
 605 opLat=1
 606 pipelined=true
 607
 608 [system.cpu.fuPool.FUList5.opList15]
 609 type=OpDesc
 610 eventq_index=0
 611 opClass=SimdFloatDiv
 612 opLat=1
 613 pipelined=true
 614
 615 [system.cpu.fuPool.FUList5.opList16]
 616 type=OpDesc
 617 eventq_index=0
 618 opClass=SimdFloatMisc
 619 opLat=1
 620 pipelined=true
 621
 622 [system.cpu.fuPool.FUList5.opList17]
 623 type=OpDesc
 624 eventq_index=0
 625 opClass=SimdFloatMult
 626 opLat=1
 627 pipelined=true
 628
 629 [system.cpu.fuPool.FUList5.opList18]
 630 type=OpDesc
 631 eventq_index=0
 632 opClass=SimdFloatMultAcc
 633 opLat=1
 634 pipelined=true
 635
 636 [system.cpu.fuPool.FUList5.opList19]
 637 type=OpDesc
 638 eventq_index=0
 639 opClass=SimdFloatSqrt
 640 opLat=1
 641 pipelined=true
 642
 643 [system.cpu.fuPool.FUList6]
 644 type=FUDesc
 645 children=opList
 646 count=0
 647 eventq_index=0
 648 opList=system.cpu.fuPool.FUList6.opList
 649
 650 [system.cpu.fuPool.FUList6.opList]
 651 type=OpDesc
 652 eventq_index=0
 653 opClass=MemWrite
 654 opLat=1
 655 pipelined=true
 656
 657 [system.cpu.fuPool.FUList7]
 658 type=FUDesc
 659 children=opList0 opList1
 660 count=4
 661 eventq_index=0
 662 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 663
 664 [system.cpu.fuPool.FUList7.opList0]
 665 type=OpDesc
 666 eventq_index=0
 667 opClass=MemRead
 668 opLat=1
 669 pipelined=true
 670
 671 [system.cpu.fuPool.FUList7.opList1]
 672 type=OpDesc
 673 eventq_index=0
 674 opClass=MemWrite
 675 opLat=1
 676 pipelined=true
 677
 678 [system.cpu.fuPool.FUList8]
 679 type=FUDesc
 680 children=opList
 681 count=1
 682 eventq_index=0
 683 opList=system.cpu.fuPool.FUList8.opList
 684
 685 [system.cpu.fuPool.FUList8.opList]
 686 type=OpDesc
 687 eventq_index=0
 688 opClass=IprAccess
 689 opLat=3
 690 pipelined=false
 691
 692 [system.cpu.icache]
 693 type=Cache
 694 children=tags
 695 addr_ranges=0:18446744073709551615
 696 assoc=2
 697 clk_domain=system.cpu_clk_domain
 698 clusivity=mostly_incl
 699 demand_mshr_reserve=1
 700 eventq_index=0
 701 forward_snoops=true
 702 hit_latency=2
 703 is_read_only=true
 704 max_miss_count=0
 705 mshrs=4
 706 prefetch_on_access=false
 707 prefetcher=Null
 708 response_latency=2
 709 sequential_access=false
 710 size=131072
 711 system=system
 712 tags=system.cpu.icache.tags
 713 tgts_per_mshr=20
 714 write_buffers=8
 715 writeback_clean=true
 716 cpu_side=system.cpu.icache_port
 717 mem_side=system.cpu.toL2Bus.slave[0]
 718
 719 [system.cpu.icache.tags]
 720 type=LRU
 721 assoc=2
 722 block_size=64
 723 clk_domain=system.cpu_clk_domain
 724 eventq_index=0
 725 hit_latency=2
 726 sequential_access=false
 727 size=131072
 728
 729 [system.cpu.interrupts]
 730 type=ArmInterrupts
 731 eventq_index=0
 732
 733 [system.cpu.isa]
 734 type=ArmISA
 735 decoderFlavour=Generic
 736 eventq_index=0
 737 fpsid=1090793632
 738 id_aa64afr0_el1=0
 739 id_aa64afr1_el1=0
 740 id_aa64dfr0_el1=1052678
 741 id_aa64dfr1_el1=0
 742 id_aa64isar0_el1=0
 743 id_aa64isar1_el1=0
 744 id_aa64mmfr0_el1=15728642
 745 id_aa64mmfr1_el1=0
 746 id_aa64pfr0_el1=17
 747 id_aa64pfr1_el1=0
 748 id_isar0=34607377
 749 id_isar1=34677009
 750 id_isar2=555950401
 751 id_isar3=17899825
 752 id_isar4=268501314
 753 id_isar5=0
 754 id_mmfr0=270536963
 755 id_mmfr1=0
 756 id_mmfr2=19070976
 757 id_mmfr3=34611729
 758 id_pfr0=49
 759 id_pfr1=4113
 760 midr=1091551472
 761 pmu=Null
 762 system=system
 763
 764 [system.cpu.istage2_mmu]
 765 type=ArmStage2MMU
 766 children=stage2_tlb
 767 eventq_index=0
 768 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 769 sys=system
 770 tlb=system.cpu.itb
 771
 772 [system.cpu.istage2_mmu.stage2_tlb]
 773 type=ArmTLB
 774 children=walker
 775 eventq_index=0
 776 is_stage2=true
 777 size=32
 778 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 779
 780 [system.cpu.istage2_mmu.stage2_tlb.walker]
 781 type=ArmTableWalker
 782 clk_domain=system.cpu_clk_domain
 783 eventq_index=0
 784 is_stage2=true
 785 num_squash_per_cycle=2
 786 sys=system
 787
 788 [system.cpu.itb]
 789 type=ArmTLB
 790 children=walker
 791 eventq_index=0
 792 is_stage2=false
 793 size=64
 794 walker=system.cpu.itb.walker
 795
 796 [system.cpu.itb.walker]
 797 type=ArmTableWalker
 798 clk_domain=system.cpu_clk_domain
 799 eventq_index=0
 800 is_stage2=false
 801 num_squash_per_cycle=2
 802 sys=system
 803 port=system.cpu.toL2Bus.slave[2]
 804
 805 [system.cpu.l2cache]
 806 type=Cache
 807 children=tags
 808 addr_ranges=0:18446744073709551615
 809 assoc=8
 810 clk_domain=system.cpu_clk_domain
 811 clusivity=mostly_incl
 812 demand_mshr_reserve=1
 813 eventq_index=0
 814 forward_snoops=true
 815 hit_latency=20
 816 is_read_only=false
 817 max_miss_count=0
 818 mshrs=20
 819 prefetch_on_access=false
 820 prefetcher=Null
 821 response_latency=20
 822 sequential_access=false
 823 size=2097152
 824 system=system
 825 tags=system.cpu.l2cache.tags
 826 tgts_per_mshr=12
 827 write_buffers=8
 828 writeback_clean=false
 829 cpu_side=system.cpu.toL2Bus.master[0]
 830 mem_side=system.membus.slave[1]
 831
 832 [system.cpu.l2cache.tags]
 833 type=LRU
 834 assoc=8
 835 block_size=64
 836 clk_domain=system.cpu_clk_domain
 837 eventq_index=0
 838 hit_latency=20
 839 sequential_access=false
 840 size=2097152
 841
 842 [system.cpu.toL2Bus]
 843 type=CoherentXBar
 844 children=snoop_filter
 845 clk_domain=system.cpu_clk_domain
 846 eventq_index=0
 847 forward_latency=0
 848 frontend_latency=1
 849 response_latency=1
 850 snoop_filter=system.cpu.toL2Bus.snoop_filter
 851 snoop_response_latency=1
 852 system=system
 853 use_default_range=false
 854 width=32
 855 master=system.cpu.l2cache.cpu_side
 856 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 857
 858 [system.cpu.toL2Bus.snoop_filter]
 859 type=SnoopFilter
 860 eventq_index=0
 861 lookup_latency=0
 862 max_capacity=8388608
 863 system=system
 864
 865 [system.cpu.tracer]
 866 type=ExeTracer
 867 eventq_index=0
 868
 869 [system.cpu.workload]
 870 type=LiveProcess
 871 cmd=hello
 872 cwd=
 873 drivers=
 874 egid=100
 875 env=
 876 errout=cerr
 877 euid=100
 878 eventq_index=0
 879 executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 880 gid=100
 881 input=cin
 882 kvmInSE=false
 883 max_stack_size=67108864
 884 output=cout
 885 pid=100
 886 ppid=99
 887 simpoint=0
 888 system=system
 889 uid=100
 890 useArchPT=false
 891
 892 [system.cpu_clk_domain]
 893 type=SrcClockDomain
 894 clock=500
 895 domain_id=-1
 896 eventq_index=0
 897 init_perf_level=0
 898 voltage_domain=system.voltage_domain
 899
 900 [system.dvfs_handler]
 901 type=DVFSHandler
 902 domains=
 903 enable=false
 904 eventq_index=0
 905 sys_clk_domain=system.clk_domain
 906 transition_latency=100000000
 907
 908 [system.membus]
 909 type=CoherentXBar
 910 clk_domain=system.clk_domain
 911 eventq_index=0
 912 forward_latency=4
 913 frontend_latency=3
 914 response_latency=2
 915 snoop_filter=Null
 916 snoop_response_latency=4
 917 system=system
 918 use_default_range=false
 919 width=16
 920 master=system.physmem.port
 921 slave=system.system_port system.cpu.l2cache.mem_side
 922
 923 [system.physmem]
 924 type=DRAMCtrl
 925 IDD0=0.075000
 926 IDD02=0.000000
 927 IDD2N=0.050000
 928 IDD2N2=0.000000
 929 IDD2P0=0.000000
 930 IDD2P02=0.000000
 931 IDD2P1=0.000000
 932 IDD2P12=0.000000
 933 IDD3N=0.057000
 934 IDD3N2=0.000000
 935 IDD3P0=0.000000
 936 IDD3P02=0.000000
 937 IDD3P1=0.000000
 938 IDD3P12=0.000000
 939 IDD4R=0.187000
 940 IDD4R2=0.000000
 941 IDD4W=0.165000
 942 IDD4W2=0.000000
 943 IDD5=0.220000
 944 IDD52=0.000000
 945 IDD6=0.000000
 946 IDD62=0.000000
 947 VDD=1.500000
 948 VDD2=0.000000
 949 activation_limit=4
 950 addr_mapping=RoRaBaCoCh
 951 bank_groups_per_rank=0
 952 banks_per_rank=8
 953 burst_length=8
 954 channels=1
 955 clk_domain=system.clk_domain
 956 conf_table_reported=true
 957 device_bus_width=8
 958 device_rowbuffer_size=1024
 959 device_size=536870912
 960 devices_per_rank=8
 961 dll=true
 962 eventq_index=0
 963 in_addr_map=true
 964 max_accesses_per_row=16
 965 mem_sched_policy=frfcfs
 966 min_writes_per_switch=16
 967 null=false
 968 page_policy=open_adaptive
 969 range=0:134217727
 970 ranks_per_channel=2
 971 read_buffer_size=32
 972 static_backend_latency=10000
 973 static_frontend_latency=10000
 974 tBURST=5000
 975 tCCD_L=0
 976 tCK=1250
 977 tCL=13750
 978 tCS=2500
 979 tRAS=35000
 980 tRCD=13750
 981 tREFI=7800000
 982 tRFC=260000
 983 tRP=13750
 984 tRRD=6000
 985 tRRD_L=0
 986 tRTP=7500
 987 tRTW=2500
 988 tWR=15000
 989 tWTR=7500
 990 tXAW=30000
 991 tXP=0
 992 tXPDLL=0
 993 tXS=0
 994 tXSDLL=0
 995 write_buffer_size=64
 996 write_high_thresh_perc=85
 997 write_low_thresh_perc=50
 998 port=system.membus.master[0]
 999
1000 [system.voltage_domain]
1001 type=VoltageDomain
1002 eventq_index=0
1003 voltage=1.000000
1004