tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 clock=1000
  14 init_param=0
  15 kernel=
  16 load_addr_mask=1099511627775
  17 mem_mode=atomic
  18 memories=system.physmem
  19 num_work_ids=16
  20 readfile=
  21 symbolfile=
  22 work_begin_ckpt_count=0
  23 work_begin_cpu_id_exit=-1
  24 work_begin_exit_count=0
  25 work_cpus_ckpt_count=0
  26 work_end_ckpt_count=0
  27 work_end_exit_count=0
  28 work_item_id=-1
  29 system_port=system.membus.slave[0]
  30
  31 [system.cpu]
  32 type=DerivO3CPU
  33 children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
  34 BTBEntries=4096
  35 BTBTagSize=16
  36 LFSTSize=1024
  37 LQEntries=32
  38 LSQCheckLoads=true
  39 LSQDepCheckShift=4
  40 RASSize=16
  41 SQEntries=32
  42 SSITSize=1024
  43 activity=0
  44 backComSize=5
  45 cachePorts=200
  46 checker=system.cpu.checker
  47 choiceCtrBits=2
  48 choicePredictorSize=8192
  49 clock=500
  50 commitToDecodeDelay=1
  51 commitToFetchDelay=1
  52 commitToIEWDelay=1
  53 commitToRenameDelay=1
  54 commitWidth=8
  55 cpu_id=0
  56 decodeToFetchDelay=1
  57 decodeToRenameDelay=1
  58 decodeWidth=8
  59 defer_registration=false
  60 dispatchWidth=8
  61 do_checkpoint_insts=true
  62 do_quiesce=true
  63 do_statistics_insts=true
  64 dtb=system.cpu.dtb
  65 fetchToDecodeDelay=1
  66 fetchTrapLatency=1
  67 fetchWidth=8
  68 forwardComSize=5
  69 fuPool=system.cpu.fuPool
  70 function_trace=false
  71 function_trace_start=0
  72 globalCtrBits=2
  73 globalHistoryBits=13
  74 globalPredictorSize=8192
  75 iewToCommitDelay=1
  76 iewToDecodeDelay=1
  77 iewToFetchDelay=1
  78 iewToRenameDelay=1
  79 instShiftAmt=2
  80 interrupts=system.cpu.interrupts
  81 issueToExecuteDelay=1
  82 issueWidth=8
  83 itb=system.cpu.itb
  84 localCtrBits=2
  85 localHistoryBits=11
  86 localHistoryTableSize=2048
  87 localPredictorSize=2048
  88 max_insts_all_threads=0
  89 max_insts_any_thread=0
  90 max_loads_all_threads=0
  91 max_loads_any_thread=0
  92 needsTSO=false
  93 numIQEntries=64
  94 numPhysFloatRegs=256
  95 numPhysIntRegs=256
  96 numROBEntries=192
  97 numRobs=1
  98 numThreads=1
  99 predType=tournament
 100 profile=0
 101 progress_interval=0
 102 renameToDecodeDelay=1
 103 renameToFetchDelay=1
 104 renameToIEWDelay=2
 105 renameToROBDelay=1
 106 renameWidth=8
 107 smtCommitPolicy=RoundRobin
 108 smtFetchPolicy=SingleThread
 109 smtIQPolicy=Partitioned
 110 smtIQThreshold=100
 111 smtLSQPolicy=Partitioned
 112 smtLSQThreshold=100
 113 smtNumFetchingThreads=1
 114 smtROBPolicy=Partitioned
 115 smtROBThreshold=100
 116 squashWidth=8
 117 store_set_clear_period=250000
 118 system=system
 119 tracer=system.cpu.tracer
 120 trapLatency=13
 121 wbDepth=1
 122 wbWidth=8
 123 workload=system.cpu.workload
 124 dcache_port=system.cpu.dcache.cpu_side
 125 icache_port=system.cpu.icache.cpu_side
 126
 127 [system.cpu.checker]
 128 type=O3Checker
 129 children=dtb itb tracer
 130 checker=Null
 131 clock=500
 132 cpu_id=0
 133 defer_registration=false
 134 do_checkpoint_insts=true
 135 do_quiesce=true
 136 do_statistics_insts=true
 137 dtb=system.cpu.checker.dtb
 138 exitOnError=false
 139 function_trace=false
 140 function_trace_start=0
 141 interrupts=Null
 142 itb=system.cpu.checker.itb
 143 max_insts_all_threads=0
 144 max_insts_any_thread=0
 145 max_loads_all_threads=0
 146 max_loads_any_thread=0
 147 numThreads=1
 148 profile=0
 149 progress_interval=0
 150 system=system
 151 tracer=system.cpu.checker.tracer
 152 updateOnError=true
 153 warnOnlyOnLoadError=true
 154 workload=system.cpu.workload
 155
 156 [system.cpu.checker.dtb]
 157 type=ArmTLB
 158 children=walker
 159 size=64
 160 walker=system.cpu.checker.dtb.walker
 161
 162 [system.cpu.checker.dtb.walker]
 163 type=ArmTableWalker
 164 clock=500
 165 num_squash_per_cycle=2
 166 sys=system
 167 port=system.cpu.toL2Bus.slave[5]
 168
 169 [system.cpu.checker.itb]
 170 type=ArmTLB
 171 children=walker
 172 size=64
 173 walker=system.cpu.checker.itb.walker
 174
 175 [system.cpu.checker.itb.walker]
 176 type=ArmTableWalker
 177 clock=500
 178 num_squash_per_cycle=2
 179 sys=system
 180 port=system.cpu.toL2Bus.slave[4]
 181
 182 [system.cpu.checker.tracer]
 183 type=ExeTracer
 184
 185 [system.cpu.dcache]
 186 type=BaseCache
 187 addr_ranges=0:18446744073709551615
 188 assoc=2
 189 block_size=64
 190 clock=500
 191 forward_snoops=true
 192 hash_delay=1
 193 hit_latency=2
 194 is_top_level=true
 195 max_miss_count=0
 196 mshrs=4
 197 prefetch_on_access=false
 198 prefetcher=Null
 199 prioritizeRequests=false
 200 repl=Null
 201 response_latency=2
 202 size=262144
 203 subblock_size=0
 204 system=system
 205 tgts_per_mshr=20
 206 trace_addr=0
 207 two_queue=false
 208 write_buffers=8
 209 cpu_side=system.cpu.dcache_port
 210 mem_side=system.cpu.toL2Bus.slave[1]
 211
 212 [system.cpu.dtb]
 213 type=ArmTLB
 214 children=walker
 215 size=64
 216 walker=system.cpu.dtb.walker
 217
 218 [system.cpu.dtb.walker]
 219 type=ArmTableWalker
 220 clock=500
 221 num_squash_per_cycle=2
 222 sys=system
 223 port=system.cpu.toL2Bus.slave[3]
 224
 225 [system.cpu.fuPool]
 226 type=FUPool
 227 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 228 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 229
 230 [system.cpu.fuPool.FUList0]
 231 type=FUDesc
 232 children=opList
 233 count=6
 234 opList=system.cpu.fuPool.FUList0.opList
 235
 236 [system.cpu.fuPool.FUList0.opList]
 237 type=OpDesc
 238 issueLat=1
 239 opClass=IntAlu
 240 opLat=1
 241
 242 [system.cpu.fuPool.FUList1]
 243 type=FUDesc
 244 children=opList0 opList1
 245 count=2
 246 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 247
 248 [system.cpu.fuPool.FUList1.opList0]
 249 type=OpDesc
 250 issueLat=1
 251 opClass=IntMult
 252 opLat=3
 253
 254 [system.cpu.fuPool.FUList1.opList1]
 255 type=OpDesc
 256 issueLat=19
 257 opClass=IntDiv
 258 opLat=20
 259
 260 [system.cpu.fuPool.FUList2]
 261 type=FUDesc
 262 children=opList0 opList1 opList2
 263 count=4
 264 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 265
 266 [system.cpu.fuPool.FUList2.opList0]
 267 type=OpDesc
 268 issueLat=1
 269 opClass=FloatAdd
 270 opLat=2
 271
 272 [system.cpu.fuPool.FUList2.opList1]
 273 type=OpDesc
 274 issueLat=1
 275 opClass=FloatCmp
 276 opLat=2
 277
 278 [system.cpu.fuPool.FUList2.opList2]
 279 type=OpDesc
 280 issueLat=1
 281 opClass=FloatCvt
 282 opLat=2
 283
 284 [system.cpu.fuPool.FUList3]
 285 type=FUDesc
 286 children=opList0 opList1 opList2
 287 count=2
 288 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 289
 290 [system.cpu.fuPool.FUList3.opList0]
 291 type=OpDesc
 292 issueLat=1
 293 opClass=FloatMult
 294 opLat=4
 295
 296 [system.cpu.fuPool.FUList3.opList1]
 297 type=OpDesc
 298 issueLat=12
 299 opClass=FloatDiv
 300 opLat=12
 301
 302 [system.cpu.fuPool.FUList3.opList2]
 303 type=OpDesc
 304 issueLat=24
 305 opClass=FloatSqrt
 306 opLat=24
 307
 308 [system.cpu.fuPool.FUList4]
 309 type=FUDesc
 310 children=opList
 311 count=0
 312 opList=system.cpu.fuPool.FUList4.opList
 313
 314 [system.cpu.fuPool.FUList4.opList]
 315 type=OpDesc
 316 issueLat=1
 317 opClass=MemRead
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5]
 321 type=FUDesc
 322 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 323 count=4
 324 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 325
 326 [system.cpu.fuPool.FUList5.opList00]
 327 type=OpDesc
 328 issueLat=1
 329 opClass=SimdAdd
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList01]
 333 type=OpDesc
 334 issueLat=1
 335 opClass=SimdAddAcc
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList02]
 339 type=OpDesc
 340 issueLat=1
 341 opClass=SimdAlu
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList03]
 345 type=OpDesc
 346 issueLat=1
 347 opClass=SimdCmp
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList04]
 351 type=OpDesc
 352 issueLat=1
 353 opClass=SimdCvt
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList05]
 357 type=OpDesc
 358 issueLat=1
 359 opClass=SimdMisc
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList06]
 363 type=OpDesc
 364 issueLat=1
 365 opClass=SimdMult
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList07]
 369 type=OpDesc
 370 issueLat=1
 371 opClass=SimdMultAcc
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList5.opList08]
 375 type=OpDesc
 376 issueLat=1
 377 opClass=SimdShift
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList09]
 381 type=OpDesc
 382 issueLat=1
 383 opClass=SimdShiftAcc
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList5.opList10]
 387 type=OpDesc
 388 issueLat=1
 389 opClass=SimdSqrt
 390 opLat=1
 391
 392 [system.cpu.fuPool.FUList5.opList11]
 393 type=OpDesc
 394 issueLat=1
 395 opClass=SimdFloatAdd
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList5.opList12]
 399 type=OpDesc
 400 issueLat=1
 401 opClass=SimdFloatAlu
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList5.opList13]
 405 type=OpDesc
 406 issueLat=1
 407 opClass=SimdFloatCmp
 408 opLat=1
 409
 410 [system.cpu.fuPool.FUList5.opList14]
 411 type=OpDesc
 412 issueLat=1
 413 opClass=SimdFloatCvt
 414 opLat=1
 415
 416 [system.cpu.fuPool.FUList5.opList15]
 417 type=OpDesc
 418 issueLat=1
 419 opClass=SimdFloatDiv
 420 opLat=1
 421
 422 [system.cpu.fuPool.FUList5.opList16]
 423 type=OpDesc
 424 issueLat=1
 425 opClass=SimdFloatMisc
 426 opLat=1
 427
 428 [system.cpu.fuPool.FUList5.opList17]
 429 type=OpDesc
 430 issueLat=1
 431 opClass=SimdFloatMult
 432 opLat=1
 433
 434 [system.cpu.fuPool.FUList5.opList18]
 435 type=OpDesc
 436 issueLat=1
 437 opClass=SimdFloatMultAcc
 438 opLat=1
 439
 440 [system.cpu.fuPool.FUList5.opList19]
 441 type=OpDesc
 442 issueLat=1
 443 opClass=SimdFloatSqrt
 444 opLat=1
 445
 446 [system.cpu.fuPool.FUList6]
 447 type=FUDesc
 448 children=opList
 449 count=0
 450 opList=system.cpu.fuPool.FUList6.opList
 451
 452 [system.cpu.fuPool.FUList6.opList]
 453 type=OpDesc
 454 issueLat=1
 455 opClass=MemWrite
 456 opLat=1
 457
 458 [system.cpu.fuPool.FUList7]
 459 type=FUDesc
 460 children=opList0 opList1
 461 count=4
 462 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 463
 464 [system.cpu.fuPool.FUList7.opList0]
 465 type=OpDesc
 466 issueLat=1
 467 opClass=MemRead
 468 opLat=1
 469
 470 [system.cpu.fuPool.FUList7.opList1]
 471 type=OpDesc
 472 issueLat=1
 473 opClass=MemWrite
 474 opLat=1
 475
 476 [system.cpu.fuPool.FUList8]
 477 type=FUDesc
 478 children=opList
 479 count=1
 480 opList=system.cpu.fuPool.FUList8.opList
 481
 482 [system.cpu.fuPool.FUList8.opList]
 483 type=OpDesc
 484 issueLat=3
 485 opClass=IprAccess
 486 opLat=3
 487
 488 [system.cpu.icache]
 489 type=BaseCache
 490 addr_ranges=0:18446744073709551615
 491 assoc=2
 492 block_size=64
 493 clock=500
 494 forward_snoops=true
 495 hash_delay=1
 496 hit_latency=2
 497 is_top_level=true
 498 max_miss_count=0
 499 mshrs=4
 500 prefetch_on_access=false
 501 prefetcher=Null
 502 prioritizeRequests=false
 503 repl=Null
 504 response_latency=2
 505 size=131072
 506 subblock_size=0
 507 system=system
 508 tgts_per_mshr=20
 509 trace_addr=0
 510 two_queue=false
 511 write_buffers=8
 512 cpu_side=system.cpu.icache_port
 513 mem_side=system.cpu.toL2Bus.slave[0]
 514
 515 [system.cpu.interrupts]
 516 type=ArmInterrupts
 517
 518 [system.cpu.itb]
 519 type=ArmTLB
 520 children=walker
 521 size=64
 522 walker=system.cpu.itb.walker
 523
 524 [system.cpu.itb.walker]
 525 type=ArmTableWalker
 526 clock=500
 527 num_squash_per_cycle=2
 528 sys=system
 529 port=system.cpu.toL2Bus.slave[2]
 530
 531 [system.cpu.l2cache]
 532 type=BaseCache
 533 addr_ranges=0:18446744073709551615
 534 assoc=8
 535 block_size=64
 536 clock=500
 537 forward_snoops=true
 538 hash_delay=1
 539 hit_latency=20
 540 is_top_level=false
 541 max_miss_count=0
 542 mshrs=20
 543 prefetch_on_access=false
 544 prefetcher=Null
 545 prioritizeRequests=false
 546 repl=Null
 547 response_latency=20
 548 size=2097152
 549 subblock_size=0
 550 system=system
 551 tgts_per_mshr=12
 552 trace_addr=0
 553 two_queue=false
 554 write_buffers=8
 555 cpu_side=system.cpu.toL2Bus.master[0]
 556 mem_side=system.membus.slave[1]
 557
 558 [system.cpu.toL2Bus]
 559 type=CoherentBus
 560 block_size=64
 561 clock=500
 562 header_cycles=1
 563 use_default_range=false
 564 width=32
 565 master=system.cpu.l2cache.cpu_side
 566 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 567
 568 [system.cpu.tracer]
 569 type=ExeTracer
 570
 571 [system.cpu.workload]
 572 type=LiveProcess
 573 cmd=hello
 574 cwd=
 575 egid=100
 576 env=
 577 errout=cerr
 578 euid=100
 579 executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
 580 gid=100
 581 input=cin
 582 max_stack_size=67108864
 583 output=cout
 584 pid=100
 585 ppid=99
 586 simpoint=0
 587 system=system
 588 uid=100
 589
 590 [system.membus]
 591 type=CoherentBus
 592 block_size=64
 593 clock=1000
 594 header_cycles=1
 595 use_default_range=false
 596 width=8
 597 master=system.physmem.port
 598 slave=system.system_port system.cpu.l2cache.mem_side
 599
 600 [system.physmem]
 601 type=SimpleDRAM
 602 addr_mapping=openmap
 603 banks_per_rank=8
 604 clock=1000
 605 conf_table_reported=false
 606 in_addr_map=true
 607 lines_per_rowbuffer=64
 608 mem_sched_policy=fcfs
 609 null=false
 610 page_policy=open
 611 range=0:134217727
 612 ranks_per_channel=2
 613 read_buffer_size=32
 614 tBURST=4000
 615 tCL=14000
 616 tRCD=14000
 617 tREFI=7800000
 618 tRFC=300000
 619 tRP=14000
 620 tWTR=1000
 621 write_buffer_size=32
 622 write_thresh_perc=70
 623 zero=false
 624 port=system.membus.master[0]
 625