tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 clock=1000
  14 init_param=0
  15 kernel=
  16 load_addr_mask=1099511627775
  17 mem_mode=timing
  18 mem_ranges=
  19 memories=system.physmem
  20 num_work_ids=16
  21 readfile=
  22 symbolfile=
  23 work_begin_ckpt_count=0
  24 work_begin_cpu_id_exit=-1
  25 work_begin_exit_count=0
  26 work_cpus_ckpt_count=0
  27 work_end_ckpt_count=0
  28 work_end_exit_count=0
  29 work_item_id=-1
  30 system_port=system.membus.slave[0]
  31
  32 [system.cpu]
  33 type=DerivO3CPU
  34 children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  35 LFSTSize=1024
  36 LQEntries=32
  37 LSQCheckLoads=true
  38 LSQDepCheckShift=4
  39 SQEntries=32
  40 SSITSize=1024
  41 activity=0
  42 backComSize=5
  43 branchPred=system.cpu.branchPred
  44 cachePorts=200
  45 checker=system.cpu.checker
  46 clock=500
  47 commitToDecodeDelay=1
  48 commitToFetchDelay=1
  49 commitToIEWDelay=1
  50 commitToRenameDelay=1
  51 commitWidth=8
  52 cpu_id=0
  53 decodeToFetchDelay=1
  54 decodeToRenameDelay=1
  55 decodeWidth=8
  56 dispatchWidth=8
  57 do_checkpoint_insts=true
  58 do_quiesce=true
  59 do_statistics_insts=true
  60 dtb=system.cpu.dtb
  61 fetchToDecodeDelay=1
  62 fetchTrapLatency=1
  63 fetchWidth=8
  64 forwardComSize=5
  65 fuPool=system.cpu.fuPool
  66 function_trace=false
  67 function_trace_start=0
  68 iewToCommitDelay=1
  69 iewToDecodeDelay=1
  70 iewToFetchDelay=1
  71 iewToRenameDelay=1
  72 interrupts=system.cpu.interrupts
  73 isa=system.cpu.isa
  74 issueToExecuteDelay=1
  75 issueWidth=8
  76 itb=system.cpu.itb
  77 max_insts_all_threads=0
  78 max_insts_any_thread=0
  79 max_loads_all_threads=0
  80 max_loads_any_thread=0
  81 needsTSO=false
  82 numIQEntries=64
  83 numPhysFloatRegs=256
  84 numPhysIntRegs=256
  85 numROBEntries=192
  86 numRobs=1
  87 numThreads=1
  88 profile=0
  89 progress_interval=0
  90 renameToDecodeDelay=1
  91 renameToFetchDelay=1
  92 renameToIEWDelay=2
  93 renameToROBDelay=1
  94 renameWidth=8
  95 smtCommitPolicy=RoundRobin
  96 smtFetchPolicy=SingleThread
  97 smtIQPolicy=Partitioned
  98 smtIQThreshold=100
  99 smtLSQPolicy=Partitioned
 100 smtLSQThreshold=100
 101 smtNumFetchingThreads=1
 102 smtROBPolicy=Partitioned
 103 smtROBThreshold=100
 104 squashWidth=8
 105 store_set_clear_period=250000
 106 switched_out=false
 107 system=system
 108 tracer=system.cpu.tracer
 109 trapLatency=13
 110 wbDepth=1
 111 wbWidth=8
 112 workload=system.cpu.workload
 113 dcache_port=system.cpu.dcache.cpu_side
 114 icache_port=system.cpu.icache.cpu_side
 115
 116 [system.cpu.branchPred]
 117 type=BranchPredictor
 118 BTBEntries=4096
 119 BTBTagSize=16
 120 RASSize=16
 121 choiceCtrBits=2
 122 choicePredictorSize=8192
 123 globalCtrBits=2
 124 globalHistoryBits=13
 125 globalPredictorSize=8192
 126 instShiftAmt=2
 127 localCtrBits=2
 128 localHistoryBits=11
 129 localHistoryTableSize=2048
 130 localPredictorSize=2048
 131 numThreads=1
 132 predType=tournament
 133
 134 [system.cpu.checker]
 135 type=O3Checker
 136 children=dtb isa itb tracer
 137 branchPred=Null
 138 checker=Null
 139 clock=500
 140 cpu_id=0
 141 do_checkpoint_insts=true
 142 do_quiesce=true
 143 do_statistics_insts=true
 144 dtb=system.cpu.checker.dtb
 145 exitOnError=false
 146 function_trace=false
 147 function_trace_start=0
 148 interrupts=Null
 149 isa=system.cpu.checker.isa
 150 itb=system.cpu.checker.itb
 151 max_insts_all_threads=0
 152 max_insts_any_thread=0
 153 max_loads_all_threads=0
 154 max_loads_any_thread=0
 155 numThreads=1
 156 profile=0
 157 progress_interval=0
 158 switched_out=false
 159 system=system
 160 tracer=system.cpu.checker.tracer
 161 updateOnError=true
 162 warnOnlyOnLoadError=true
 163 workload=system.cpu.workload
 164
 165 [system.cpu.checker.dtb]
 166 type=ArmTLB
 167 children=walker
 168 size=64
 169 walker=system.cpu.checker.dtb.walker
 170
 171 [system.cpu.checker.dtb.walker]
 172 type=ArmTableWalker
 173 clock=500
 174 num_squash_per_cycle=2
 175 sys=system
 176 port=system.cpu.toL2Bus.slave[5]
 177
 178 [system.cpu.checker.isa]
 179 type=ArmISA
 180 fpsid=1090793632
 181 id_isar0=34607377
 182 id_isar1=34677009
 183 id_isar2=555950401
 184 id_isar3=17899825
 185 id_isar4=268501314
 186 id_isar5=0
 187 id_mmfr0=3
 188 id_mmfr1=0
 189 id_mmfr2=19070976
 190 id_mmfr3=4027589137
 191 id_pfr0=49
 192 id_pfr1=1
 193 midr=890224640
 194
 195 [system.cpu.checker.itb]
 196 type=ArmTLB
 197 children=walker
 198 size=64
 199 walker=system.cpu.checker.itb.walker
 200
 201 [system.cpu.checker.itb.walker]
 202 type=ArmTableWalker
 203 clock=500
 204 num_squash_per_cycle=2
 205 sys=system
 206 port=system.cpu.toL2Bus.slave[4]
 207
 208 [system.cpu.checker.tracer]
 209 type=ExeTracer
 210
 211 [system.cpu.dcache]
 212 type=BaseCache
 213 addr_ranges=0:18446744073709551615
 214 assoc=2
 215 block_size=64
 216 clock=500
 217 forward_snoops=true
 218 hit_latency=2
 219 is_top_level=true
 220 max_miss_count=0
 221 mshrs=4
 222 prefetch_on_access=false
 223 prefetcher=Null
 224 response_latency=2
 225 size=262144
 226 system=system
 227 tgts_per_mshr=20
 228 two_queue=false
 229 write_buffers=8
 230 cpu_side=system.cpu.dcache_port
 231 mem_side=system.cpu.toL2Bus.slave[1]
 232
 233 [system.cpu.dtb]
 234 type=ArmTLB
 235 children=walker
 236 size=64
 237 walker=system.cpu.dtb.walker
 238
 239 [system.cpu.dtb.walker]
 240 type=ArmTableWalker
 241 clock=500
 242 num_squash_per_cycle=2
 243 sys=system
 244 port=system.cpu.toL2Bus.slave[3]
 245
 246 [system.cpu.fuPool]
 247 type=FUPool
 248 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 249 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 250
 251 [system.cpu.fuPool.FUList0]
 252 type=FUDesc
 253 children=opList
 254 count=6
 255 opList=system.cpu.fuPool.FUList0.opList
 256
 257 [system.cpu.fuPool.FUList0.opList]
 258 type=OpDesc
 259 issueLat=1
 260 opClass=IntAlu
 261 opLat=1
 262
 263 [system.cpu.fuPool.FUList1]
 264 type=FUDesc
 265 children=opList0 opList1
 266 count=2
 267 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 268
 269 [system.cpu.fuPool.FUList1.opList0]
 270 type=OpDesc
 271 issueLat=1
 272 opClass=IntMult
 273 opLat=3
 274
 275 [system.cpu.fuPool.FUList1.opList1]
 276 type=OpDesc
 277 issueLat=19
 278 opClass=IntDiv
 279 opLat=20
 280
 281 [system.cpu.fuPool.FUList2]
 282 type=FUDesc
 283 children=opList0 opList1 opList2
 284 count=4
 285 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 286
 287 [system.cpu.fuPool.FUList2.opList0]
 288 type=OpDesc
 289 issueLat=1
 290 opClass=FloatAdd
 291 opLat=2
 292
 293 [system.cpu.fuPool.FUList2.opList1]
 294 type=OpDesc
 295 issueLat=1
 296 opClass=FloatCmp
 297 opLat=2
 298
 299 [system.cpu.fuPool.FUList2.opList2]
 300 type=OpDesc
 301 issueLat=1
 302 opClass=FloatCvt
 303 opLat=2
 304
 305 [system.cpu.fuPool.FUList3]
 306 type=FUDesc
 307 children=opList0 opList1 opList2
 308 count=2
 309 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 310
 311 [system.cpu.fuPool.FUList3.opList0]
 312 type=OpDesc
 313 issueLat=1
 314 opClass=FloatMult
 315 opLat=4
 316
 317 [system.cpu.fuPool.FUList3.opList1]
 318 type=OpDesc
 319 issueLat=12
 320 opClass=FloatDiv
 321 opLat=12
 322
 323 [system.cpu.fuPool.FUList3.opList2]
 324 type=OpDesc
 325 issueLat=24
 326 opClass=FloatSqrt
 327 opLat=24
 328
 329 [system.cpu.fuPool.FUList4]
 330 type=FUDesc
 331 children=opList
 332 count=0
 333 opList=system.cpu.fuPool.FUList4.opList
 334
 335 [system.cpu.fuPool.FUList4.opList]
 336 type=OpDesc
 337 issueLat=1
 338 opClass=MemRead
 339 opLat=1
 340
 341 [system.cpu.fuPool.FUList5]
 342 type=FUDesc
 343 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 344 count=4
 345 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 346
 347 [system.cpu.fuPool.FUList5.opList00]
 348 type=OpDesc
 349 issueLat=1
 350 opClass=SimdAdd
 351 opLat=1
 352
 353 [system.cpu.fuPool.FUList5.opList01]
 354 type=OpDesc
 355 issueLat=1
 356 opClass=SimdAddAcc
 357 opLat=1
 358
 359 [system.cpu.fuPool.FUList5.opList02]
 360 type=OpDesc
 361 issueLat=1
 362 opClass=SimdAlu
 363 opLat=1
 364
 365 [system.cpu.fuPool.FUList5.opList03]
 366 type=OpDesc
 367 issueLat=1
 368 opClass=SimdCmp
 369 opLat=1
 370
 371 [system.cpu.fuPool.FUList5.opList04]
 372 type=OpDesc
 373 issueLat=1
 374 opClass=SimdCvt
 375 opLat=1
 376
 377 [system.cpu.fuPool.FUList5.opList05]
 378 type=OpDesc
 379 issueLat=1
 380 opClass=SimdMisc
 381 opLat=1
 382
 383 [system.cpu.fuPool.FUList5.opList06]
 384 type=OpDesc
 385 issueLat=1
 386 opClass=SimdMult
 387 opLat=1
 388
 389 [system.cpu.fuPool.FUList5.opList07]
 390 type=OpDesc
 391 issueLat=1
 392 opClass=SimdMultAcc
 393 opLat=1
 394
 395 [system.cpu.fuPool.FUList5.opList08]
 396 type=OpDesc
 397 issueLat=1
 398 opClass=SimdShift
 399 opLat=1
 400
 401 [system.cpu.fuPool.FUList5.opList09]
 402 type=OpDesc
 403 issueLat=1
 404 opClass=SimdShiftAcc
 405 opLat=1
 406
 407 [system.cpu.fuPool.FUList5.opList10]
 408 type=OpDesc
 409 issueLat=1
 410 opClass=SimdSqrt
 411 opLat=1
 412
 413 [system.cpu.fuPool.FUList5.opList11]
 414 type=OpDesc
 415 issueLat=1
 416 opClass=SimdFloatAdd
 417 opLat=1
 418
 419 [system.cpu.fuPool.FUList5.opList12]
 420 type=OpDesc
 421 issueLat=1
 422 opClass=SimdFloatAlu
 423 opLat=1
 424
 425 [system.cpu.fuPool.FUList5.opList13]
 426 type=OpDesc
 427 issueLat=1
 428 opClass=SimdFloatCmp
 429 opLat=1
 430
 431 [system.cpu.fuPool.FUList5.opList14]
 432 type=OpDesc
 433 issueLat=1
 434 opClass=SimdFloatCvt
 435 opLat=1
 436
 437 [system.cpu.fuPool.FUList5.opList15]
 438 type=OpDesc
 439 issueLat=1
 440 opClass=SimdFloatDiv
 441 opLat=1
 442
 443 [system.cpu.fuPool.FUList5.opList16]
 444 type=OpDesc
 445 issueLat=1
 446 opClass=SimdFloatMisc
 447 opLat=1
 448
 449 [system.cpu.fuPool.FUList5.opList17]
 450 type=OpDesc
 451 issueLat=1
 452 opClass=SimdFloatMult
 453 opLat=1
 454
 455 [system.cpu.fuPool.FUList5.opList18]
 456 type=OpDesc
 457 issueLat=1
 458 opClass=SimdFloatMultAcc
 459 opLat=1
 460
 461 [system.cpu.fuPool.FUList5.opList19]
 462 type=OpDesc
 463 issueLat=1
 464 opClass=SimdFloatSqrt
 465 opLat=1
 466
 467 [system.cpu.fuPool.FUList6]
 468 type=FUDesc
 469 children=opList
 470 count=0
 471 opList=system.cpu.fuPool.FUList6.opList
 472
 473 [system.cpu.fuPool.FUList6.opList]
 474 type=OpDesc
 475 issueLat=1
 476 opClass=MemWrite
 477 opLat=1
 478
 479 [system.cpu.fuPool.FUList7]
 480 type=FUDesc
 481 children=opList0 opList1
 482 count=4
 483 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 484
 485 [system.cpu.fuPool.FUList7.opList0]
 486 type=OpDesc
 487 issueLat=1
 488 opClass=MemRead
 489 opLat=1
 490
 491 [system.cpu.fuPool.FUList7.opList1]
 492 type=OpDesc
 493 issueLat=1
 494 opClass=MemWrite
 495 opLat=1
 496
 497 [system.cpu.fuPool.FUList8]
 498 type=FUDesc
 499 children=opList
 500 count=1
 501 opList=system.cpu.fuPool.FUList8.opList
 502
 503 [system.cpu.fuPool.FUList8.opList]
 504 type=OpDesc
 505 issueLat=3
 506 opClass=IprAccess
 507 opLat=3
 508
 509 [system.cpu.icache]
 510 type=BaseCache
 511 addr_ranges=0:18446744073709551615
 512 assoc=2
 513 block_size=64
 514 clock=500
 515 forward_snoops=true
 516 hit_latency=2
 517 is_top_level=true
 518 max_miss_count=0
 519 mshrs=4
 520 prefetch_on_access=false
 521 prefetcher=Null
 522 response_latency=2
 523 size=131072
 524 system=system
 525 tgts_per_mshr=20
 526 two_queue=false
 527 write_buffers=8
 528 cpu_side=system.cpu.icache_port
 529 mem_side=system.cpu.toL2Bus.slave[0]
 530
 531 [system.cpu.interrupts]
 532 type=ArmInterrupts
 533
 534 [system.cpu.isa]
 535 type=ArmISA
 536 fpsid=1090793632
 537 id_isar0=34607377
 538 id_isar1=34677009
 539 id_isar2=555950401
 540 id_isar3=17899825
 541 id_isar4=268501314
 542 id_isar5=0
 543 id_mmfr0=3
 544 id_mmfr1=0
 545 id_mmfr2=19070976
 546 id_mmfr3=4027589137
 547 id_pfr0=49
 548 id_pfr1=1
 549 midr=890224640
 550
 551 [system.cpu.itb]
 552 type=ArmTLB
 553 children=walker
 554 size=64
 555 walker=system.cpu.itb.walker
 556
 557 [system.cpu.itb.walker]
 558 type=ArmTableWalker
 559 clock=500
 560 num_squash_per_cycle=2
 561 sys=system
 562 port=system.cpu.toL2Bus.slave[2]
 563
 564 [system.cpu.l2cache]
 565 type=BaseCache
 566 addr_ranges=0:18446744073709551615
 567 assoc=8
 568 block_size=64
 569 clock=500
 570 forward_snoops=true
 571 hit_latency=20
 572 is_top_level=false
 573 max_miss_count=0
 574 mshrs=20
 575 prefetch_on_access=false
 576 prefetcher=Null
 577 response_latency=20
 578 size=2097152
 579 system=system
 580 tgts_per_mshr=12
 581 two_queue=false
 582 write_buffers=8
 583 cpu_side=system.cpu.toL2Bus.master[0]
 584 mem_side=system.membus.slave[1]
 585
 586 [system.cpu.toL2Bus]
 587 type=CoherentBus
 588 block_size=64
 589 clock=500
 590 header_cycles=1
 591 system=system
 592 use_default_range=false
 593 width=32
 594 master=system.cpu.l2cache.cpu_side
 595 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 596
 597 [system.cpu.tracer]
 598 type=ExeTracer
 599
 600 [system.cpu.workload]
 601 type=LiveProcess
 602 cmd=hello
 603 cwd=
 604 egid=100
 605 env=
 606 errout=cerr
 607 euid=100
 608 executable=tests/test-progs/hello/bin/arm/linux/hello
 609 gid=100
 610 input=cin
 611 max_stack_size=67108864
 612 output=cout
 613 pid=100
 614 ppid=99
 615 simpoint=0
 616 system=system
 617 uid=100
 618
 619 [system.membus]
 620 type=CoherentBus
 621 block_size=64
 622 clock=1000
 623 header_cycles=1
 624 system=system
 625 use_default_range=false
 626 width=8
 627 master=system.physmem.port
 628 slave=system.system_port system.cpu.l2cache.mem_side
 629
 630 [system.physmem]
 631 type=SimpleDRAM
 632 activation_limit=4
 633 addr_mapping=openmap
 634 banks_per_rank=8
 635 channels=1
 636 clock=1000
 637 conf_table_reported=false
 638 in_addr_map=true
 639 lines_per_rowbuffer=32
 640 mem_sched_policy=frfcfs
 641 null=false
 642 page_policy=open
 643 range=0:134217727
 644 ranks_per_channel=2
 645 read_buffer_size=32
 646 tBURST=5000
 647 tCL=13750
 648 tRCD=13750
 649 tREFI=7800000
 650 tRFC=300000
 651 tRP=13750
 652 tWTR=7500
 653 tXAW=40000
 654 write_buffer_size=32
 655 write_thresh_perc=70
 656 zero=false
 657 port=system.membus.master[0]
 658