2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000003 # Number of seconds simulated
4 sim_ticks 2870500 # Number of ticks simulated
5 final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 135849 # Simulator instruction rate (inst/s)
8 host_op_rate 169454 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 84871687 # Simulator tick rate (ticks/s)
10 host_mem_usage 256868 # Number of bytes of host memory used
11 host_seconds 0.03 # Real time elapsed on the host
12 sim_insts 4591 # Number of instructions simulated
13 sim_ops 5729 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 22907 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory
26 system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
38 system.membus.throughput 9251001568 # Throughput (bytes/s)
39 system.membus.data_through_bus 26555 # Total data (bytes)
40 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41 system.cpu_clk_domain.clock 500 # Clock period in ticks
42 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
43 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
44 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
45 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
46 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
47 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
48 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
49 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
50 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
51 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
52 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
53 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
54 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
55 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
56 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
57 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
58 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
59 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
60 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
61 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
62 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
63 system.cpu.dtb.inst_hits 0 # ITB inst hits
64 system.cpu.dtb.inst_misses 0 # ITB inst misses
65 system.cpu.dtb.read_hits 0 # DTB read hits
66 system.cpu.dtb.read_misses 0 # DTB read misses
67 system.cpu.dtb.write_hits 0 # DTB write hits
68 system.cpu.dtb.write_misses 0 # DTB write misses
69 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
70 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
71 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
72 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
73 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
74 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
75 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
76 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
77 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
78 system.cpu.dtb.read_accesses 0 # DTB read accesses
79 system.cpu.dtb.write_accesses 0 # DTB write accesses
80 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
81 system.cpu.dtb.hits 0 # DTB hits
82 system.cpu.dtb.misses 0 # DTB misses
83 system.cpu.dtb.accesses 0 # DTB accesses
84 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
85 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
86 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
87 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
88 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
89 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
90 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
91 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
92 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
93 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
94 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
95 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
96 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
97 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
98 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
99 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
100 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
101 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
102 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
103 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
104 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
105 system.cpu.itb.inst_hits 0 # ITB inst hits
106 system.cpu.itb.inst_misses 0 # ITB inst misses
107 system.cpu.itb.read_hits 0 # DTB read hits
108 system.cpu.itb.read_misses 0 # DTB read misses
109 system.cpu.itb.write_hits 0 # DTB write hits
110 system.cpu.itb.write_misses 0 # DTB write misses
111 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
112 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
113 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
114 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
115 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
116 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
117 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
118 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
119 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
120 system.cpu.itb.read_accesses 0 # DTB read accesses
121 system.cpu.itb.write_accesses 0 # DTB write accesses
122 system.cpu.itb.inst_accesses 0 # ITB inst accesses
123 system.cpu.itb.hits 0 # DTB hits
124 system.cpu.itb.misses 0 # DTB misses
125 system.cpu.itb.accesses 0 # DTB accesses
126 system.cpu.workload.num_syscalls 13 # Number of system calls
127 system.cpu.numCycles 5742 # number of cpu cycles simulated
128 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
129 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
130 system.cpu.committedInsts 4591 # Number of instructions committed
131 system.cpu.committedOps 5729 # Number of ops (including micro ops) committed
132 system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
133 system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
134 system.cpu.num_func_calls 203 # number of times a function call or return occured
135 system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
136 system.cpu.num_int_insts 4976 # number of integer instructions
137 system.cpu.num_fp_insts 16 # number of float instructions
138 system.cpu.num_int_register_reads 25360 # number of times the integer registers were read
139 system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
140 system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
141 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
142 system.cpu.num_mem_refs 2138 # number of memory refs
143 system.cpu.num_load_insts 1200 # Number of load instructions
144 system.cpu.num_store_insts 938 # Number of store instructions
145 system.cpu.num_idle_cycles 0 # Number of idle cycles
146 system.cpu.num_busy_cycles 5742 # Number of busy cycles
147 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
148 system.cpu.idle_fraction 0 # Percentage of idle cycles
150 ---------- End Simulation Statistics ----------
projects / gem5.git / blob