tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 exit_on_work_items=false
  19 init_param=0
  20 kernel=
  21 kernel_addr_check=true
  22 load_addr_mask=1099511627775
  23 load_offset=0
  24 mem_mode=timing
  25 mem_ranges=
  26 memories=system.physmem
  27 mmap_using_noreserve=false
  28 multi_thread=false
  29 num_work_ids=16
  30 readfile=
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[0]
  40
  41 [system.clk_domain]
  42 type=SrcClockDomain
  43 clock=1000
  44 domain_id=-1
  45 eventq_index=0
  46 init_perf_level=0
  47 voltage_domain=system.voltage_domain
  48
  49 [system.cpu]
  50 type=TimingSimpleCPU
  51 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  52 branchPred=Null
  53 checker=Null
  54 clk_domain=system.cpu_clk_domain
  55 cpu_id=0
  56 do_checkpoint_insts=true
  57 do_quiesce=true
  58 do_statistics_insts=true
  59 dstage2_mmu=system.cpu.dstage2_mmu
  60 dtb=system.cpu.dtb
  61 eventq_index=0
  62 function_trace=false
  63 function_trace_start=0
  64 interrupts=system.cpu.interrupts
  65 isa=system.cpu.isa
  66 istage2_mmu=system.cpu.istage2_mmu
  67 itb=system.cpu.itb
  68 max_insts_all_threads=0
  69 max_insts_any_thread=0
  70 max_loads_all_threads=0
  71 max_loads_any_thread=0
  72 numThreads=1
  73 profile=0
  74 progress_interval=0
  75 simpoint_start_insts=
  76 socket_id=0
  77 switched_out=false
  78 system=system
  79 tracer=system.cpu.tracer
  80 workload=system.cpu.workload
  81 dcache_port=system.cpu.dcache.cpu_side
  82 icache_port=system.cpu.icache.cpu_side
  83
  84 [system.cpu.dcache]
  85 type=Cache
  86 children=tags
  87 addr_ranges=0:18446744073709551615
  88 assoc=2
  89 clk_domain=system.cpu_clk_domain
  90 clusivity=mostly_incl
  91 demand_mshr_reserve=1
  92 eventq_index=0
  93 forward_snoops=true
  94 hit_latency=2
  95 is_read_only=false
  96 max_miss_count=0
  97 mshrs=4
  98 prefetch_on_access=false
  99 prefetcher=Null
 100 response_latency=2
 101 sequential_access=false
 102 size=262144
 103 system=system
 104 tags=system.cpu.dcache.tags
 105 tgts_per_mshr=20
 106 write_buffers=8
 107 writeback_clean=false
 108 cpu_side=system.cpu.dcache_port
 109 mem_side=system.cpu.toL2Bus.slave[1]
 110
 111 [system.cpu.dcache.tags]
 112 type=LRU
 113 assoc=2
 114 block_size=64
 115 clk_domain=system.cpu_clk_domain
 116 eventq_index=0
 117 hit_latency=2
 118 sequential_access=false
 119 size=262144
 120
 121 [system.cpu.dstage2_mmu]
 122 type=ArmStage2MMU
 123 children=stage2_tlb
 124 eventq_index=0
 125 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 126 sys=system
 127 tlb=system.cpu.dtb
 128
 129 [system.cpu.dstage2_mmu.stage2_tlb]
 130 type=ArmTLB
 131 children=walker
 132 eventq_index=0
 133 is_stage2=true
 134 size=32
 135 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 136
 137 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 138 type=ArmTableWalker
 139 clk_domain=system.cpu_clk_domain
 140 eventq_index=0
 141 is_stage2=true
 142 num_squash_per_cycle=2
 143 sys=system
 144
 145 [system.cpu.dtb]
 146 type=ArmTLB
 147 children=walker
 148 eventq_index=0
 149 is_stage2=false
 150 size=64
 151 walker=system.cpu.dtb.walker
 152
 153 [system.cpu.dtb.walker]
 154 type=ArmTableWalker
 155 clk_domain=system.cpu_clk_domain
 156 eventq_index=0
 157 is_stage2=false
 158 num_squash_per_cycle=2
 159 sys=system
 160 port=system.cpu.toL2Bus.slave[3]
 161
 162 [system.cpu.icache]
 163 type=Cache
 164 children=tags
 165 addr_ranges=0:18446744073709551615
 166 assoc=2
 167 clk_domain=system.cpu_clk_domain
 168 clusivity=mostly_incl
 169 demand_mshr_reserve=1
 170 eventq_index=0
 171 forward_snoops=true
 172 hit_latency=2
 173 is_read_only=true
 174 max_miss_count=0
 175 mshrs=4
 176 prefetch_on_access=false
 177 prefetcher=Null
 178 response_latency=2
 179 sequential_access=false
 180 size=131072
 181 system=system
 182 tags=system.cpu.icache.tags
 183 tgts_per_mshr=20
 184 write_buffers=8
 185 writeback_clean=true
 186 cpu_side=system.cpu.icache_port
 187 mem_side=system.cpu.toL2Bus.slave[0]
 188
 189 [system.cpu.icache.tags]
 190 type=LRU
 191 assoc=2
 192 block_size=64
 193 clk_domain=system.cpu_clk_domain
 194 eventq_index=0
 195 hit_latency=2
 196 sequential_access=false
 197 size=131072
 198
 199 [system.cpu.interrupts]
 200 type=ArmInterrupts
 201 eventq_index=0
 202
 203 [system.cpu.isa]
 204 type=ArmISA
 205 decoderFlavour=Generic
 206 eventq_index=0
 207 fpsid=1090793632
 208 id_aa64afr0_el1=0
 209 id_aa64afr1_el1=0
 210 id_aa64dfr0_el1=1052678
 211 id_aa64dfr1_el1=0
 212 id_aa64isar0_el1=0
 213 id_aa64isar1_el1=0
 214 id_aa64mmfr0_el1=15728642
 215 id_aa64mmfr1_el1=0
 216 id_aa64pfr0_el1=17
 217 id_aa64pfr1_el1=0
 218 id_isar0=34607377
 219 id_isar1=34677009
 220 id_isar2=555950401
 221 id_isar3=17899825
 222 id_isar4=268501314
 223 id_isar5=0
 224 id_mmfr0=270536963
 225 id_mmfr1=0
 226 id_mmfr2=19070976
 227 id_mmfr3=34611729
 228 id_pfr0=49
 229 id_pfr1=4113
 230 midr=1091551472
 231 pmu=Null
 232 system=system
 233
 234 [system.cpu.istage2_mmu]
 235 type=ArmStage2MMU
 236 children=stage2_tlb
 237 eventq_index=0
 238 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 239 sys=system
 240 tlb=system.cpu.itb
 241
 242 [system.cpu.istage2_mmu.stage2_tlb]
 243 type=ArmTLB
 244 children=walker
 245 eventq_index=0
 246 is_stage2=true
 247 size=32
 248 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 249
 250 [system.cpu.istage2_mmu.stage2_tlb.walker]
 251 type=ArmTableWalker
 252 clk_domain=system.cpu_clk_domain
 253 eventq_index=0
 254 is_stage2=true
 255 num_squash_per_cycle=2
 256 sys=system
 257
 258 [system.cpu.itb]
 259 type=ArmTLB
 260 children=walker
 261 eventq_index=0
 262 is_stage2=false
 263 size=64
 264 walker=system.cpu.itb.walker
 265
 266 [system.cpu.itb.walker]
 267 type=ArmTableWalker
 268 clk_domain=system.cpu_clk_domain
 269 eventq_index=0
 270 is_stage2=false
 271 num_squash_per_cycle=2
 272 sys=system
 273 port=system.cpu.toL2Bus.slave[2]
 274
 275 [system.cpu.l2cache]
 276 type=Cache
 277 children=tags
 278 addr_ranges=0:18446744073709551615
 279 assoc=8
 280 clk_domain=system.cpu_clk_domain
 281 clusivity=mostly_incl
 282 demand_mshr_reserve=1
 283 eventq_index=0
 284 forward_snoops=true
 285 hit_latency=20
 286 is_read_only=false
 287 max_miss_count=0
 288 mshrs=20
 289 prefetch_on_access=false
 290 prefetcher=Null
 291 response_latency=20
 292 sequential_access=false
 293 size=2097152
 294 system=system
 295 tags=system.cpu.l2cache.tags
 296 tgts_per_mshr=12
 297 write_buffers=8
 298 writeback_clean=false
 299 cpu_side=system.cpu.toL2Bus.master[0]
 300 mem_side=system.membus.slave[1]
 301
 302 [system.cpu.l2cache.tags]
 303 type=LRU
 304 assoc=8
 305 block_size=64
 306 clk_domain=system.cpu_clk_domain
 307 eventq_index=0
 308 hit_latency=20
 309 sequential_access=false
 310 size=2097152
 311
 312 [system.cpu.toL2Bus]
 313 type=CoherentXBar
 314 children=snoop_filter
 315 clk_domain=system.cpu_clk_domain
 316 eventq_index=0
 317 forward_latency=0
 318 frontend_latency=1
 319 response_latency=1
 320 snoop_filter=system.cpu.toL2Bus.snoop_filter
 321 snoop_response_latency=1
 322 system=system
 323 use_default_range=false
 324 width=32
 325 master=system.cpu.l2cache.cpu_side
 326 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 327
 328 [system.cpu.toL2Bus.snoop_filter]
 329 type=SnoopFilter
 330 eventq_index=0
 331 lookup_latency=0
 332 max_capacity=8388608
 333 system=system
 334
 335 [system.cpu.tracer]
 336 type=ExeTracer
 337 eventq_index=0
 338
 339 [system.cpu.workload]
 340 type=LiveProcess
 341 cmd=hello
 342 cwd=
 343 drivers=
 344 egid=100
 345 env=
 346 errout=cerr
 347 euid=100
 348 eventq_index=0
 349 executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 350 gid=100
 351 input=cin
 352 kvmInSE=false
 353 max_stack_size=67108864
 354 output=cout
 355 pid=100
 356 ppid=99
 357 simpoint=0
 358 system=system
 359 uid=100
 360 useArchPT=false
 361
 362 [system.cpu_clk_domain]
 363 type=SrcClockDomain
 364 clock=500
 365 domain_id=-1
 366 eventq_index=0
 367 init_perf_level=0
 368 voltage_domain=system.voltage_domain
 369
 370 [system.dvfs_handler]
 371 type=DVFSHandler
 372 domains=
 373 enable=false
 374 eventq_index=0
 375 sys_clk_domain=system.clk_domain
 376 transition_latency=100000000
 377
 378 [system.membus]
 379 type=CoherentXBar
 380 clk_domain=system.clk_domain
 381 eventq_index=0
 382 forward_latency=4
 383 frontend_latency=3
 384 response_latency=2
 385 snoop_filter=Null
 386 snoop_response_latency=4
 387 system=system
 388 use_default_range=false
 389 width=16
 390 master=system.physmem.port
 391 slave=system.system_port system.cpu.l2cache.mem_side
 392
 393 [system.physmem]
 394 type=SimpleMemory
 395 bandwidth=73.000000
 396 clk_domain=system.clk_domain
 397 conf_table_reported=true
 398 eventq_index=0
 399 in_addr_map=true
 400 latency=30000
 401 latency_var=0
 402 null=false
 403 range=0:134217727
 404 port=system.membus.master[0]
 405
 406 [system.voltage_domain]
 407 type=VoltageDomain
 408 eventq_index=0
 409 voltage=1.000000
 410