d881a3977ef596bc79f0556e05ed9b1d4a2d6cbc
5 time_sync_period=100000000000
6 time_sync_spin_threshold=100000000
10 children=cpu membus physmem
12 memories=system.physmem
14 physmem=system.physmem
15 work_begin_ckpt_count=0
16 work_begin_cpu_id_exit=-1
17 work_begin_exit_count=0
18 work_cpus_ckpt_count=0
22 system_port=system.membus.port[0]
26 children=dcache dtb icache itb l2cache toL2Bus tracer workload
30 defer_registration=false
31 do_checkpoint_insts=true
32 do_statistics_insts=true
35 function_trace_start=0
37 max_insts_all_threads=0
38 max_insts_any_thread=0
39 max_loads_all_threads=0
40 max_loads_any_thread=0
45 tracer=system.cpu.tracer
46 workload=system.cpu.workload
47 dcache_port=system.cpu.dcache.cpu_side
48 icache_port=system.cpu.icache.cpu_side
52 addr_range=0:18446744073709551615
62 prefetch_data_accesses_only=false
64 prefetch_latency=10000
65 prefetch_on_access=false
66 prefetch_past_page=false
68 prefetch_serial_squash=false
69 prefetch_use_cpu_id=true
71 prioritizeRequests=false
79 cpu_side=system.cpu.dcache_port
80 mem_side=system.cpu.toL2Bus.port[1]
88 addr_range=0:18446744073709551615
98 prefetch_data_accesses_only=false
100 prefetch_latency=10000
101 prefetch_on_access=false
102 prefetch_past_page=false
104 prefetch_serial_squash=false
105 prefetch_use_cpu_id=true
107 prioritizeRequests=false
115 cpu_side=system.cpu.icache_port
116 mem_side=system.cpu.toL2Bus.port[0]
124 addr_range=0:18446744073709551615
134 prefetch_data_accesses_only=false
136 prefetch_latency=100000
137 prefetch_on_access=false
138 prefetch_past_page=false
140 prefetch_serial_squash=false
141 prefetch_use_cpu_id=true
143 prioritizeRequests=false
151 cpu_side=system.cpu.toL2Bus.port[2]
152 mem_side=system.membus.port[2]
160 use_default_range=false
162 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
167 [system.cpu.workload]
175 executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
178 max_stack_size=67108864
192 use_default_range=false
194 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
204 port=system.membus.port[1]