tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=System
  10 children=cpu membus physmem
  11 mem_mode=atomic
  12 memories=system.physmem
  13 num_work_ids=16
  14 physmem=system.physmem
  15 work_begin_ckpt_count=0
  16 work_begin_cpu_id_exit=-1
  17 work_begin_exit_count=0
  18 work_cpus_ckpt_count=0
  19 work_end_ckpt_count=0
  20 work_end_exit_count=0
  21 work_item_id=-1
  22 system_port=system.membus.port[0]
  23
  24 [system.cpu]
  25 type=TimingSimpleCPU
  26 children=dcache dtb icache itb l2cache toL2Bus tracer workload
  27 checker=Null
  28 clock=500
  29 cpu_id=0
  30 defer_registration=false
  31 do_checkpoint_insts=true
  32 do_statistics_insts=true
  33 dtb=system.cpu.dtb
  34 function_trace=false
  35 function_trace_start=0
  36 itb=system.cpu.itb
  37 max_insts_all_threads=0
  38 max_insts_any_thread=0
  39 max_loads_all_threads=0
  40 max_loads_any_thread=0
  41 numThreads=1
  42 phase=0
  43 progress_interval=0
  44 system=system
  45 tracer=system.cpu.tracer
  46 workload=system.cpu.workload
  47 dcache_port=system.cpu.dcache.cpu_side
  48 icache_port=system.cpu.icache.cpu_side
  49
  50 [system.cpu.dcache]
  51 type=BaseCache
  52 addr_range=0:18446744073709551615
  53 assoc=2
  54 block_size=64
  55 forward_snoops=true
  56 hash_delay=1
  57 is_top_level=true
  58 latency=1000
  59 max_miss_count=0
  60 mshrs=10
  61 num_cpus=1
  62 prefetch_data_accesses_only=false
  63 prefetch_degree=1
  64 prefetch_latency=10000
  65 prefetch_on_access=false
  66 prefetch_past_page=false
  67 prefetch_policy=none
  68 prefetch_serial_squash=false
  69 prefetch_use_cpu_id=true
  70 prefetcher_size=100
  71 prioritizeRequests=false
  72 repl=Null
  73 size=262144
  74 subblock_size=0
  75 tgts_per_mshr=5
  76 trace_addr=0
  77 two_queue=false
  78 write_buffers=8
  79 cpu_side=system.cpu.dcache_port
  80 mem_side=system.cpu.toL2Bus.port[1]
  81
  82 [system.cpu.dtb]
  83 type=ArmTLB
  84 size=64
  85
  86 [system.cpu.icache]
  87 type=BaseCache
  88 addr_range=0:18446744073709551615
  89 assoc=2
  90 block_size=64
  91 forward_snoops=true
  92 hash_delay=1
  93 is_top_level=true
  94 latency=1000
  95 max_miss_count=0
  96 mshrs=10
  97 num_cpus=1
  98 prefetch_data_accesses_only=false
  99 prefetch_degree=1
 100 prefetch_latency=10000
 101 prefetch_on_access=false
 102 prefetch_past_page=false
 103 prefetch_policy=none
 104 prefetch_serial_squash=false
 105 prefetch_use_cpu_id=true
 106 prefetcher_size=100
 107 prioritizeRequests=false
 108 repl=Null
 109 size=131072
 110 subblock_size=0
 111 tgts_per_mshr=5
 112 trace_addr=0
 113 two_queue=false
 114 write_buffers=8
 115 cpu_side=system.cpu.icache_port
 116 mem_side=system.cpu.toL2Bus.port[0]
 117
 118 [system.cpu.itb]
 119 type=ArmTLB
 120 size=64
 121
 122 [system.cpu.l2cache]
 123 type=BaseCache
 124 addr_range=0:18446744073709551615
 125 assoc=2
 126 block_size=64
 127 forward_snoops=true
 128 hash_delay=1
 129 is_top_level=false
 130 latency=10000
 131 max_miss_count=0
 132 mshrs=10
 133 num_cpus=1
 134 prefetch_data_accesses_only=false
 135 prefetch_degree=1
 136 prefetch_latency=100000
 137 prefetch_on_access=false
 138 prefetch_past_page=false
 139 prefetch_policy=none
 140 prefetch_serial_squash=false
 141 prefetch_use_cpu_id=true
 142 prefetcher_size=100
 143 prioritizeRequests=false
 144 repl=Null
 145 size=2097152
 146 subblock_size=0
 147 tgts_per_mshr=5
 148 trace_addr=0
 149 two_queue=false
 150 write_buffers=8
 151 cpu_side=system.cpu.toL2Bus.port[2]
 152 mem_side=system.membus.port[2]
 153
 154 [system.cpu.toL2Bus]
 155 type=Bus
 156 block_size=64
 157 bus_id=0
 158 clock=1000
 159 header_cycles=1
 160 use_default_range=false
 161 width=64
 162 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 163
 164 [system.cpu.tracer]
 165 type=ExeTracer
 166
 167 [system.cpu.workload]
 168 type=LiveProcess
 169 cmd=hello
 170 cwd=
 171 egid=100
 172 env=
 173 errout=cerr
 174 euid=100
 175 executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 176 gid=100
 177 input=cin
 178 max_stack_size=67108864
 179 output=cout
 180 pid=100
 181 ppid=99
 182 simpoint=0
 183 system=system
 184 uid=100
 185
 186 [system.membus]
 187 type=Bus
 188 block_size=64
 189 bus_id=0
 190 clock=1000
 191 header_cycles=1
 192 use_default_range=false
 193 width=64
 194 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 195
 196 [system.physmem]
 197 type=PhysicalMemory
 198 file=
 199 latency=30000
 200 latency_var=0
 201 null=false
 202 range=0:134217727
 203 zero=false
 204 port=system.membus.port[1]
 205