stats: update stats for insts/ops and master id changes
[gem5.git] / tests / quick / se / 00.hello / ref / mips / linux / inorder-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 full_system=false
5 time_sync_enable=false
6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
8
9 [system]
10 type=System
11 children=cpu membus physmem
12 boot_osflags=a
13 init_param=0
14 kernel=
15 load_addr_mask=1099511627775
16 mem_mode=atomic
17 memories=system.physmem
18 num_work_ids=16
19 physmem=system.physmem
20 readfile=
21 symbolfile=
22 work_begin_ckpt_count=0
23 work_begin_cpu_id_exit=-1
24 work_begin_exit_count=0
25 work_cpus_ckpt_count=0
26 work_end_ckpt_count=0
27 work_end_exit_count=0
28 work_item_id=-1
29 system_port=system.membus.port[0]
30
31 [system.cpu]
32 type=InOrderCPU
33 children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
34 BTBEntries=4096
35 BTBTagSize=16
36 RASSize=16
37 activity=0
38 cachePorts=2
39 checker=Null
40 choiceCtrBits=2
41 choicePredictorSize=8192
42 clock=500
43 cpu_id=0
44 dataMemPort=dcache_port
45 defer_registration=false
46 div16Latency=1
47 div16RepeatRate=1
48 div24Latency=1
49 div24RepeatRate=1
50 div32Latency=1
51 div32RepeatRate=1
52 div8Latency=1
53 div8RepeatRate=1
54 do_checkpoint_insts=true
55 do_quiesce=true
56 do_statistics_insts=true
57 dtb=system.cpu.dtb
58 fetchBuffSize=4
59 fetchMemPort=icache_port
60 functionTrace=false
61 functionTraceStart=0
62 function_trace=false
63 function_trace_start=0
64 globalCtrBits=2
65 globalHistoryBits=13
66 globalPredictorSize=8192
67 instShiftAmt=2
68 interrupts=system.cpu.interrupts
69 itb=system.cpu.itb
70 localCtrBits=2
71 localHistoryBits=11
72 localHistoryTableSize=2048
73 localPredictorSize=2048
74 max_insts_all_threads=0
75 max_insts_any_thread=0
76 max_loads_all_threads=0
77 max_loads_any_thread=0
78 memBlockSize=64
79 multLatency=1
80 multRepeatRate=1
81 numThreads=1
82 phase=0
83 predType=tournament
84 profile=0
85 progress_interval=0
86 stageTracing=false
87 stageWidth=4
88 system=system
89 threadModel=SMT
90 tracer=system.cpu.tracer
91 workload=system.cpu.workload
92 dcache_port=system.cpu.dcache.cpu_side
93 icache_port=system.cpu.icache.cpu_side
94
95 [system.cpu.dcache]
96 type=BaseCache
97 addr_range=0:18446744073709551615
98 assoc=2
99 block_size=64
100 forward_snoops=true
101 hash_delay=1
102 is_top_level=true
103 latency=1000
104 max_miss_count=0
105 mshrs=10
106 prefetch_on_access=false
107 prefetcher=Null
108 prioritizeRequests=false
109 repl=Null
110 size=262144
111 subblock_size=0
112 system=system
113 tgts_per_mshr=5
114 trace_addr=0
115 two_queue=false
116 write_buffers=8
117 cpu_side=system.cpu.dcache_port
118 mem_side=system.cpu.toL2Bus.port[1]
119
120 [system.cpu.dtb]
121 type=MipsTLB
122 size=64
123
124 [system.cpu.icache]
125 type=BaseCache
126 addr_range=0:18446744073709551615
127 assoc=2
128 block_size=64
129 forward_snoops=true
130 hash_delay=1
131 is_top_level=true
132 latency=1000
133 max_miss_count=0
134 mshrs=10
135 prefetch_on_access=false
136 prefetcher=Null
137 prioritizeRequests=false
138 repl=Null
139 size=131072
140 subblock_size=0
141 system=system
142 tgts_per_mshr=5
143 trace_addr=0
144 two_queue=false
145 write_buffers=8
146 cpu_side=system.cpu.icache_port
147 mem_side=system.cpu.toL2Bus.port[0]
148
149 [system.cpu.interrupts]
150 type=MipsInterrupts
151
152 [system.cpu.itb]
153 type=MipsTLB
154 size=64
155
156 [system.cpu.l2cache]
157 type=BaseCache
158 addr_range=0:18446744073709551615
159 assoc=2
160 block_size=64
161 forward_snoops=true
162 hash_delay=1
163 is_top_level=false
164 latency=10000
165 max_miss_count=0
166 mshrs=10
167 prefetch_on_access=false
168 prefetcher=Null
169 prioritizeRequests=false
170 repl=Null
171 size=2097152
172 subblock_size=0
173 system=system
174 tgts_per_mshr=5
175 trace_addr=0
176 two_queue=false
177 write_buffers=8
178 cpu_side=system.cpu.toL2Bus.port[2]
179 mem_side=system.membus.port[2]
180
181 [system.cpu.toL2Bus]
182 type=Bus
183 block_size=64
184 bus_id=0
185 clock=1000
186 header_cycles=1
187 use_default_range=false
188 width=64
189 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
190
191 [system.cpu.tracer]
192 type=ExeTracer
193
194 [system.cpu.workload]
195 type=LiveProcess
196 cmd=hello
197 cwd=
198 egid=100
199 env=
200 errout=cerr
201 euid=100
202 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
203 gid=100
204 input=cin
205 max_stack_size=67108864
206 output=cout
207 pid=100
208 ppid=99
209 simpoint=0
210 system=system
211 uid=100
212
213 [system.membus]
214 type=Bus
215 block_size=64
216 bus_id=0
217 clock=1000
218 header_cycles=1
219 use_default_range=false
220 width=64
221 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
222
223 [system.physmem]
224 type=PhysicalMemory
225 file=
226 latency=30000
227 latency_var=0
228 null=false
229 range=0:134217727
230 zero=false
231 port=system.membus.port[1]
232