tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=InOrderCPU
  48 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  49 activity=0
  50 branchPred=system.cpu.branchPred
  51 cachePorts=2
  52 checker=Null
  53 clk_domain=system.cpu_clk_domain
  54 cpu_id=0
  55 div16Latency=1
  56 div16RepeatRate=1
  57 div24Latency=1
  58 div24RepeatRate=1
  59 div32Latency=1
  60 div32RepeatRate=1
  61 div8Latency=1
  62 div8RepeatRate=1
  63 do_checkpoint_insts=true
  64 do_quiesce=true
  65 do_statistics_insts=true
  66 dtb=system.cpu.dtb
  67 eventq_index=0
  68 fetchBuffSize=4
  69 function_trace=false
  70 function_trace_start=0
  71 interrupts=system.cpu.interrupts
  72 isa=system.cpu.isa
  73 itb=system.cpu.itb
  74 max_insts_all_threads=0
  75 max_insts_any_thread=0
  76 max_loads_all_threads=0
  77 max_loads_any_thread=0
  78 memBlockSize=64
  79 multLatency=1
  80 multRepeatRate=1
  81 numThreads=1
  82 profile=0
  83 progress_interval=0
  84 simpoint_start_insts=
  85 socket_id=0
  86 stageTracing=false
  87 stageWidth=4
  88 switched_out=false
  89 system=system
  90 threadModel=SMT
  91 tracer=system.cpu.tracer
  92 workload=system.cpu.workload
  93 dcache_port=system.cpu.dcache.cpu_side
  94 icache_port=system.cpu.icache.cpu_side
  95
  96 [system.cpu.branchPred]
  97 type=BranchPredictor
  98 BTBEntries=4096
  99 BTBTagSize=16
 100 RASSize=16
 101 choiceCtrBits=2
 102 choicePredictorSize=8192
 103 eventq_index=0
 104 globalCtrBits=2
 105 globalPredictorSize=8192
 106 instShiftAmt=2
 107 localCtrBits=2
 108 localHistoryTableSize=2048
 109 localPredictorSize=2048
 110 numThreads=1
 111 predType=tournament
 112
 113 [system.cpu.dcache]
 114 type=BaseCache
 115 children=tags
 116 addr_ranges=0:18446744073709551615
 117 assoc=2
 118 clk_domain=system.cpu_clk_domain
 119 eventq_index=0
 120 forward_snoops=true
 121 hit_latency=2
 122 is_top_level=true
 123 max_miss_count=0
 124 mshrs=4
 125 prefetch_on_access=false
 126 prefetcher=Null
 127 response_latency=2
 128 sequential_access=false
 129 size=262144
 130 system=system
 131 tags=system.cpu.dcache.tags
 132 tgts_per_mshr=20
 133 two_queue=false
 134 write_buffers=8
 135 cpu_side=system.cpu.dcache_port
 136 mem_side=system.cpu.toL2Bus.slave[1]
 137
 138 [system.cpu.dcache.tags]
 139 type=LRU
 140 assoc=2
 141 block_size=64
 142 clk_domain=system.cpu_clk_domain
 143 eventq_index=0
 144 hit_latency=2
 145 sequential_access=false
 146 size=262144
 147
 148 [system.cpu.dtb]
 149 type=MipsTLB
 150 eventq_index=0
 151 size=64
 152
 153 [system.cpu.icache]
 154 type=BaseCache
 155 children=tags
 156 addr_ranges=0:18446744073709551615
 157 assoc=2
 158 clk_domain=system.cpu_clk_domain
 159 eventq_index=0
 160 forward_snoops=true
 161 hit_latency=2
 162 is_top_level=true
 163 max_miss_count=0
 164 mshrs=4
 165 prefetch_on_access=false
 166 prefetcher=Null
 167 response_latency=2
 168 sequential_access=false
 169 size=131072
 170 system=system
 171 tags=system.cpu.icache.tags
 172 tgts_per_mshr=20
 173 two_queue=false
 174 write_buffers=8
 175 cpu_side=system.cpu.icache_port
 176 mem_side=system.cpu.toL2Bus.slave[0]
 177
 178 [system.cpu.icache.tags]
 179 type=LRU
 180 assoc=2
 181 block_size=64
 182 clk_domain=system.cpu_clk_domain
 183 eventq_index=0
 184 hit_latency=2
 185 sequential_access=false
 186 size=131072
 187
 188 [system.cpu.interrupts]
 189 type=MipsInterrupts
 190 eventq_index=0
 191
 192 [system.cpu.isa]
 193 type=MipsISA
 194 eventq_index=0
 195 num_threads=1
 196 num_vpes=1
 197 system=system
 198
 199 [system.cpu.itb]
 200 type=MipsTLB
 201 eventq_index=0
 202 size=64
 203
 204 [system.cpu.l2cache]
 205 type=BaseCache
 206 children=tags
 207 addr_ranges=0:18446744073709551615
 208 assoc=8
 209 clk_domain=system.cpu_clk_domain
 210 eventq_index=0
 211 forward_snoops=true
 212 hit_latency=20
 213 is_top_level=false
 214 max_miss_count=0
 215 mshrs=20
 216 prefetch_on_access=false
 217 prefetcher=Null
 218 response_latency=20
 219 sequential_access=false
 220 size=2097152
 221 system=system
 222 tags=system.cpu.l2cache.tags
 223 tgts_per_mshr=12
 224 two_queue=false
 225 write_buffers=8
 226 cpu_side=system.cpu.toL2Bus.master[0]
 227 mem_side=system.membus.slave[1]
 228
 229 [system.cpu.l2cache.tags]
 230 type=LRU
 231 assoc=8
 232 block_size=64
 233 clk_domain=system.cpu_clk_domain
 234 eventq_index=0
 235 hit_latency=20
 236 sequential_access=false
 237 size=2097152
 238
 239 [system.cpu.toL2Bus]
 240 type=CoherentBus
 241 clk_domain=system.cpu_clk_domain
 242 eventq_index=0
 243 header_cycles=1
 244 system=system
 245 use_default_range=false
 246 width=32
 247 master=system.cpu.l2cache.cpu_side
 248 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 249
 250 [system.cpu.tracer]
 251 type=ExeTracer
 252 eventq_index=0
 253
 254 [system.cpu.workload]
 255 type=LiveProcess
 256 cmd=hello
 257 cwd=
 258 egid=100
 259 env=
 260 errout=cerr
 261 euid=100
 262 eventq_index=0
 263 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
 264 gid=100
 265 input=cin
 266 max_stack_size=67108864
 267 output=cout
 268 pid=100
 269 ppid=99
 270 simpoint=0
 271 system=system
 272 uid=100
 273
 274 [system.cpu_clk_domain]
 275 type=SrcClockDomain
 276 clock=500
 277 domain_id=-1
 278 eventq_index=0
 279 init_perf_level=0
 280 voltage_domain=system.voltage_domain
 281
 282 [system.dvfs_handler]
 283 type=DVFSHandler
 284 domains=
 285 enable=false
 286 eventq_index=0
 287 sys_clk_domain=system.clk_domain
 288 transition_latency=100000000
 289
 290 [system.membus]
 291 type=CoherentBus
 292 clk_domain=system.clk_domain
 293 eventq_index=0
 294 header_cycles=1
 295 system=system
 296 use_default_range=false
 297 width=8
 298 master=system.physmem.port
 299 slave=system.system_port system.cpu.l2cache.mem_side
 300
 301 [system.physmem]
 302 type=DRAMCtrl
 303 activation_limit=4
 304 addr_mapping=RoRaBaChCo
 305 banks_per_rank=8
 306 burst_length=8
 307 channels=1
 308 clk_domain=system.clk_domain
 309 conf_table_reported=true
 310 device_bus_width=8
 311 device_rowbuffer_size=1024
 312 devices_per_rank=8
 313 eventq_index=0
 314 in_addr_map=true
 315 max_accesses_per_row=16
 316 mem_sched_policy=frfcfs
 317 min_writes_per_switch=16
 318 null=false
 319 page_policy=open_adaptive
 320 range=0:134217727
 321 ranks_per_channel=2
 322 read_buffer_size=32
 323 static_backend_latency=10000
 324 static_frontend_latency=10000
 325 tBURST=5000
 326 tCK=1250
 327 tCL=13750
 328 tRAS=35000
 329 tRCD=13750
 330 tREFI=7800000
 331 tRFC=260000
 332 tRP=13750
 333 tRRD=6000
 334 tRTP=7500
 335 tRTW=2500
 336 tWR=15000
 337 tWTR=7500
 338 tXAW=30000
 339 write_buffer_size=64
 340 write_high_thresh_perc=85
 341 write_low_thresh_perc=50
 342 port=system.membus.master[0]
 343
 344 [system.voltage_domain]
 345 type=VoltageDomain
 346 eventq_index=0
 347 voltage=1.000000
 348