2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000025 # Number of seconds simulated
4 sim_ticks 24975000 # Number of ticks simulated
5 final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 84511 # Simulator instruction rate (inst/s)
8 host_op_rate 84494 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 362882134 # Simulator tick rate (ticks/s)
10 host_mem_usage 254488 # Number of bytes of host memory used
11 host_seconds 0.07 # Real time elapsed on the host
12 sim_insts 5814 # Number of instructions simulated
13 sim_ops 5814 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 29120 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 455 # Number of read requests accepted
31 system.physmem.writeReqs 0 # Number of write requests accepted
32 system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue
33 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
34 system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM
35 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
36 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
37 system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side
38 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
39 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
40 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
41 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
42 system.physmem.perBankRdBursts::0 28 # Per bank write bursts
43 system.physmem.perBankRdBursts::1 0 # Per bank write bursts
44 system.physmem.perBankRdBursts::2 0 # Per bank write bursts
45 system.physmem.perBankRdBursts::3 0 # Per bank write bursts
46 system.physmem.perBankRdBursts::4 8 # Per bank write bursts
47 system.physmem.perBankRdBursts::5 3 # Per bank write bursts
48 system.physmem.perBankRdBursts::6 12 # Per bank write bursts
49 system.physmem.perBankRdBursts::7 51 # Per bank write bursts
50 system.physmem.perBankRdBursts::8 59 # Per bank write bursts
51 system.physmem.perBankRdBursts::9 75 # Per bank write bursts
52 system.physmem.perBankRdBursts::10 36 # Per bank write bursts
53 system.physmem.perBankRdBursts::11 19 # Per bank write bursts
54 system.physmem.perBankRdBursts::12 52 # Per bank write bursts
55 system.physmem.perBankRdBursts::13 28 # Per bank write bursts
56 system.physmem.perBankRdBursts::14 77 # Per bank write bursts
57 system.physmem.perBankRdBursts::15 7 # Per bank write bursts
58 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
59 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
60 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
74 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
75 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
76 system.physmem.totGap 24894000 # Total gap between requests
77 system.physmem.readPktSize::0 0 # Read request sizes (log2)
78 system.physmem.readPktSize::1 0 # Read request sizes (log2)
79 system.physmem.readPktSize::2 0 # Read request sizes (log2)
80 system.physmem.readPktSize::3 0 # Read request sizes (log2)
81 system.physmem.readPktSize::4 0 # Read request sizes (log2)
82 system.physmem.readPktSize::5 0 # Read request sizes (log2)
83 system.physmem.readPktSize::6 455 # Read request sizes (log2)
84 system.physmem.writePktSize::0 0 # Write request sizes (log2)
85 system.physmem.writePktSize::1 0 # Write request sizes (log2)
86 system.physmem.writePktSize::2 0 # Write request sizes (log2)
87 system.physmem.writePktSize::3 0 # Write request sizes (log2)
88 system.physmem.writePktSize::4 0 # Write request sizes (log2)
89 system.physmem.writePktSize::5 0 # Write request sizes (log2)
90 system.physmem.writePktSize::6 0 # Write request sizes (log2)
91 system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
123 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
155 system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation
175 system.physmem.totQLat 3167500 # Total ticks spent queuing
176 system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM
177 system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers
178 system.physmem.totBankLat 8112500 # Total ticks spent accessing banks
179 system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst
180 system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst
181 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
182 system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst
183 system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s
184 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
185 system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s
186 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
187 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
188 system.physmem.busUtil 9.11 # Data bus utilization in percentage
189 system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads
190 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
191 system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing
192 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
193 system.physmem.readRowHits 348 # Number of row buffer hits during reads
194 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
195 system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads
196 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
197 system.physmem.avgGap 54712.09 # Average gap between requests
198 system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined
199 system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state
200 system.membus.throughput 1165965966 # Throughput (bytes/s)
201 system.membus.trans_dist::ReadReq 404 # Transaction distribution
202 system.membus.trans_dist::ReadResp 404 # Transaction distribution
203 system.membus.trans_dist::ReadExReq 51 # Transaction distribution
204 system.membus.trans_dist::ReadExResp 51 # Transaction distribution
205 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes)
206 system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes)
207 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes)
208 system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes)
209 system.membus.data_through_bus 29120 # Total data (bytes)
210 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
211 system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks)
212 system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
213 system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks)
214 system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
215 system.cpu.branchPred.lookups 1156 # Number of BP lookups
216 system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted
217 system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect
218 system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups
219 system.cpu.branchPred.BTBHits 339 # Number of BTB hits
220 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
221 system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage
222 system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target.
223 system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
224 system.cpu.dtb.read_hits 0 # DTB read hits
225 system.cpu.dtb.read_misses 0 # DTB read misses
226 system.cpu.dtb.read_accesses 0 # DTB read accesses
227 system.cpu.dtb.write_hits 0 # DTB write hits
228 system.cpu.dtb.write_misses 0 # DTB write misses
229 system.cpu.dtb.write_accesses 0 # DTB write accesses
230 system.cpu.dtb.hits 0 # DTB hits
231 system.cpu.dtb.misses 0 # DTB misses
232 system.cpu.dtb.accesses 0 # DTB accesses
233 system.cpu.itb.read_hits 0 # DTB read hits
234 system.cpu.itb.read_misses 0 # DTB read misses
235 system.cpu.itb.read_accesses 0 # DTB read accesses
236 system.cpu.itb.write_hits 0 # DTB write hits
237 system.cpu.itb.write_misses 0 # DTB write misses
238 system.cpu.itb.write_accesses 0 # DTB write accesses
239 system.cpu.itb.hits 0 # DTB hits
240 system.cpu.itb.misses 0 # DTB misses
241 system.cpu.itb.accesses 0 # DTB accesses
242 system.cpu.workload.num_syscalls 8 # Number of system calls
243 system.cpu.numCycles 49951 # number of cpu cycles simulated
244 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
245 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
246 system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True).
247 system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False).
248 system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File
249 system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
250 system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File
251 system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
252 system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
253 system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
254 system.cpu.regfile_manager.regForwards 1328 # Number of Registers Read Through Forwarding Logic
255 system.cpu.agen_unit.agens 2229 # Number of Address Generations
256 system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken.
257 system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken).
258 system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted
259 system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted
260 system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts
261 system.cpu.execution_unit.executions 3133 # Number of Instructions Executed.
262 system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
263 system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
264 system.cpu.contextSwitches 1 # Number of context switches
265 system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
266 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
267 system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself
268 system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed
269 system.cpu.runCycles 5383 # Number of cycles cpu stages are processed.
270 system.cpu.activity 10.776561 # Percentage of cycles cpu is active
271 system.cpu.comLoads 1163 # Number of Load instructions committed
272 system.cpu.comStores 925 # Number of Store instructions committed
273 system.cpu.comBranches 915 # Number of Branches instructions committed
274 system.cpu.comNops 657 # Number of Nop instructions committed
275 system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
276 system.cpu.comInts 2144 # Number of Integer instructions committed
277 system.cpu.comFloats 0 # Number of Floating Point instructions committed
278 system.cpu.committedInsts 5814 # Number of Instructions committed (Per-Thread)
279 system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
280 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
281 system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
282 system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread)
283 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
284 system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads
285 system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread)
286 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
287 system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads
288 system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed.
289 system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed.
290 system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts).
291 system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed.
292 system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed.
293 system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts).
294 system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed.
295 system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed.
296 system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts).
297 system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed.
298 system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed.
299 system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts).
300 system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed.
301 system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed.
302 system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts).
303 system.cpu.icache.tags.replacements 13 # number of replacements
304 system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use
305 system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
306 system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
307 system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
308 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
309 system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor
310 system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy
311 system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy
312 system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
313 system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
314 system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
315 system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits
316 system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits
317 system.cpu.icache.overall_hits::total 428 # number of overall hits
318 system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
319 system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
320 system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
321 system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
322 system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
323 system.cpu.icache.overall_misses::total 350 # number of overall misses
324 system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles
325 system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles
326 system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles
327 system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles
328 system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles
329 system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles
330 system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
331 system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses)
332 system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
333 system.cpu.icache.demand_accesses::total 778 # number of demand (read+write) accesses
334 system.cpu.icache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses
335 system.cpu.icache.overall_accesses::total 778 # number of overall (read+write) accesses
336 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.449871 # miss rate for ReadReq accesses
337 system.cpu.icache.ReadReq_miss_rate::total 0.449871 # miss rate for ReadReq accesses
338 system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 # miss rate for demand accesses
339 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses
340 system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses
341 system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses
342 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency
343 system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency
344 system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
345 system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency
346 system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
347 system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency
348 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
349 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
350 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
351 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
352 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
353 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
354 system.cpu.icache.fast_writes 0 # number of fast writes performed
355 system.cpu.icache.cache_copies 0 # number of cache copies performed
356 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31 # number of ReadReq MSHR hits
357 system.cpu.icache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits
358 system.cpu.icache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits
359 system.cpu.icache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits
360 system.cpu.icache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits
361 system.cpu.icache.overall_mshr_hits::total 31 # number of overall MSHR hits
362 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses
363 system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses
364 system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses
365 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
366 system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
367 system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
368 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles
369 system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles
370 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles
371 system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles
372 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles
373 system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles
374 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses
375 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses
376 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses
377 system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses
378 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses
379 system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses
380 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency
381 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency
382 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
383 system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
384 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
385 system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
386 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
387 system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s)
388 system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
389 system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
390 system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
391 system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
392 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes)
393 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
394 system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes)
395 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes)
396 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
397 system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes)
398 system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes)
399 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
400 system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
401 system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
402 system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks)
403 system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
404 system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks)
405 system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
406 system.cpu.l2cache.tags.replacements 0 # number of replacements
407 system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use
408 system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
409 system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks.
410 system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks.
411 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
412 system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor
413 system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor
414 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy
415 system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy
416 system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy
417 system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
418 system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
419 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
420 system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
421 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
422 system.cpu.l2cache.overall_hits::total 2 # number of overall hits
423 system.cpu.l2cache.ReadReq_misses::cpu.inst 317 # number of ReadReq misses
424 system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
425 system.cpu.l2cache.ReadReq_misses::total 404 # number of ReadReq misses
426 system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
427 system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
428 system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses
429 system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
430 system.cpu.l2cache.demand_misses::total 455 # number of demand (read+write) misses
431 system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
432 system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
433 system.cpu.l2cache.overall_misses::total 455 # number of overall misses
434 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles
435 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles
436 system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles
437 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles
438 system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles
439 system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles
440 system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles
441 system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles
442 system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles
443 system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles
444 system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles
445 system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
446 system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
447 system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
448 system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
449 system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
450 system.cpu.l2cache.demand_accesses::cpu.inst 319 # number of demand (read+write) accesses
451 system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
452 system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
453 system.cpu.l2cache.overall_accesses::cpu.inst 319 # number of overall (read+write) accesses
454 system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
455 system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
456 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses
457 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
458 system.cpu.l2cache.ReadReq_miss_rate::total 0.995074 # miss rate for ReadReq accesses
459 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
460 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
461 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses
462 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
463 system.cpu.l2cache.demand_miss_rate::total 0.995624 # miss rate for demand accesses
464 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
465 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
466 system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
467 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency
468 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency
469 system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency
470 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency
471 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency
472 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
473 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
474 system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency
475 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
476 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
477 system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency
478 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
479 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
480 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
481 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
482 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
483 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
484 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
485 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
486 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses
487 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
488 system.cpu.l2cache.ReadReq_mshr_misses::total 404 # number of ReadReq MSHR misses
489 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
490 system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
491 system.cpu.l2cache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses
492 system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
493 system.cpu.l2cache.demand_mshr_misses::total 455 # number of demand (read+write) MSHR misses
494 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
495 system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
496 system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
497 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles
498 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles
499 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles
500 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles
501 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles
502 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles
503 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles
504 system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles
505 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles
506 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles
507 system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles
508 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
509 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
510 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
511 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
512 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
513 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses
514 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
515 system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 # mshr miss rate for demand accesses
516 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
517 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
518 system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
519 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency
520 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency
521 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency
522 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency
523 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency
524 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
525 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
526 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
527 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
528 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
529 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
530 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
531 system.cpu.dcache.tags.replacements 0 # number of replacements
532 system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use
533 system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks.
534 system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
535 system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks.
536 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
537 system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor
538 system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy
539 system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy
540 system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits
541 system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits
542 system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
543 system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits
544 system.cpu.dcache.demand_hits::cpu.data 1638 # number of demand (read+write) hits
545 system.cpu.dcache.demand_hits::total 1638 # number of demand (read+write) hits
546 system.cpu.dcache.overall_hits::cpu.data 1638 # number of overall hits
547 system.cpu.dcache.overall_hits::total 1638 # number of overall hits
548 system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
549 system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
550 system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses
551 system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses
552 system.cpu.dcache.demand_misses::cpu.data 450 # number of demand (read+write) misses
553 system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses
554 system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses
555 system.cpu.dcache.overall_misses::total 450 # number of overall misses
556 system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles
557 system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles
558 system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles
559 system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles
560 system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles
561 system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles
562 system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles
563 system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles
564 system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
565 system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
566 system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
567 system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
568 system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
569 system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
570 system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
571 system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
572 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083405 # miss rate for ReadReq accesses
573 system.cpu.dcache.ReadReq_miss_rate::total 0.083405 # miss rate for ReadReq accesses
574 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses
575 system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses
576 system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 # miss rate for demand accesses
577 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses
578 system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses
579 system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses
580 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency
581 system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency
582 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency
583 system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency
584 system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
585 system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency
586 system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
587 system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency
588 system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked
589 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
590 system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
591 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
592 system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked
593 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
594 system.cpu.dcache.fast_writes 0 # number of fast writes performed
595 system.cpu.dcache.cache_copies 0 # number of cache copies performed
596 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
597 system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
598 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits
599 system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits
600 system.cpu.dcache.demand_mshr_hits::cpu.data 312 # number of demand (read+write) MSHR hits
601 system.cpu.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits
602 system.cpu.dcache.overall_mshr_hits::cpu.data 312 # number of overall MSHR hits
603 system.cpu.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits
604 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
605 system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
606 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
607 system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
608 system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
609 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
610 system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
611 system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
612 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles
613 system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles
614 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles
615 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles
616 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles
617 system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles
618 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles
619 system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles
620 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
621 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
622 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
623 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
624 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
625 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
626 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
627 system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
628 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency
629 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency
630 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency
631 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency
632 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
633 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
634 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
635 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
636 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
638 ---------- End Simulation Statistics ----------
projects / gem5.git / blob