2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000020 # Number of seconds simulated
4 sim_ticks 19785000 # Number of ticks simulated
5 final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 71616 # Simulator instruction rate (inst/s)
8 host_tick_rate 243111037 # Simulator tick rate (ticks/s)
9 host_mem_usage 208328 # Number of bytes of host memory used
10 host_seconds 0.08 # Real time elapsed on the host
11 sim_insts 5827 # Number of instructions simulated
12 system.physmem.bytes_read 29120 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 0 # Number of bytes written to this memory
15 system.physmem.num_reads 455 # Number of read requests responded to by this memory
16 system.physmem.num_writes 0 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 1471822087 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 1025423300 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_total 1471822087 # Total bandwidth to/from this memory (bytes/s)
21 system.cpu.dtb.read_hits 0 # DTB read hits
22 system.cpu.dtb.read_misses 0 # DTB read misses
23 system.cpu.dtb.read_accesses 0 # DTB read accesses
24 system.cpu.dtb.write_hits 0 # DTB write hits
25 system.cpu.dtb.write_misses 0 # DTB write misses
26 system.cpu.dtb.write_accesses 0 # DTB write accesses
27 system.cpu.dtb.hits 0 # DTB hits
28 system.cpu.dtb.misses 0 # DTB misses
29 system.cpu.dtb.accesses 0 # DTB accesses
30 system.cpu.itb.read_hits 0 # DTB read hits
31 system.cpu.itb.read_misses 0 # DTB read misses
32 system.cpu.itb.read_accesses 0 # DTB read accesses
33 system.cpu.itb.write_hits 0 # DTB write hits
34 system.cpu.itb.write_misses 0 # DTB write misses
35 system.cpu.itb.write_accesses 0 # DTB write accesses
36 system.cpu.itb.hits 0 # DTB hits
37 system.cpu.itb.misses 0 # DTB misses
38 system.cpu.itb.accesses 0 # DTB accesses
39 system.cpu.workload.num_syscalls 8 # Number of system calls
40 system.cpu.numCycles 39571 # number of cpu cycles simulated
41 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
42 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
43 system.cpu.contextSwitches 1 # Number of context switches
44 system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
45 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
46 system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself
47 system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed
48 system.cpu.runCycles 5405 # Number of cycles cpu stages are processed.
49 system.cpu.activity 13.658993 # Percentage of cycles cpu is active
50 system.cpu.comLoads 1164 # Number of Load instructions committed
51 system.cpu.comStores 925 # Number of Store instructions committed
52 system.cpu.comBranches 916 # Number of Branches instructions committed
53 system.cpu.comNops 657 # Number of Nop instructions committed
54 system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
55 system.cpu.comInts 2155 # Number of Integer instructions committed
56 system.cpu.comFloats 0 # Number of Floating Point instructions committed
57 system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
58 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
59 system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
60 system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread)
61 system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
62 system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads
63 system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread)
64 system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
65 system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads
66 system.cpu.branch_predictor.lookups 1185 # Number of BP lookups
67 system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted
68 system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect
69 system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups
70 system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits
71 system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target.
72 system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions.
73 system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage
74 system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True).
75 system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False).
76 system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File
77 system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File
78 system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File
79 system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
80 system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
81 system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
82 system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic
83 system.cpu.agen_unit.agens 2228 # Number of Address Generations
84 system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken.
85 system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken).
86 system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted
87 system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted
88 system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts
89 system.cpu.execution_unit.executions 3132 # Number of Instructions Executed.
90 system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
91 system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
92 system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed.
93 system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed.
94 system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts).
95 system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed.
96 system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed.
97 system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts).
98 system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed.
99 system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed.
100 system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts).
101 system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed.
102 system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed.
103 system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts).
104 system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed.
105 system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed.
106 system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts).
107 system.cpu.icache.replacements 13 # number of replacements
108 system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use
109 system.cpu.icache.total_refs 443 # Total number of references to valid blocks.
110 system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
111 system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks.
112 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
113 system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context
114 system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy
115 system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits
116 system.cpu.icache.demand_hits 443 # number of demand (read+write) hits
117 system.cpu.icache.overall_hits 443 # number of overall hits
118 system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses
119 system.cpu.icache.demand_misses 341 # number of demand (read+write) misses
120 system.cpu.icache.overall_misses 341 # number of overall misses
121 system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles
122 system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles
123 system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles
124 system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses)
125 system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses
126 system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses
127 system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses
128 system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses
129 system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses
130 system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency
131 system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency
132 system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency
133 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
134 system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
135 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
136 system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
137 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
138 system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
139 system.cpu.icache.fast_writes 0 # number of fast writes performed
140 system.cpu.icache.cache_copies 0 # number of cache copies performed
141 system.cpu.icache.writebacks 0 # number of writebacks
142 system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
143 system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
144 system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits
145 system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
146 system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses
147 system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses
148 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
149 system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles
150 system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles
151 system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles
152 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
153 system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses
154 system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses
155 system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses
156 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency
157 system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency
158 system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency
159 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
160 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
161 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
162 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
163 system.cpu.dcache.replacements 0 # number of replacements
164 system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use
165 system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks.
166 system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
167 system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks.
168 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
169 system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context
170 system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy
171 system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits
172 system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits
173 system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits
174 system.cpu.dcache.overall_hits 1838 # number of overall hits
175 system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses
176 system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses
177 system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses
178 system.cpu.dcache.overall_misses 251 # number of overall misses
179 system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles
180 system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles
181 system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles
182 system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles
183 system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
184 system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
185 system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
186 system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
187 system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses
188 system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses
189 system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses
190 system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses
191 system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency
192 system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency
193 system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency
194 system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency
195 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196 system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked
197 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
198 system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
199 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
200 system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked
201 system.cpu.dcache.fast_writes 0 # number of fast writes performed
202 system.cpu.dcache.cache_copies 0 # number of cache copies performed
203 system.cpu.dcache.writebacks 0 # number of writebacks
204 system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
205 system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits
206 system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits
207 system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits
208 system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
209 system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
210 system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
211 system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
212 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
213 system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles
214 system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles
215 system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles
216 system.cpu.dcache.overall_mshr_miss_latency 7448500 # number of overall MSHR miss cycles
217 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
218 system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
219 system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
220 system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
221 system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
222 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency
223 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255 # average WriteReq mshr miss latency
224 system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency
225 system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency
226 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
227 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
228 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
229 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
230 system.cpu.l2cache.replacements 0 # number of replacements
231 system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use
232 system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
233 system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
234 system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
235 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
236 system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context
237 system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy
238 system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
239 system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
240 system.cpu.l2cache.overall_hits 2 # number of overall hits
241 system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses
242 system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
243 system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses
244 system.cpu.l2cache.overall_misses 455 # number of overall misses
245 system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles
246 system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles
247 system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles
248 system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles
249 system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses)
250 system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
251 system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses
252 system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses
253 system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses
254 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
255 system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses
256 system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses
257 system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency
258 system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency
259 system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency
260 system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency
261 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
262 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
263 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
264 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
265 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
266 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
267 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
268 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
269 system.cpu.l2cache.writebacks 0 # number of writebacks
270 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
271 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
272 system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
273 system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
274 system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses
275 system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses
276 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
277 system.cpu.l2cache.ReadReq_mshr_miss_latency 16247000 # number of ReadReq MSHR miss cycles
278 system.cpu.l2cache.ReadExReq_mshr_miss_latency 2058000 # number of ReadExReq MSHR miss cycles
279 system.cpu.l2cache.demand_mshr_miss_latency 18305000 # number of demand (read+write) MSHR miss cycles
280 system.cpu.l2cache.overall_mshr_miss_latency 18305000 # number of overall MSHR miss cycles
281 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
282 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses
283 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
284 system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses
285 system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses
286 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535 # average ReadReq mshr miss latency
287 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176 # average ReadExReq mshr miss latency
288 system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
289 system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
290 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
291 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
292 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
293 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
295 ---------- End Simulation Statistics ----------
projects / gem5.git / blob