2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000024 # Number of seconds simulated
4 sim_ticks 24405000 # Number of ticks simulated
5 final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 119579 # Simulator instruction rate (inst/s)
8 host_op_rate 119550 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 583509526 # Simulator tick rate (ticks/s)
10 host_mem_usage 251420 # Number of bytes of host memory used
11 host_seconds 0.04 # Real time elapsed on the host
12 sim_insts 4999 # Number of instructions simulated
13 sim_ops 4999 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 862774022 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 367137882 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 1229911903 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 862774022 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 862774022 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 862774022 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 367137882 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 1229911903 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.readReqs 469 # Number of read requests accepted
34 system.physmem.writeReqs 0 # Number of write requests accepted
35 system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
36 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37 system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
38 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40 system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
41 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45 system.physmem.perBankRdBursts::0 29 # Per bank write bursts
46 system.physmem.perBankRdBursts::1 0 # Per bank write bursts
47 system.physmem.perBankRdBursts::2 1 # Per bank write bursts
48 system.physmem.perBankRdBursts::3 0 # Per bank write bursts
49 system.physmem.perBankRdBursts::4 7 # Per bank write bursts
50 system.physmem.perBankRdBursts::5 3 # Per bank write bursts
51 system.physmem.perBankRdBursts::6 13 # Per bank write bursts
52 system.physmem.perBankRdBursts::7 53 # Per bank write bursts
53 system.physmem.perBankRdBursts::8 59 # Per bank write bursts
54 system.physmem.perBankRdBursts::9 76 # Per bank write bursts
55 system.physmem.perBankRdBursts::10 43 # Per bank write bursts
56 system.physmem.perBankRdBursts::11 21 # Per bank write bursts
57 system.physmem.perBankRdBursts::12 51 # Per bank write bursts
58 system.physmem.perBankRdBursts::13 29 # Per bank write bursts
59 system.physmem.perBankRdBursts::14 77 # Per bank write bursts
60 system.physmem.perBankRdBursts::15 7 # Per bank write bursts
61 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79 system.physmem.totGap 24305500 # Total gap between requests
80 system.physmem.readPktSize::0 0 # Read request sizes (log2)
81 system.physmem.readPktSize::1 0 # Read request sizes (log2)
82 system.physmem.readPktSize::2 0 # Read request sizes (log2)
83 system.physmem.readPktSize::3 0 # Read request sizes (log2)
84 system.physmem.readPktSize::4 0 # Read request sizes (log2)
85 system.physmem.readPktSize::5 0 # Read request sizes (log2)
86 system.physmem.readPktSize::6 469 # Read request sizes (log2)
87 system.physmem.writePktSize::0 0 # Write request sizes (log2)
88 system.physmem.writePktSize::1 0 # Write request sizes (log2)
89 system.physmem.writePktSize::2 0 # Write request sizes (log2)
90 system.physmem.writePktSize::3 0 # Write request sizes (log2)
91 system.physmem.writePktSize::4 0 # Write request sizes (log2)
92 system.physmem.writePktSize::5 0 # Write request sizes (log2)
93 system.physmem.writePktSize::6 0 # Write request sizes (log2)
94 system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190 system.physmem.bytesPerActivate::samples 114 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::mean 261.614035 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::gmean 175.762153 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::stdev 255.654479 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::0-127 36 31.58% 31.58% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::128-255 34 29.82% 61.40% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation
204 system.physmem.totQLat 7589250 # Total ticks spent queuing
205 system.physmem.totMemAccLat 16383000 # Total ticks spent from burst creation until serviced by the DRAM
206 system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
207 system.physmem.avgQLat 16181.77 # Average queueing delay per DRAM burst
208 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209 system.physmem.avgMemAccLat 34931.77 # Average memory access latency per DRAM burst
210 system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s
211 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212 system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s
213 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215 system.physmem.busUtil 9.61 # Data bus utilization in percentage
216 system.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads
217 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218 system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing
219 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220 system.physmem.readRowHits 352 # Number of row buffer hits during reads
221 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222 system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads
223 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224 system.physmem.avgGap 51824.09 # Average gap between requests
225 system.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined
226 system.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ)
227 system.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ)
228 system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ)
229 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230 system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
231 system.physmem_0.actBackEnergy 1603980 # Energy for active background per rank (pJ)
232 system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ)
233 system.physmem_0.actPowerDownEnergy 8337960 # Energy for active power-down per rank (pJ)
234 system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ)
235 system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
236 system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ)
237 system.physmem_0.averagePower 566.830977 # Core power per rank (mW)
238 system.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank
239 system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
240 system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
241 system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
242 system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states
243 system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states
244 system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states
245 system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ)
246 system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ)
247 system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ)
248 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249 system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
250 system.physmem_1.actBackEnergy 4208310 # Energy for active background per rank (pJ)
251 system.physmem_1.preBackEnergy 89280 # Energy for precharge background per rank (pJ)
252 system.physmem_1.actPowerDownEnergy 6602310 # Energy for active power-down per rank (pJ)
253 system.physmem_1.prePowerDownEnergy 178560 # Energy for precharge power-down per rank (pJ)
254 system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255 system.physmem_1.totalEnergy 16490760 # Total energy per rank (pJ)
256 system.physmem_1.averagePower 675.712354 # Core power per rank (mW)
257 system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank
258 system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states
259 system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
260 system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
261 system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states
262 system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states
263 system.physmem_1.memoryStateTime::ACT_PDN 14474500 # Time in different power states
264 system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
265 system.cpu.branchPred.lookups 2177 # Number of BP lookups
266 system.cpu.branchPred.condPredicted 1448 # Number of conditional branches predicted
267 system.cpu.branchPred.condIncorrect 422 # Number of conditional branches incorrect
268 system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups
269 system.cpu.branchPred.BTBHits 589 # Number of BTB hits
270 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271 system.cpu.branchPred.BTBHitPct 33.108488 # BTB Hit Percentage
272 system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target.
273 system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
274 system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups.
275 system.cpu.branchPred.indirectHits 2 # Number of indirect target hits.
276 system.cpu.branchPred.indirectMisses 268 # Number of indirect misses.
277 system.cpu.branchPredindirectMispredicted 95 # Number of mispredicted indirect branches.
278 system.cpu_clk_domain.clock 500 # Clock period in ticks
279 system.cpu.dtb.read_hits 0 # DTB read hits
280 system.cpu.dtb.read_misses 0 # DTB read misses
281 system.cpu.dtb.read_accesses 0 # DTB read accesses
282 system.cpu.dtb.write_hits 0 # DTB write hits
283 system.cpu.dtb.write_misses 0 # DTB write misses
284 system.cpu.dtb.write_accesses 0 # DTB write accesses
285 system.cpu.dtb.hits 0 # DTB hits
286 system.cpu.dtb.misses 0 # DTB misses
287 system.cpu.dtb.accesses 0 # DTB accesses
288 system.cpu.itb.read_hits 0 # DTB read hits
289 system.cpu.itb.read_misses 0 # DTB read misses
290 system.cpu.itb.read_accesses 0 # DTB read accesses
291 system.cpu.itb.write_hits 0 # DTB write hits
292 system.cpu.itb.write_misses 0 # DTB write misses
293 system.cpu.itb.write_accesses 0 # DTB write accesses
294 system.cpu.itb.hits 0 # DTB hits
295 system.cpu.itb.misses 0 # DTB misses
296 system.cpu.itb.accesses 0 # DTB accesses
297 system.cpu.workload.numSyscalls 7 # Number of system calls
298 system.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states
299 system.cpu.numCycles 48811 # number of cpu cycles simulated
300 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
301 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
302 system.cpu.fetch.icacheStallCycles 9085 # Number of cycles fetch is stalled on an Icache miss
303 system.cpu.fetch.Insts 12947 # Number of instructions fetch has processed
304 system.cpu.fetch.Branches 2177 # Number of branches that fetch encountered
305 system.cpu.fetch.predictedBranches 842 # Number of branches that fetch has predicted taken
306 system.cpu.fetch.Cycles 5440 # Number of cycles fetch has run and was not squashing or blocked
307 system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing
308 system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
309 system.cpu.fetch.CacheLines 2046 # Number of cache lines fetched
310 system.cpu.fetch.IcacheSquashes 261 # Number of outstanding Icache misses that were squashed
311 system.cpu.fetch.rateDist::samples 15162 # Number of instructions fetched each cycle (Total)
312 system.cpu.fetch.rateDist::mean 0.853911 # Number of instructions fetched each cycle (Total)
313 system.cpu.fetch.rateDist::stdev 2.140587 # Number of instructions fetched each cycle (Total)
314 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
315 system.cpu.fetch.rateDist::0 11809 77.89% 77.89% # Number of instructions fetched each cycle (Total)
316 system.cpu.fetch.rateDist::1 1506 9.93% 87.82% # Number of instructions fetched each cycle (Total)
317 system.cpu.fetch.rateDist::2 111 0.73% 88.55% # Number of instructions fetched each cycle (Total)
318 system.cpu.fetch.rateDist::3 164 1.08% 89.63% # Number of instructions fetched each cycle (Total)
319 system.cpu.fetch.rateDist::4 279 1.84% 91.47% # Number of instructions fetched each cycle (Total)
320 system.cpu.fetch.rateDist::5 101 0.67% 92.14% # Number of instructions fetched each cycle (Total)
321 system.cpu.fetch.rateDist::6 136 0.90% 93.04% # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::7 158 1.04% 94.08% # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::8 898 5.92% 100.00% # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::total 15162 # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.branchRate 0.044601 # Number of branch fetches per cycle
329 system.cpu.fetch.rate 0.265248 # Number of inst fetches per cycle
330 system.cpu.decode.IdleCycles 8416 # Number of cycles decode is idle
331 system.cpu.decode.BlockedCycles 3447 # Number of cycles decode is blocked
332 system.cpu.decode.RunCycles 2766 # Number of cycles decode is running
333 system.cpu.decode.UnblockCycles 141 # Number of cycles decode is unblocking
334 system.cpu.decode.SquashCycles 392 # Number of cycles decode is squashing
335 system.cpu.decode.BranchResolved 589 # Number of times decode resolved a branch
336 system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction
337 system.cpu.decode.DecodedInsts 11962 # Number of instructions handled by decode
338 system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode
339 system.cpu.rename.SquashCycles 392 # Number of cycles rename is squashing
340 system.cpu.rename.IdleCycles 8568 # Number of cycles rename is idle
341 system.cpu.rename.BlockCycles 617 # Number of cycles rename is blocking
342 system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
343 system.cpu.rename.RunCycles 2736 # Number of cycles rename is running
344 system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking
345 system.cpu.rename.RenamedInsts 11523 # Number of instructions processed by rename
346 system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
347 system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
348 system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full
349 system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full
350 system.cpu.rename.RenamedOperands 6897 # Number of destination operands rename has renamed
351 system.cpu.rename.RenameLookups 13509 # Number of register rename lookups that rename has made
352 system.cpu.rename.int_rename_lookups 13276 # Number of integer rename lookups
353 system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
354 system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed
355 system.cpu.rename.UndoneMaps 3605 # Number of HB maps that are undone due to squashing
356 system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
357 system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
358 system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
359 system.cpu.memDep0.insertedLoads 2464 # Number of loads inserted to the mem dependence unit.
360 system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
361 system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
362 system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
363 system.cpu.iq.iqInstsAdded 8995 # Number of instructions added to the IQ (excludes non-spec)
364 system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
365 system.cpu.iq.iqInstsIssued 8108 # Number of instructions issued
366 system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
367 system.cpu.iq.iqSquashedInstsExamined 4006 # Number of squashed instructions iterated over during squash; mainly for profiling
368 system.cpu.iq.iqSquashedOperandsExamined 1995 # Number of squashed operands that are examined and possibly removed from graph
369 system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
370 system.cpu.iq.issued_per_cycle::samples 15162 # Number of insts issued each cycle
371 system.cpu.iq.issued_per_cycle::mean 0.534758 # Number of insts issued each cycle
372 system.cpu.iq.issued_per_cycle::stdev 1.264874 # Number of insts issued each cycle
373 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
374 system.cpu.iq.issued_per_cycle::0 11839 78.08% 78.08% # Number of insts issued each cycle
375 system.cpu.iq.issued_per_cycle::1 1338 8.82% 86.91% # Number of insts issued each cycle
376 system.cpu.iq.issued_per_cycle::2 727 4.79% 91.70% # Number of insts issued each cycle
377 system.cpu.iq.issued_per_cycle::3 451 2.97% 94.68% # Number of insts issued each cycle
378 system.cpu.iq.issued_per_cycle::4 343 2.26% 96.94% # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::5 283 1.87% 98.81% # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::6 110 0.73% 99.53% # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::7 52 0.34% 99.87% # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::total 15162 # Number of insts issued each cycle
387 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
388 system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available
389 system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
390 system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
391 system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
392 system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
393 system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
394 system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
395 system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
396 system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
397 system.cpu.iq.fu_full::FloatMisc 0 0.00% 3.33% # attempts to use FU when none available
398 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
399 system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
400 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
401 system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
402 system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
403 system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
404 system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
419 system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available
420 system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available
421 system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
422 system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
423 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
424 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
425 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
426 system.cpu.iq.FU_type_0::IntAlu 4767 58.79% 58.79% # Type of FU issued
427 system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.84% # Type of FU issued
428 system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.86% # Type of FU issued
429 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.88% # Type of FU issued
430 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued
431 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued
432 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued
433 system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.88% # Type of FU issued
434 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued
435 system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.88% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued
437 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued
438 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued
457 system.cpu.iq.FU_type_0::MemRead 2271 28.01% 86.89% # Type of FU issued
458 system.cpu.iq.FU_type_0::MemWrite 1063 13.11% 100.00% # Type of FU issued
459 system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
460 system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
461 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
462 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
463 system.cpu.iq.FU_type_0::total 8108 # Type of FU issued
464 system.cpu.iq.rate 0.166110 # Inst issue rate
465 system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
466 system.cpu.iq.fu_busy_rate 0.022200 # FU busy rate (busy events/executed inst)
467 system.cpu.iq.int_inst_queue_reads 31574 # Number of integer instruction queue reads
468 system.cpu.iq.int_inst_queue_writes 13019 # Number of integer instruction queue writes
469 system.cpu.iq.int_inst_queue_wakeup_accesses 7329 # Number of integer instruction queue wakeup accesses
470 system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
471 system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
472 system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
473 system.cpu.iq.int_alu_accesses 8286 # Number of integer alu accesses
474 system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
475 system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
476 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
477 system.cpu.iew.lsq.thread0.squashedLoads 1329 # Number of loads squashed
478 system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
479 system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
480 system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
481 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
482 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
483 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
484 system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
485 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
486 system.cpu.iew.iewSquashCycles 392 # Number of cycles IEW is squashing
487 system.cpu.iew.iewBlockCycles 487 # Number of cycles IEW is blocking
488 system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking
489 system.cpu.iew.iewDispatchedInsts 10600 # Number of instructions dispatched to IQ
490 system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch
491 system.cpu.iew.iewDispLoadInsts 2464 # Number of dispatched load instructions
492 system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
493 system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
494 system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
495 system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall
496 system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
497 system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
498 system.cpu.iew.predictedNotTakenIncorrect 335 # Number of branches that were predicted not taken incorrectly
499 system.cpu.iew.branchMispredicts 436 # Number of branch mispredicts detected at execute
500 system.cpu.iew.iewExecutedInsts 7776 # Number of executed instructions
501 system.cpu.iew.iewExecLoadInsts 2123 # Number of load instructions executed
502 system.cpu.iew.iewExecSquashedInsts 332 # Number of squashed instructions skipped in execute
503 system.cpu.iew.exec_swp 0 # number of swp insts executed
504 system.cpu.iew.exec_nop 1594 # number of nop insts executed
505 system.cpu.iew.exec_refs 3172 # number of memory reference insts executed
506 system.cpu.iew.exec_branches 1361 # Number of branches executed
507 system.cpu.iew.exec_stores 1049 # Number of stores executed
508 system.cpu.iew.exec_rate 0.159308 # Inst execution rate
509 system.cpu.iew.wb_sent 7424 # cumulative count of insts sent to commit
510 system.cpu.iew.wb_count 7331 # cumulative count of insts written-back
511 system.cpu.iew.wb_producers 2863 # num instructions producing a value
512 system.cpu.iew.wb_consumers 4269 # num instructions consuming a value
513 system.cpu.iew.wb_rate 0.150192 # insts written-back per cycle
514 system.cpu.iew.wb_fanout 0.670649 # average fanout of values written-back
515 system.cpu.commit.commitSquashedInsts 4961 # The number of squashed insts skipped by commit
516 system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
517 system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted
518 system.cpu.commit.committed_per_cycle::samples 14286 # Number of insts commited each cycle
519 system.cpu.commit.committed_per_cycle::mean 0.394792 # Number of insts commited each cycle
520 system.cpu.commit.committed_per_cycle::stdev 1.199270 # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::0 12095 84.66% 84.66% # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::1 883 6.18% 90.84% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::2 522 3.65% 94.50% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::6 63 0.44% 99.00% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::7 41 0.29% 99.29% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::total 14286 # Number of insts commited each cycle
535 system.cpu.commit.committedInsts 5640 # Number of instructions committed
536 system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed
537 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
538 system.cpu.commit.refs 2036 # Number of memory references committed
539 system.cpu.commit.loads 1135 # Number of loads committed
540 system.cpu.commit.membars 0 # Number of memory barriers committed
541 system.cpu.commit.branches 886 # Number of branches committed
542 system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
543 system.cpu.commit.int_insts 4955 # Number of committed integer instructions.
544 system.cpu.commit.function_calls 85 # Number of function calls committed.
545 system.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction
546 system.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction
547 system.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction
548 system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction
549 system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction
550 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction
551 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction
552 system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction
553 system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.90% # Class of committed instruction
554 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction
555 system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.90% # Class of committed instruction
556 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction
569 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction
570 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction
571 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction
575 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction
577 system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction
578 system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction
579 system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
580 system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
581 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
582 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
583 system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
584 system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
585 system.cpu.rob.rob_reads 24772 # The number of ROB reads
586 system.cpu.rob.rob_writes 22085 # The number of ROB writes
587 system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself
588 system.cpu.idleCycles 33649 # Total number of cycles that the CPU has spent unscheduled due to idling
589 system.cpu.committedInsts 4999 # Number of Instructions Simulated
590 system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
591 system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction
592 system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads
593 system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle
594 system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads
595 system.cpu.int_regfile_reads 10585 # number of integer regfile reads
596 system.cpu.int_regfile_writes 5135 # number of integer regfile writes
597 system.cpu.fp_regfile_reads 3 # number of floating regfile reads
598 system.cpu.fp_regfile_writes 1 # number of floating regfile writes
599 system.cpu.misc_regfile_reads 161 # number of misc regfile reads
600 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
601 system.cpu.dcache.tags.replacements 0 # number of replacements
602 system.cpu.dcache.tags.tagsinuse 91.124976 # Cycle average of tags in use
603 system.cpu.dcache.tags.total_refs 2389 # Total number of references to valid blocks.
604 system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks.
605 system.cpu.dcache.tags.avg_refs 17.064286 # Average number of references to valid blocks.
606 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
607 system.cpu.dcache.tags.occ_blocks::cpu.data 91.124976 # Average occupied blocks per requestor
608 system.cpu.dcache.tags.occ_percent::cpu.data 0.022247 # Average percentage of cache occupancy
609 system.cpu.dcache.tags.occ_percent::total 0.022247 # Average percentage of cache occupancy
610 system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id
611 system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
612 system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
613 system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
614 system.cpu.dcache.tags.tag_accesses 5940 # Number of tag accesses
615 system.cpu.dcache.tags.data_accesses 5940 # Number of data accesses
616 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
617 system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits
618 system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits
619 system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits
620 system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits
621 system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits
622 system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits
623 system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits
624 system.cpu.dcache.overall_hits::total 2389 # number of overall hits
625 system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
626 system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
627 system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses
628 system.cpu.dcache.WriteReq_misses::total 344 # number of WriteReq misses
629 system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses
630 system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses
631 system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses
632 system.cpu.dcache.overall_misses::total 511 # number of overall misses
633 system.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles
634 system.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles
635 system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles
636 system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles
637 system.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles
638 system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles
639 system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles
640 system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles
641 system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses)
642 system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses)
643 system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
644 system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
645 system.cpu.dcache.demand_accesses::cpu.data 2900 # number of demand (read+write) accesses
646 system.cpu.dcache.demand_accesses::total 2900 # number of demand (read+write) accesses
647 system.cpu.dcache.overall_accesses::cpu.data 2900 # number of overall (read+write) accesses
648 system.cpu.dcache.overall_accesses::total 2900 # number of overall (read+write) accesses
649 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083542 # miss rate for ReadReq accesses
650 system.cpu.dcache.ReadReq_miss_rate::total 0.083542 # miss rate for ReadReq accesses
651 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses
652 system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses
653 system.cpu.dcache.demand_miss_rate::cpu.data 0.176207 # miss rate for demand accesses
654 system.cpu.dcache.demand_miss_rate::total 0.176207 # miss rate for demand accesses
655 system.cpu.dcache.overall_miss_rate::cpu.data 0.176207 # miss rate for overall accesses
656 system.cpu.dcache.overall_miss_rate::total 0.176207 # miss rate for overall accesses
657 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency
658 system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency
659 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency
660 system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency
661 system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
662 system.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency
663 system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
664 system.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency
665 system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked
666 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
667 system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
668 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
669 system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked
670 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
671 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits
672 system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
673 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 294 # number of WriteReq MSHR hits
674 system.cpu.dcache.WriteReq_mshr_hits::total 294 # number of WriteReq MSHR hits
675 system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits
676 system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits
677 system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits
678 system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits
679 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
680 system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
681 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
682 system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
683 system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
684 system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses
685 system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
686 system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses
687 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles
688 system.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles
689 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles
690 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles
691 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles
692 system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles
693 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles
694 system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles
695 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses
696 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses
697 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
698 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
699 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for demand accesses
700 system.cpu.dcache.demand_mshr_miss_rate::total 0.048276 # mshr miss rate for demand accesses
701 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for overall accesses
702 system.cpu.dcache.overall_mshr_miss_rate::total 0.048276 # mshr miss rate for overall accesses
703 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency
704 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency
705 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency
706 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency
707 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
708 system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
709 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
710 system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
711 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
712 system.cpu.icache.tags.replacements 17 # number of replacements
713 system.cpu.icache.tags.tagsinuse 160.153151 # Cycle average of tags in use
714 system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks.
715 system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks.
716 system.cpu.icache.tags.avg_refs 4.846386 # Average number of references to valid blocks.
717 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
718 system.cpu.icache.tags.occ_blocks::cpu.inst 160.153151 # Average occupied blocks per requestor
719 system.cpu.icache.tags.occ_percent::cpu.inst 0.078200 # Average percentage of cache occupancy
720 system.cpu.icache.tags.occ_percent::total 0.078200 # Average percentage of cache occupancy
721 system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id
722 system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
723 system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
724 system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id
725 system.cpu.icache.tags.tag_accesses 4424 # Number of tag accesses
726 system.cpu.icache.tags.data_accesses 4424 # Number of data accesses
727 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
728 system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits
729 system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits
730 system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits
731 system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits
732 system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits
733 system.cpu.icache.overall_hits::total 1609 # number of overall hits
734 system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
735 system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
736 system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
737 system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
738 system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
739 system.cpu.icache.overall_misses::total 437 # number of overall misses
740 system.cpu.icache.ReadReq_miss_latency::cpu.inst 35547000 # number of ReadReq miss cycles
741 system.cpu.icache.ReadReq_miss_latency::total 35547000 # number of ReadReq miss cycles
742 system.cpu.icache.demand_miss_latency::cpu.inst 35547000 # number of demand (read+write) miss cycles
743 system.cpu.icache.demand_miss_latency::total 35547000 # number of demand (read+write) miss cycles
744 system.cpu.icache.overall_miss_latency::cpu.inst 35547000 # number of overall miss cycles
745 system.cpu.icache.overall_miss_latency::total 35547000 # number of overall miss cycles
746 system.cpu.icache.ReadReq_accesses::cpu.inst 2046 # number of ReadReq accesses(hits+misses)
747 system.cpu.icache.ReadReq_accesses::total 2046 # number of ReadReq accesses(hits+misses)
748 system.cpu.icache.demand_accesses::cpu.inst 2046 # number of demand (read+write) accesses
749 system.cpu.icache.demand_accesses::total 2046 # number of demand (read+write) accesses
750 system.cpu.icache.overall_accesses::cpu.inst 2046 # number of overall (read+write) accesses
751 system.cpu.icache.overall_accesses::total 2046 # number of overall (read+write) accesses
752 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213587 # miss rate for ReadReq accesses
753 system.cpu.icache.ReadReq_miss_rate::total 0.213587 # miss rate for ReadReq accesses
754 system.cpu.icache.demand_miss_rate::cpu.inst 0.213587 # miss rate for demand accesses
755 system.cpu.icache.demand_miss_rate::total 0.213587 # miss rate for demand accesses
756 system.cpu.icache.overall_miss_rate::cpu.inst 0.213587 # miss rate for overall accesses
757 system.cpu.icache.overall_miss_rate::total 0.213587 # miss rate for overall accesses
758 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81343.249428 # average ReadReq miss latency
759 system.cpu.icache.ReadReq_avg_miss_latency::total 81343.249428 # average ReadReq miss latency
760 system.cpu.icache.demand_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency
761 system.cpu.icache.demand_avg_miss_latency::total 81343.249428 # average overall miss latency
762 system.cpu.icache.overall_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency
763 system.cpu.icache.overall_avg_miss_latency::total 81343.249428 # average overall miss latency
764 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
765 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
766 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
767 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
768 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
769 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
770 system.cpu.icache.writebacks::writebacks 17 # number of writebacks
771 system.cpu.icache.writebacks::total 17 # number of writebacks
772 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits
773 system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits
774 system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits
775 system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits
776 system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits
777 system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits
778 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses
779 system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses
780 system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses
781 system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses
782 system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses
783 system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses
784 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28124000 # number of ReadReq MSHR miss cycles
785 system.cpu.icache.ReadReq_mshr_miss_latency::total 28124000 # number of ReadReq MSHR miss cycles
786 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28124000 # number of demand (read+write) MSHR miss cycles
787 system.cpu.icache.demand_mshr_miss_latency::total 28124000 # number of demand (read+write) MSHR miss cycles
788 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28124000 # number of overall MSHR miss cycles
789 system.cpu.icache.overall_mshr_miss_latency::total 28124000 # number of overall MSHR miss cycles
790 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for ReadReq accesses
791 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162268 # mshr miss rate for ReadReq accesses
792 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for demand accesses
793 system.cpu.icache.demand_mshr_miss_rate::total 0.162268 # mshr miss rate for demand accesses
794 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for overall accesses
795 system.cpu.icache.overall_mshr_miss_rate::total 0.162268 # mshr miss rate for overall accesses
796 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84710.843373 # average ReadReq mshr miss latency
797 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84710.843373 # average ReadReq mshr miss latency
798 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency
799 system.cpu.icache.demand_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency
800 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency
801 system.cpu.icache.overall_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency
802 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
803 system.cpu.l2cache.tags.replacements 0 # number of replacements
804 system.cpu.l2cache.tags.tagsinuse 253.368786 # Cycle average of tags in use
805 system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
806 system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks.
807 system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks.
808 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
809 system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.183576 # Average occupied blocks per requestor
810 system.cpu.l2cache.tags.occ_blocks::cpu.data 91.185210 # Average occupied blocks per requestor
811 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004949 # Average percentage of cache occupancy
812 system.cpu.l2cache.tags.occ_percent::cpu.data 0.002783 # Average percentage of cache occupancy
813 system.cpu.l2cache.tags.occ_percent::total 0.007732 # Average percentage of cache occupancy
814 system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id
815 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
816 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id
817 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id
818 system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
819 system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
820 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
821 system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
822 system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
823 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
824 system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
825 system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
826 system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
827 system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
828 system.cpu.l2cache.overall_hits::total 3 # number of overall hits
829 system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
830 system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
831 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 329 # number of ReadCleanReq misses
832 system.cpu.l2cache.ReadCleanReq_misses::total 329 # number of ReadCleanReq misses
833 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses
834 system.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses
835 system.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses
836 system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses
837 system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
838 system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses
839 system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses
840 system.cpu.l2cache.overall_misses::total 469 # number of overall misses
841 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles
842 system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles
843 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27593000 # number of ReadCleanReq miss cycles
844 system.cpu.l2cache.ReadCleanReq_miss_latency::total 27593000 # number of ReadCleanReq miss cycles
845 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles
846 system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles
847 system.cpu.l2cache.demand_miss_latency::cpu.inst 27593000 # number of demand (read+write) miss cycles
848 system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles
849 system.cpu.l2cache.demand_miss_latency::total 40389500 # number of demand (read+write) miss cycles
850 system.cpu.l2cache.overall_miss_latency::cpu.inst 27593000 # number of overall miss cycles
851 system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles
852 system.cpu.l2cache.overall_miss_latency::total 40389500 # number of overall miss cycles
853 system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
854 system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
855 system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
856 system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
857 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses)
858 system.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses)
859 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses)
860 system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses)
861 system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses
862 system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses
863 system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses
864 system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses
865 system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses
866 system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses
867 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
868 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
869 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990964 # miss rate for ReadCleanReq accesses
870 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990964 # miss rate for ReadCleanReq accesses
871 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
872 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
873 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses
874 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
875 system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses
876 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses
877 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
878 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
879 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency
880 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency
881 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83869.300912 # average ReadCleanReq miss latency
882 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83869.300912 # average ReadCleanReq miss latency
883 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency
884 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency
885 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency
886 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
887 system.cpu.l2cache.demand_avg_miss_latency::total 86118.336887 # average overall miss latency
888 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency
889 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
890 system.cpu.l2cache.overall_avg_miss_latency::total 86118.336887 # average overall miss latency
891 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
892 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
893 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
894 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
895 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
896 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
897 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
898 system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
899 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses
900 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses
901 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses
902 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses
903 system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses
904 system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
905 system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
906 system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses
907 system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
908 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
909 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles
910 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles
911 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24303000 # number of ReadCleanReq MSHR miss cycles
912 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24303000 # number of ReadCleanReq MSHR miss cycles
913 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles
914 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles
915 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24303000 # number of demand (read+write) MSHR miss cycles
916 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles
917 system.cpu.l2cache.demand_mshr_miss_latency::total 35699500 # number of demand (read+write) MSHR miss cycles
918 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24303000 # number of overall MSHR miss cycles
919 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles
920 system.cpu.l2cache.overall_mshr_miss_latency::total 35699500 # number of overall MSHR miss cycles
921 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
922 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
923 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses
924 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses
925 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
926 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
927 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses
928 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
929 system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
930 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses
931 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
932 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
933 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency
934 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency
935 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73869.300912 # average ReadCleanReq mshr miss latency
936 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73869.300912 # average ReadCleanReq mshr miss latency
937 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency
938 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency
939 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency
940 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
941 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency
942 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency
943 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
944 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency
945 system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
946 system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
947 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
948 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
949 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
950 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
951 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
952 system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
953 system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
954 system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
955 system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
956 system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution
957 system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution
958 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes)
959 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes)
960 system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
961 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
962 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes)
963 system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
964 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
965 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
966 system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
967 system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
968 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
969 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
970 system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
971 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
972 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
973 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
974 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
975 system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
976 system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
977 system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
978 system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
979 system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks)
980 system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
981 system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks)
982 system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
983 system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter.
984 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
985 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
986 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
987 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
988 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
989 system.membus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
990 system.membus.trans_dist::ReadResp 419 # Transaction distribution
991 system.membus.trans_dist::ReadExReq 50 # Transaction distribution
992 system.membus.trans_dist::ReadExResp 50 # Transaction distribution
993 system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
994 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
995 system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
996 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
997 system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
998 system.membus.snoops 0 # Total snoops (count)
999 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1000 system.membus.snoop_fanout::samples 469 # Request fanout histogram
1001 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1002 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1003 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1004 system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
1005 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1006 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1007 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1008 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1009 system.membus.snoop_fanout::total 469 # Request fanout histogram
1010 system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks)
1011 system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
1012 system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks)
1013 system.membus.respLayer1.utilization 10.2 # Layer utilization (%)
1015 ---------- End Simulation Statistics ----------
projects / gem5.git / blob