2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000012 # Number of seconds simulated
4 sim_ticks 12478500 # Number of ticks simulated
5 final_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 84509 # Simulator instruction rate (inst/s)
8 host_op_rate 84485 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 203899861 # Simulator tick rate (ticks/s)
10 host_mem_usage 220092 # Number of bytes of host memory used
11 host_seconds 0.06 # Real time elapsed on the host
12 sim_insts 5169 # Number of instructions simulated
13 sim_ops 5169 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 30784 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 481 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s)
30 system.cpu.dtb.read_hits 0 # DTB read hits
31 system.cpu.dtb.read_misses 0 # DTB read misses
32 system.cpu.dtb.read_accesses 0 # DTB read accesses
33 system.cpu.dtb.write_hits 0 # DTB write hits
34 system.cpu.dtb.write_misses 0 # DTB write misses
35 system.cpu.dtb.write_accesses 0 # DTB write accesses
36 system.cpu.dtb.hits 0 # DTB hits
37 system.cpu.dtb.misses 0 # DTB misses
38 system.cpu.dtb.accesses 0 # DTB accesses
39 system.cpu.itb.read_hits 0 # DTB read hits
40 system.cpu.itb.read_misses 0 # DTB read misses
41 system.cpu.itb.read_accesses 0 # DTB read accesses
42 system.cpu.itb.write_hits 0 # DTB write hits
43 system.cpu.itb.write_misses 0 # DTB write misses
44 system.cpu.itb.write_accesses 0 # DTB write accesses
45 system.cpu.itb.hits 0 # DTB hits
46 system.cpu.itb.misses 0 # DTB misses
47 system.cpu.itb.accesses 0 # DTB accesses
48 system.cpu.workload.num_syscalls 8 # Number of system calls
49 system.cpu.numCycles 24958 # number of cpu cycles simulated
50 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
51 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
52 system.cpu.BPredUnit.lookups 2172 # Number of BP lookups
53 system.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted
54 system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect
55 system.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups
56 system.cpu.BPredUnit.BTBHits 457 # Number of BTB hits
57 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
58 system.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target.
59 system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
60 system.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss
61 system.cpu.fetch.Insts 13207 # Number of instructions fetch has processed
62 system.cpu.fetch.Branches 2172 # Number of branches that fetch encountered
63 system.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken
64 system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked
65 system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing
66 system.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked
67 system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
68 system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
69 system.cpu.fetch.CacheLines 1938 # Number of cache lines fetched
70 system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed
71 system.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total)
72 system.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total)
73 system.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total)
74 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
75 system.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total)
76 system.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total)
77 system.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total)
78 system.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total)
79 system.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total)
80 system.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total)
81 system.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total)
82 system.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total)
83 system.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total)
84 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
85 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle
89 system.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle
90 system.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle
91 system.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked
92 system.cpu.decode.RunCycles 3014 # Number of cycles decode is running
93 system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking
94 system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing
95 system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch
96 system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction
97 system.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode
98 system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode
99 system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing
100 system.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle
101 system.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking
102 system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst
103 system.cpu.rename.RunCycles 2873 # Number of cycles rename is running
104 system.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking
105 system.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename
106 system.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full
107 system.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed
108 system.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made
109 system.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups
110 system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
111 system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed
112 system.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing
113 system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
114 system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
115 system.cpu.rename.skidInsts 266 # count of insts added to the skid buffer
116 system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit.
117 system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit.
118 system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
119 system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
120 system.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec)
121 system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
122 system.cpu.iq.iqInstsIssued 8121 # Number of instructions issued
123 system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued
124 system.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling
125 system.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph
126 system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
127 system.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle
128 system.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle
129 system.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle
130 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
131 system.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle
132 system.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle
133 system.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle
134 system.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle
135 system.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle
136 system.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle
137 system.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle
138 system.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle
139 system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle
140 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
141 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
142 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle
144 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
145 system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available
146 system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
147 system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
148 system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
149 system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
150 system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
151 system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
152 system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
153 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
154 system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
155 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
156 system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
157 system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
158 system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
159 system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
160 system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
161 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
162 system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
163 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
164 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
165 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
166 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
167 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
168 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
174 system.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available
175 system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available
176 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
177 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
178 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
179 system.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued
180 system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued
181 system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued
182 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued
183 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued
184 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued
185 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued
186 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued
187 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued
188 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued
189 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued
190 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued
191 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued
192 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued
193 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued
194 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued
195 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued
196 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued
197 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued
198 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued
199 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued
200 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued
201 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued
202 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued
208 system.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued
209 system.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued
210 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
211 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
212 system.cpu.iq.FU_type_0::total 8121 # Type of FU issued
213 system.cpu.iq.rate 0.325387 # Inst issue rate
214 system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
215 system.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst)
216 system.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads
217 system.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes
218 system.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses
219 system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
220 system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
221 system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
222 system.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses
223 system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
224 system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
225 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
226 system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed
227 system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
228 system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
229 system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed
230 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
231 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
232 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
233 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
234 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
235 system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing
236 system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking
237 system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
238 system.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ
239 system.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch
240 system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions
241 system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions
242 system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
243 system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
244 system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
245 system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
246 system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
247 system.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly
248 system.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute
249 system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions
250 system.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed
251 system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute
252 system.cpu.iew.exec_swp 0 # number of swp insts executed
253 system.cpu.iew.exec_nop 1469 # number of nop insts executed
254 system.cpu.iew.exec_refs 3191 # number of memory reference insts executed
255 system.cpu.iew.exec_branches 1304 # Number of branches executed
256 system.cpu.iew.exec_stores 1065 # Number of stores executed
257 system.cpu.iew.exec_rate 0.311163 # Inst execution rate
258 system.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit
259 system.cpu.iew.wb_count 7294 # cumulative count of insts written-back
260 system.cpu.iew.wb_producers 2836 # num instructions producing a value
261 system.cpu.iew.wb_consumers 4075 # num instructions consuming a value
262 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
263 system.cpu.iew.wb_rate 0.292251 # insts written-back per cycle
264 system.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back
265 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
266 system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
267 system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions
268 system.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit
269 system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
270 system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted
271 system.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle
272 system.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle
273 system.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle
274 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
275 system.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle
276 system.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle
277 system.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle
278 system.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle
279 system.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle
280 system.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle
281 system.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle
282 system.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle
283 system.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle
284 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
285 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
286 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
287 system.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle
288 system.cpu.commit.committedInsts 5826 # Number of instructions committed
289 system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed
290 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
291 system.cpu.commit.refs 2089 # Number of memory references committed
292 system.cpu.commit.loads 1164 # Number of loads committed
293 system.cpu.commit.membars 0 # Number of memory barriers committed
294 system.cpu.commit.branches 916 # Number of branches committed
295 system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
296 system.cpu.commit.int_insts 5124 # Number of committed integer instructions.
297 system.cpu.commit.function_calls 87 # Number of function calls committed.
298 system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached
299 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
300 system.cpu.rob.rob_reads 22599 # The number of ROB reads
301 system.cpu.rob.rob_writes 21853 # The number of ROB writes
302 system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself
303 system.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling
304 system.cpu.committedInsts 5169 # Number of Instructions Simulated
305 system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated
306 system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
307 system.cpu.cpi 4.828400 # CPI: Cycles Per Instruction
308 system.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads
309 system.cpu.ipc 0.207108 # IPC: Instructions Per Cycle
310 system.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads
311 system.cpu.int_regfile_reads 10560 # number of integer regfile reads
312 system.cpu.int_regfile_writes 5130 # number of integer regfile writes
313 system.cpu.fp_regfile_reads 3 # number of floating regfile reads
314 system.cpu.fp_regfile_writes 1 # number of floating regfile writes
315 system.cpu.misc_regfile_reads 150 # number of misc regfile reads
316 system.cpu.icache.replacements 17 # number of replacements
317 system.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use
318 system.cpu.icache.total_refs 1503 # Total number of references to valid blocks.
319 system.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks.
320 system.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks.
321 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
322 system.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor
323 system.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy
324 system.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy
325 system.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits
326 system.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits
327 system.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits
328 system.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits
329 system.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits
330 system.cpu.icache.overall_hits::total 1503 # number of overall hits
331 system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses
332 system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses
333 system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses
334 system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses
335 system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses
336 system.cpu.icache.overall_misses::total 435 # number of overall misses
337 system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles
338 system.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles
339 system.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles
340 system.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles
341 system.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles
342 system.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles
343 system.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses)
344 system.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses)
345 system.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses
346 system.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses
347 system.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses
348 system.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses
349 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses
350 system.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses
351 system.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses
352 system.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses
353 system.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses
354 system.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses
355 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency
356 system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency
357 system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency
358 system.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency
359 system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency
360 system.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency
361 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
362 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
363 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
364 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
365 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
366 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
367 system.cpu.icache.fast_writes 0 # number of fast writes performed
368 system.cpu.icache.cache_copies 0 # number of cache copies performed
369 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
370 system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
371 system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
372 system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
373 system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
374 system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
375 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses
376 system.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses
377 system.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses
378 system.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses
379 system.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses
380 system.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses
381 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles
382 system.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles
383 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles
384 system.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles
385 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles
386 system.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles
387 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses
388 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses
389 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses
390 system.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses
391 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses
392 system.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses
393 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency
394 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency
395 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency
396 system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency
397 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency
398 system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency
399 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
400 system.cpu.dcache.replacements 0 # number of replacements
401 system.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use
402 system.cpu.dcache.total_refs 2489 # Total number of references to valid blocks.
403 system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks.
404 system.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks.
405 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
406 system.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor
407 system.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy
408 system.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy
409 system.cpu.dcache.ReadReq_hits::cpu.data 1903 # number of ReadReq hits
410 system.cpu.dcache.ReadReq_hits::total 1903 # number of ReadReq hits
411 system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits
412 system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits
413 system.cpu.dcache.demand_hits::cpu.data 2489 # number of demand (read+write) hits
414 system.cpu.dcache.demand_hits::total 2489 # number of demand (read+write) hits
415 system.cpu.dcache.overall_hits::cpu.data 2489 # number of overall hits
416 system.cpu.dcache.overall_hits::total 2489 # number of overall hits
417 system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
418 system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
419 system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses
420 system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses
421 system.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses
422 system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses
423 system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses
424 system.cpu.dcache.overall_misses::total 472 # number of overall misses
425 system.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles
426 system.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles
427 system.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles
428 system.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles
429 system.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles
430 system.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles
431 system.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles
432 system.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles
433 system.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses)
434 system.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses)
435 system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
436 system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
437 system.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses
438 system.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses
439 system.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses
440 system.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses
441 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses
442 system.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses
443 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses
444 system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses
445 system.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses
446 system.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses
447 system.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses
448 system.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses
449 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency
450 system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency
451 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency
452 system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency
453 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency
454 system.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency
455 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency
456 system.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency
457 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
458 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
459 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
460 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
461 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
462 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
463 system.cpu.dcache.fast_writes 0 # number of fast writes performed
464 system.cpu.dcache.cache_copies 0 # number of cache copies performed
465 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits
466 system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits
467 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits
468 system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits
469 system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits
470 system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits
471 system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits
472 system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits
473 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses
474 system.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses
475 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
476 system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
477 system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
478 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses
479 system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
480 system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses
481 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3306000 # number of ReadReq MSHR miss cycles
482 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3306000 # number of ReadReq MSHR miss cycles
483 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845000 # number of WriteReq MSHR miss cycles
484 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles
485 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151000 # number of demand (read+write) MSHR miss cycles
486 system.cpu.dcache.demand_mshr_miss_latency::total 5151000 # number of demand (read+write) MSHR miss cycles
487 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151000 # number of overall MSHR miss cycles
488 system.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles
489 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses
490 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses
491 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
492 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
493 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for demand accesses
494 system.cpu.dcache.demand_mshr_miss_rate::total 0.048294 # mshr miss rate for demand accesses
495 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for overall accesses
496 system.cpu.dcache.overall_mshr_miss_rate::total 0.048294 # mshr miss rate for overall accesses
497 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35934.782609 # average ReadReq mshr miss latency
498 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35934.782609 # average ReadReq mshr miss latency
499 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36176.470588 # average WriteReq mshr miss latency
500 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36176.470588 # average WriteReq mshr miss latency
501 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency
502 system.cpu.dcache.demand_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency
503 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency
504 system.cpu.dcache.overall_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency
505 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
506 system.cpu.l2cache.replacements 0 # number of replacements
507 system.cpu.l2cache.tagsinuse 224.190745 # Cycle average of tags in use
508 system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
509 system.cpu.l2cache.sampled_refs 430 # Sample count of references to valid blocks.
510 system.cpu.l2cache.avg_refs 0.006977 # Average number of references to valid blocks.
511 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
512 system.cpu.l2cache.occ_blocks::cpu.inst 165.976213 # Average occupied blocks per requestor
513 system.cpu.l2cache.occ_blocks::cpu.data 58.214532 # Average occupied blocks per requestor
514 system.cpu.l2cache.occ_percent::cpu.inst 0.005065 # Average percentage of cache occupancy
515 system.cpu.l2cache.occ_percent::cpu.data 0.001777 # Average percentage of cache occupancy
516 system.cpu.l2cache.occ_percent::total 0.006842 # Average percentage of cache occupancy
517 system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
518 system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
519 system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
520 system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
521 system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
522 system.cpu.l2cache.overall_hits::total 3 # number of overall hits
523 system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses
524 system.cpu.l2cache.ReadReq_misses::cpu.data 92 # number of ReadReq misses
525 system.cpu.l2cache.ReadReq_misses::total 430 # number of ReadReq misses
526 system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
527 system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
528 system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses
529 system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses
530 system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses
531 system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses
532 system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses
533 system.cpu.l2cache.overall_misses::total 481 # number of overall misses
534 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11593500 # number of ReadReq miss cycles
535 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3178500 # number of ReadReq miss cycles
536 system.cpu.l2cache.ReadReq_miss_latency::total 14772000 # number of ReadReq miss cycles
537 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1768500 # number of ReadExReq miss cycles
538 system.cpu.l2cache.ReadExReq_miss_latency::total 1768500 # number of ReadExReq miss cycles
539 system.cpu.l2cache.demand_miss_latency::cpu.inst 11593500 # number of demand (read+write) miss cycles
540 system.cpu.l2cache.demand_miss_latency::cpu.data 4947000 # number of demand (read+write) miss cycles
541 system.cpu.l2cache.demand_miss_latency::total 16540500 # number of demand (read+write) miss cycles
542 system.cpu.l2cache.overall_miss_latency::cpu.inst 11593500 # number of overall miss cycles
543 system.cpu.l2cache.overall_miss_latency::cpu.data 4947000 # number of overall miss cycles
544 system.cpu.l2cache.overall_miss_latency::total 16540500 # number of overall miss cycles
545 system.cpu.l2cache.ReadReq_accesses::cpu.inst 341 # number of ReadReq accesses(hits+misses)
546 system.cpu.l2cache.ReadReq_accesses::cpu.data 92 # number of ReadReq accesses(hits+misses)
547 system.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses)
548 system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
549 system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
550 system.cpu.l2cache.demand_accesses::cpu.inst 341 # number of demand (read+write) accesses
551 system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses
552 system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses
553 system.cpu.l2cache.overall_accesses::cpu.inst 341 # number of overall (read+write) accesses
554 system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses
555 system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses
556 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991202 # miss rate for ReadReq accesses
557 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
558 system.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses
559 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
560 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
561 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991202 # miss rate for demand accesses
562 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
563 system.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses
564 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991202 # miss rate for overall accesses
565 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
566 system.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses
567 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858 # average ReadReq miss latency
568 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043 # average ReadReq miss latency
569 system.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372 # average ReadReq miss latency
570 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588 # average ReadExReq miss latency
571 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588 # average ReadExReq miss latency
572 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency
573 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency
574 system.cpu.l2cache.demand_avg_miss_latency::total 34387.733888 # average overall miss latency
575 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency
576 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency
577 system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency
578 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
579 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
580 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
581 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
582 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
583 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
584 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
585 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
586 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
587 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses
588 system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
589 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
590 system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
591 system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
592 system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
593 system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses
594 system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
595 system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
596 system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses
597 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10498500 # number of ReadReq MSHR miss cycles
598 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2890500 # number of ReadReq MSHR miss cycles
599 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13389000 # number of ReadReq MSHR miss cycles
600 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles
601 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles
602 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10498500 # number of demand (read+write) MSHR miss cycles
603 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4494500 # number of demand (read+write) MSHR miss cycles
604 system.cpu.l2cache.demand_mshr_miss_latency::total 14993000 # number of demand (read+write) MSHR miss cycles
605 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10498500 # number of overall MSHR miss cycles
606 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4494500 # number of overall MSHR miss cycles
607 system.cpu.l2cache.overall_mshr_miss_latency::total 14993000 # number of overall MSHR miss cycles
608 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for ReadReq accesses
609 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
610 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses
611 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
612 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
613 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for demand accesses
614 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
615 system.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses
616 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for overall accesses
617 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
618 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses
619 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888 # average ReadReq mshr miss latency
620 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261 # average ReadReq mshr miss latency
621 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302 # average ReadReq mshr miss latency
622 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency
623 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency
624 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency
625 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency
626 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency
627 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency
628 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency
629 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency
630 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
632 ---------- End Simulation Statistics ----------
projects / gem5.git / blob