2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000023 # Number of seconds simulated
4 sim_ticks 22532000 # Number of ticks simulated
5 final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 96442 # Simulator instruction rate (inst/s)
8 host_op_rate 96403 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 434426491 # Simulator tick rate (ticks/s)
10 host_mem_usage 247240 # Number of bytes of host memory used
11 host_seconds 0.05 # Real time elapsed on the host
12 sim_insts 4999 # Number of instructions simulated
13 sim_ops 4999 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 934493165 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 397656666 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 1332149831 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 934493165 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 934493165 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 934493165 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 397656666 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 1332149831 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 469 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 29 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 0 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 1 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 0 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 7 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 3 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 13 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 53 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 59 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 76 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 43 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 21 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 51 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 29 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 77 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 7 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 22446500 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 469 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 257.207547 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 176.154447 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 250.139569 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 32 30.19% 30.19% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 32 30.19% 60.38% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 19 17.92% 78.30% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 9 8.49% 86.79% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 4 3.77% 90.57% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 2 1.89% 94.34% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::1024-1151 6 5.66% 100.00% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation
202 system.physmem.totQLat 4611250 # Total ticks spent queuing
203 system.physmem.totMemAccLat 13405000 # Total ticks spent from burst creation until serviced by the DRAM
204 system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
205 system.physmem.avgQLat 9832.09 # Average queueing delay per DRAM burst
206 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
207 system.physmem.avgMemAccLat 28582.09 # Average memory access latency per DRAM burst
208 system.physmem.avgRdBW 1332.15 # Average DRAM read bandwidth in MiByte/s
209 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
210 system.physmem.avgRdBWSys 1332.15 # Average system read bandwidth in MiByte/s
211 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
212 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
213 system.physmem.busUtil 10.41 # Data bus utilization in percentage
214 system.physmem.busUtilRead 10.41 # Data bus utilization in percentage for reads
215 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
216 system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
217 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
218 system.physmem.readRowHits 353 # Number of row buffer hits during reads
219 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
220 system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads
221 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
222 system.physmem.avgGap 47860.34 # Average gap between requests
223 system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined
224 system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
225 system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
226 system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ)
227 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
228 system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
229 system.physmem_0.actBackEnergy 9591390 # Energy for active background per rank (pJ)
230 system.physmem_0.preBackEnergy 1086000 # Energy for precharge background per rank (pJ)
231 system.physmem_0.totalEnergy 12431355 # Total energy per rank (pJ)
232 system.physmem_0.averagePower 785.179536 # Core power per rank (mW)
233 system.physmem_0.memoryStateTime::IDLE 2005750 # Time in different power states
234 system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
235 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
236 system.physmem_0.memoryStateTime::ACT 13559250 # Time in different power states
237 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
238 system.physmem_1.actEnergy 529200 # Energy for activate commands per rank (pJ)
239 system.physmem_1.preEnergy 288750 # Energy for precharge commands per rank (pJ)
240 system.physmem_1.readEnergy 2176200 # Energy for read commands per rank (pJ)
241 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
242 system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
243 system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
244 system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
245 system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ)
246 system.physmem_1.averagePower 936.587399 # Core power per rank (mW)
247 system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
248 system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
249 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
250 system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
251 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
252 system.cpu.branchPred.lookups 2183 # Number of BP lookups
253 system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted
254 system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect
255 system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups
256 system.cpu.branchPred.BTBHits 587 # Number of BTB hits
257 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
258 system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage
259 system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target.
260 system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
261 system.cpu.branchPred.indirectLookups 269 # Number of indirect predictor lookups.
262 system.cpu.branchPred.indirectHits 2 # Number of indirect target hits.
263 system.cpu.branchPred.indirectMisses 267 # Number of indirect misses.
264 system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches.
265 system.cpu_clk_domain.clock 500 # Clock period in ticks
266 system.cpu.dtb.read_hits 0 # DTB read hits
267 system.cpu.dtb.read_misses 0 # DTB read misses
268 system.cpu.dtb.read_accesses 0 # DTB read accesses
269 system.cpu.dtb.write_hits 0 # DTB write hits
270 system.cpu.dtb.write_misses 0 # DTB write misses
271 system.cpu.dtb.write_accesses 0 # DTB write accesses
272 system.cpu.dtb.hits 0 # DTB hits
273 system.cpu.dtb.misses 0 # DTB misses
274 system.cpu.dtb.accesses 0 # DTB accesses
275 system.cpu.itb.read_hits 0 # DTB read hits
276 system.cpu.itb.read_misses 0 # DTB read misses
277 system.cpu.itb.read_accesses 0 # DTB read accesses
278 system.cpu.itb.write_hits 0 # DTB write hits
279 system.cpu.itb.write_misses 0 # DTB write misses
280 system.cpu.itb.write_accesses 0 # DTB write accesses
281 system.cpu.itb.hits 0 # DTB hits
282 system.cpu.itb.misses 0 # DTB misses
283 system.cpu.itb.accesses 0 # DTB accesses
284 system.cpu.workload.num_syscalls 7 # Number of system calls
285 system.cpu.numCycles 45065 # number of cpu cycles simulated
286 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
288 system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss
289 system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed
290 system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered
291 system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken
292 system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked
293 system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing
294 system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
295 system.cpu.fetch.CacheLines 2047 # Number of cache lines fetched
296 system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
297 system.cpu.fetch.rateDist::samples 14454 # Number of instructions fetched each cycle (Total)
298 system.cpu.fetch.rateDist::mean 0.898436 # Number of instructions fetched each cycle (Total)
299 system.cpu.fetch.rateDist::stdev 2.187928 # Number of instructions fetched each cycle (Total)
300 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
301 system.cpu.fetch.rateDist::0 11097 76.77% 76.77% # Number of instructions fetched each cycle (Total)
302 system.cpu.fetch.rateDist::1 1507 10.43% 87.20% # Number of instructions fetched each cycle (Total)
303 system.cpu.fetch.rateDist::2 110 0.76% 87.96% # Number of instructions fetched each cycle (Total)
304 system.cpu.fetch.rateDist::3 162 1.12% 89.08% # Number of instructions fetched each cycle (Total)
305 system.cpu.fetch.rateDist::4 279 1.93% 91.01% # Number of instructions fetched each cycle (Total)
306 system.cpu.fetch.rateDist::5 99 0.68% 91.70% # Number of instructions fetched each cycle (Total)
307 system.cpu.fetch.rateDist::6 140 0.97% 92.67% # Number of instructions fetched each cycle (Total)
308 system.cpu.fetch.rateDist::7 158 1.09% 93.76% # Number of instructions fetched each cycle (Total)
309 system.cpu.fetch.rateDist::8 902 6.24% 100.00% # Number of instructions fetched each cycle (Total)
310 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
311 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
312 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
313 system.cpu.fetch.rateDist::total 14454 # Number of instructions fetched each cycle (Total)
314 system.cpu.fetch.branchRate 0.048441 # Number of branch fetches per cycle
315 system.cpu.fetch.rate 0.288162 # Number of inst fetches per cycle
316 system.cpu.decode.IdleCycles 8443 # Number of cycles decode is idle
317 system.cpu.decode.BlockedCycles 2703 # Number of cycles decode is blocked
318 system.cpu.decode.RunCycles 2773 # Number of cycles decode is running
319 system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking
320 system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing
321 system.cpu.decode.BranchResolved 182 # Number of times decode resolved a branch
322 system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction
323 system.cpu.decode.DecodedInsts 12006 # Number of instructions handled by decode
324 system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode
325 system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing
326 system.cpu.rename.IdleCycles 8593 # Number of cycles rename is idle
327 system.cpu.rename.BlockCycles 592 # Number of cycles rename is blocking
328 system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
329 system.cpu.rename.RunCycles 2745 # Number of cycles rename is running
330 system.cpu.rename.UnblockCycles 1156 # Number of cycles rename is unblocking
331 system.cpu.rename.RenamedInsts 11571 # Number of instructions processed by rename
332 system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
333 system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
334 system.cpu.rename.LQFullEvents 175 # Number of times rename has blocked due to LQ full
335 system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
336 system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed
337 system.cpu.rename.RenameLookups 13573 # Number of register rename lookups that rename has made
338 system.cpu.rename.int_rename_lookups 13340 # Number of integer rename lookups
339 system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
340 system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed
341 system.cpu.rename.UndoneMaps 3648 # Number of HB maps that are undone due to squashing
342 system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
343 system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
344 system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer
345 system.cpu.memDep0.insertedLoads 2471 # Number of loads inserted to the mem dependence unit.
346 system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
347 system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
348 system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
349 system.cpu.iq.iqInstsAdded 9030 # Number of instructions added to the IQ (excludes non-spec)
350 system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ
351 system.cpu.iq.iqInstsIssued 8122 # Number of instructions issued
352 system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
353 system.cpu.iq.iqSquashedInstsExamined 4040 # Number of squashed instructions iterated over during squash; mainly for profiling
354 system.cpu.iq.iqSquashedOperandsExamined 2024 # Number of squashed operands that are examined and possibly removed from graph
355 system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
356 system.cpu.iq.issued_per_cycle::samples 14454 # Number of insts issued each cycle
357 system.cpu.iq.issued_per_cycle::mean 0.561921 # Number of insts issued each cycle
358 system.cpu.iq.issued_per_cycle::stdev 1.290505 # Number of insts issued each cycle
359 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
360 system.cpu.iq.issued_per_cycle::0 11129 77.00% 77.00% # Number of insts issued each cycle
361 system.cpu.iq.issued_per_cycle::1 1334 9.23% 86.23% # Number of insts issued each cycle
362 system.cpu.iq.issued_per_cycle::2 725 5.02% 91.24% # Number of insts issued each cycle
363 system.cpu.iq.issued_per_cycle::3 461 3.19% 94.43% # Number of insts issued each cycle
364 system.cpu.iq.issued_per_cycle::4 340 2.35% 96.78% # Number of insts issued each cycle
365 system.cpu.iq.issued_per_cycle::5 284 1.96% 98.75% # Number of insts issued each cycle
366 system.cpu.iq.issued_per_cycle::6 111 0.77% 99.52% # Number of insts issued each cycle
367 system.cpu.iq.issued_per_cycle::7 51 0.35% 99.87% # Number of insts issued each cycle
368 system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
369 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
370 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
371 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
372 system.cpu.iq.issued_per_cycle::total 14454 # Number of insts issued each cycle
373 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
374 system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available
375 system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available
376 system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available
377 system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available
378 system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available
379 system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available
380 system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available
381 system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available
382 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
383 system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available
384 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available
385 system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available
386 system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available
387 system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available
388 system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available
389 system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available
390 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available
391 system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available
392 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available
393 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available
394 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available
395 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available
396 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available
397 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available
398 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available
399 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available
400 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available
401 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available
402 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
403 system.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available
404 system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available
405 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
406 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
407 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
408 system.cpu.iq.FU_type_0::IntAlu 4782 58.88% 58.88% # Type of FU issued
409 system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued
410 system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued
411 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.96% # Type of FU issued
412 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.96% # Type of FU issued
413 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.96% # Type of FU issued
414 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.96% # Type of FU issued
415 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.96% # Type of FU issued
416 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.96% # Type of FU issued
417 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.96% # Type of FU issued
418 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.96% # Type of FU issued
419 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.96% # Type of FU issued
420 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.96% # Type of FU issued
421 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.96% # Type of FU issued
422 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.96% # Type of FU issued
423 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.96% # Type of FU issued
424 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.96% # Type of FU issued
425 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.96% # Type of FU issued
426 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.96% # Type of FU issued
427 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.96% # Type of FU issued
428 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.96% # Type of FU issued
429 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.96% # Type of FU issued
430 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.96% # Type of FU issued
431 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.96% # Type of FU issued
432 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.96% # Type of FU issued
433 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.96% # Type of FU issued
434 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.96% # Type of FU issued
435 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.96% # Type of FU issued
436 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.96% # Type of FU issued
437 system.cpu.iq.FU_type_0::MemRead 2272 27.97% 86.94% # Type of FU issued
438 system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued
439 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
440 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
441 system.cpu.iq.FU_type_0::total 8122 # Type of FU issued
442 system.cpu.iq.rate 0.180229 # Inst issue rate
443 system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
444 system.cpu.iq.fu_busy_rate 0.022285 # FU busy rate (busy events/executed inst)
445 system.cpu.iq.int_inst_queue_reads 30894 # Number of integer instruction queue reads
446 system.cpu.iq.int_inst_queue_writes 13087 # Number of integer instruction queue writes
447 system.cpu.iq.int_inst_queue_wakeup_accesses 7350 # Number of integer instruction queue wakeup accesses
448 system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
449 system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
450 system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
451 system.cpu.iq.int_alu_accesses 8301 # Number of integer alu accesses
452 system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
453 system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
454 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
455 system.cpu.iew.lsq.thread0.squashedLoads 1336 # Number of loads squashed
456 system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
457 system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
458 system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
459 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
460 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
461 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
462 system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
463 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
464 system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing
465 system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
466 system.cpu.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
467 system.cpu.iew.iewDispatchedInsts 10642 # Number of instructions dispatched to IQ
468 system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch
469 system.cpu.iew.iewDispLoadInsts 2471 # Number of dispatched load instructions
470 system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
471 system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions
472 system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
473 system.cpu.iew.iewLSQFullEvents 57 # Number of times the LSQ has become full, causing a stall
474 system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
475 system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
476 system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly
477 system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute
478 system.cpu.iew.iewExecutedInsts 7800 # Number of executed instructions
479 system.cpu.iew.iewExecLoadInsts 2128 # Number of load instructions executed
480 system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute
481 system.cpu.iew.exec_swp 0 # number of swp insts executed
482 system.cpu.iew.exec_nop 1602 # number of nop insts executed
483 system.cpu.iew.exec_refs 3177 # number of memory reference insts executed
484 system.cpu.iew.exec_branches 1369 # Number of branches executed
485 system.cpu.iew.exec_stores 1049 # Number of stores executed
486 system.cpu.iew.exec_rate 0.173083 # Inst execution rate
487 system.cpu.iew.wb_sent 7447 # cumulative count of insts sent to commit
488 system.cpu.iew.wb_count 7352 # cumulative count of insts written-back
489 system.cpu.iew.wb_producers 2874 # num instructions producing a value
490 system.cpu.iew.wb_consumers 4285 # num instructions consuming a value
491 system.cpu.iew.wb_rate 0.163142 # insts written-back per cycle
492 system.cpu.iew.wb_fanout 0.670712 # average fanout of values written-back
493 system.cpu.commit.commitSquashedInsts 4995 # The number of squashed insts skipped by commit
494 system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
495 system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted
496 system.cpu.commit.committed_per_cycle::samples 13572 # Number of insts commited each cycle
497 system.cpu.commit.committed_per_cycle::mean 0.415561 # Number of insts commited each cycle
498 system.cpu.commit.committed_per_cycle::stdev 1.228101 # Number of insts commited each cycle
499 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
500 system.cpu.commit.committed_per_cycle::0 11381 83.86% 83.86% # Number of insts commited each cycle
501 system.cpu.commit.committed_per_cycle::1 886 6.53% 90.38% # Number of insts commited each cycle
502 system.cpu.commit.committed_per_cycle::2 519 3.82% 94.21% # Number of insts commited each cycle
503 system.cpu.commit.committed_per_cycle::3 254 1.87% 96.08% # Number of insts commited each cycle
504 system.cpu.commit.committed_per_cycle::4 162 1.19% 97.27% # Number of insts commited each cycle
505 system.cpu.commit.committed_per_cycle::5 163 1.20% 98.47% # Number of insts commited each cycle
506 system.cpu.commit.committed_per_cycle::6 62 0.46% 98.93% # Number of insts commited each cycle
507 system.cpu.commit.committed_per_cycle::7 41 0.30% 99.23% # Number of insts commited each cycle
508 system.cpu.commit.committed_per_cycle::8 104 0.77% 100.00% # Number of insts commited each cycle
509 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
510 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
511 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
512 system.cpu.commit.committed_per_cycle::total 13572 # Number of insts commited each cycle
513 system.cpu.commit.committedInsts 5640 # Number of instructions committed
514 system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed
515 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
516 system.cpu.commit.refs 2036 # Number of memory references committed
517 system.cpu.commit.loads 1135 # Number of loads committed
518 system.cpu.commit.membars 0 # Number of memory barriers committed
519 system.cpu.commit.branches 886 # Number of branches committed
520 system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
521 system.cpu.commit.int_insts 4955 # Number of committed integer instructions.
522 system.cpu.commit.function_calls 85 # Number of function calls committed.
523 system.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction
524 system.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction
525 system.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction
526 system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction
527 system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction
528 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction
529 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction
530 system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction
531 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction
532 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction
533 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction
534 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction
535 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction
536 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction
537 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction
538 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction
539 system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction
540 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction
541 system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction
542 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction
543 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction
544 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction
545 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction
546 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction
547 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction
548 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction
549 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction
550 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction
551 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction
552 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction
553 system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction
554 system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction
555 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
556 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
557 system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
558 system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached
559 system.cpu.rob.rob_reads 24090 # The number of ROB reads
560 system.cpu.rob.rob_writes 22160 # The number of ROB writes
561 system.cpu.timesIdled 263 # Number of times that the entire CPU went into an idle state and unscheduled itself
562 system.cpu.idleCycles 30611 # Total number of cycles that the CPU has spent unscheduled due to idling
563 system.cpu.committedInsts 4999 # Number of Instructions Simulated
564 system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
565 system.cpu.cpi 9.014803 # CPI: Cycles Per Instruction
566 system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads
567 system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle
568 system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads
569 system.cpu.int_regfile_reads 10573 # number of integer regfile reads
570 system.cpu.int_regfile_writes 5151 # number of integer regfile writes
571 system.cpu.fp_regfile_reads 3 # number of floating regfile reads
572 system.cpu.fp_regfile_writes 1 # number of floating regfile writes
573 system.cpu.misc_regfile_reads 160 # number of misc regfile reads
574 system.cpu.dcache.tags.replacements 0 # number of replacements
575 system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use
576 system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks.
577 system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks.
578 system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks.
579 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
580 system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor
581 system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy
582 system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy
583 system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id
584 system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
585 system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
586 system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
587 system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses
588 system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses
589 system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
590 system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
591 system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
592 system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
593 system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits
594 system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits
595 system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits
596 system.cpu.dcache.overall_hits::total 2393 # number of overall hits
597 system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
598 system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
599 system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
600 system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
601 system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
602 system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
603 system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
604 system.cpu.dcache.overall_misses::total 512 # number of overall misses
605 system.cpu.dcache.ReadReq_miss_latency::cpu.data 11867500 # number of ReadReq miss cycles
606 system.cpu.dcache.ReadReq_miss_latency::total 11867500 # number of ReadReq miss cycles
607 system.cpu.dcache.WriteReq_miss_latency::cpu.data 24012499 # number of WriteReq miss cycles
608 system.cpu.dcache.WriteReq_miss_latency::total 24012499 # number of WriteReq miss cycles
609 system.cpu.dcache.demand_miss_latency::cpu.data 35879999 # number of demand (read+write) miss cycles
610 system.cpu.dcache.demand_miss_latency::total 35879999 # number of demand (read+write) miss cycles
611 system.cpu.dcache.overall_miss_latency::cpu.data 35879999 # number of overall miss cycles
612 system.cpu.dcache.overall_miss_latency::total 35879999 # number of overall miss cycles
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614 system.cpu.dcache.ReadReq_accesses::total 2004 # number of ReadReq accesses(hits+misses)
615 system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
616 system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
617 system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses
618 system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses
619 system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses
620 system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses
621 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083333 # miss rate for ReadReq accesses
622 system.cpu.dcache.ReadReq_miss_rate::total 0.083333 # miss rate for ReadReq accesses
623 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
624 system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
625 system.cpu.dcache.demand_miss_rate::cpu.data 0.176248 # miss rate for demand accesses
626 system.cpu.dcache.demand_miss_rate::total 0.176248 # miss rate for demand accesses
627 system.cpu.dcache.overall_miss_rate::cpu.data 0.176248 # miss rate for overall accesses
628 system.cpu.dcache.overall_miss_rate::total 0.176248 # miss rate for overall accesses
629 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71062.874251 # average ReadReq miss latency
630 system.cpu.dcache.ReadReq_avg_miss_latency::total 71062.874251 # average ReadReq miss latency
631 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69601.446377 # average WriteReq miss latency
632 system.cpu.dcache.WriteReq_avg_miss_latency::total 69601.446377 # average WriteReq miss latency
633 system.cpu.dcache.demand_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
634 system.cpu.dcache.demand_avg_miss_latency::total 70078.123047 # average overall miss latency
635 system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
636 system.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency
637 system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked
638 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
639 system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
640 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
641 system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked
642 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
643 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits
644 system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
645 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
646 system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
647 system.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits
648 system.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits
649 system.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits
650 system.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits
651 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
652 system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
653 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
654 system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
655 system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
656 system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses
657 system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
658 system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses
659 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7550000 # number of ReadReq MSHR miss cycles
660 system.cpu.dcache.ReadReq_mshr_miss_latency::total 7550000 # number of ReadReq MSHR miss cycles
661 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4082999 # number of WriteReq MSHR miss cycles
662 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4082999 # number of WriteReq MSHR miss cycles
663 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11632999 # number of demand (read+write) MSHR miss cycles
664 system.cpu.dcache.demand_mshr_miss_latency::total 11632999 # number of demand (read+write) MSHR miss cycles
665 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11632999 # number of overall MSHR miss cycles
666 system.cpu.dcache.overall_mshr_miss_latency::total 11632999 # number of overall MSHR miss cycles
667 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044910 # mshr miss rate for ReadReq accesses
668 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044910 # mshr miss rate for ReadReq accesses
669 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
670 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
671 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for demand accesses
672 system.cpu.dcache.demand_mshr_miss_rate::total 0.048193 # mshr miss rate for demand accesses
673 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for overall accesses
674 system.cpu.dcache.overall_mshr_miss_rate::total 0.048193 # mshr miss rate for overall accesses
675 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency
676 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency
677 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency
678 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency
679 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
680 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
681 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
682 system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
683 system.cpu.icache.tags.replacements 17 # number of replacements
684 system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use
685 system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
686 system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks.
687 system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks.
688 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
689 system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor
690 system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy
691 system.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy
692 system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id
693 system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
694 system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
695 system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id
696 system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses
697 system.cpu.icache.tags.data_accesses 4426 # Number of data accesses
698 system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits
699 system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits
700 system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits
701 system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits
702 system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits
703 system.cpu.icache.overall_hits::total 1610 # number of overall hits
704 system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
705 system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
706 system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
707 system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
708 system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
709 system.cpu.icache.overall_misses::total 437 # number of overall misses
710 system.cpu.icache.ReadReq_miss_latency::cpu.inst 32774000 # number of ReadReq miss cycles
711 system.cpu.icache.ReadReq_miss_latency::total 32774000 # number of ReadReq miss cycles
712 system.cpu.icache.demand_miss_latency::cpu.inst 32774000 # number of demand (read+write) miss cycles
713 system.cpu.icache.demand_miss_latency::total 32774000 # number of demand (read+write) miss cycles
714 system.cpu.icache.overall_miss_latency::cpu.inst 32774000 # number of overall miss cycles
715 system.cpu.icache.overall_miss_latency::total 32774000 # number of overall miss cycles
716 system.cpu.icache.ReadReq_accesses::cpu.inst 2047 # number of ReadReq accesses(hits+misses)
717 system.cpu.icache.ReadReq_accesses::total 2047 # number of ReadReq accesses(hits+misses)
718 system.cpu.icache.demand_accesses::cpu.inst 2047 # number of demand (read+write) accesses
719 system.cpu.icache.demand_accesses::total 2047 # number of demand (read+write) accesses
720 system.cpu.icache.overall_accesses::cpu.inst 2047 # number of overall (read+write) accesses
721 system.cpu.icache.overall_accesses::total 2047 # number of overall (read+write) accesses
722 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213483 # miss rate for ReadReq accesses
723 system.cpu.icache.ReadReq_miss_rate::total 0.213483 # miss rate for ReadReq accesses
724 system.cpu.icache.demand_miss_rate::cpu.inst 0.213483 # miss rate for demand accesses
725 system.cpu.icache.demand_miss_rate::total 0.213483 # miss rate for demand accesses
726 system.cpu.icache.overall_miss_rate::cpu.inst 0.213483 # miss rate for overall accesses
727 system.cpu.icache.overall_miss_rate::total 0.213483 # miss rate for overall accesses
728 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74997.711670 # average ReadReq miss latency
729 system.cpu.icache.ReadReq_avg_miss_latency::total 74997.711670 # average ReadReq miss latency
730 system.cpu.icache.demand_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency
731 system.cpu.icache.demand_avg_miss_latency::total 74997.711670 # average overall miss latency
732 system.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency
733 system.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency
734 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
735 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
736 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
737 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
738 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
739 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
740 system.cpu.icache.writebacks::writebacks 17 # number of writebacks
741 system.cpu.icache.writebacks::total 17 # number of writebacks
742 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits
743 system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits
744 system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits
745 system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits
746 system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits
747 system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits
748 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses
749 system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses
750 system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses
751 system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses
752 system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses
753 system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses
754 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26055500 # number of ReadReq MSHR miss cycles
755 system.cpu.icache.ReadReq_mshr_miss_latency::total 26055500 # number of ReadReq MSHR miss cycles
756 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26055500 # number of demand (read+write) MSHR miss cycles
757 system.cpu.icache.demand_mshr_miss_latency::total 26055500 # number of demand (read+write) MSHR miss cycles
758 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26055500 # number of overall MSHR miss cycles
759 system.cpu.icache.overall_mshr_miss_latency::total 26055500 # number of overall MSHR miss cycles
760 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for ReadReq accesses
761 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162189 # mshr miss rate for ReadReq accesses
762 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for demand accesses
763 system.cpu.icache.demand_mshr_miss_rate::total 0.162189 # mshr miss rate for demand accesses
764 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses
765 system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses
766 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency
767 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency
768 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
769 system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
770 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
771 system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
772 system.cpu.l2cache.tags.replacements 0 # number of replacements
773 system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use
774 system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
775 system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
776 system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
777 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
778 system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor
779 system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor
780 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy
781 system.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy
782 system.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy
783 system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
784 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
785 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
786 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
787 system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
788 system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
789 system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
790 system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
791 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
792 system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
793 system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
794 system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
795 system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
796 system.cpu.l2cache.overall_hits::total 3 # number of overall hits
797 system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
798 system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
799 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 329 # number of ReadCleanReq misses
800 system.cpu.l2cache.ReadCleanReq_misses::total 329 # number of ReadCleanReq misses
801 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses
802 system.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses
803 system.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses
804 system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses
805 system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
806 system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses
807 system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses
808 system.cpu.l2cache.overall_misses::total 469 # number of overall misses
809 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007000 # number of ReadExReq miss cycles
810 system.cpu.l2cache.ReadExReq_miss_latency::total 4007000 # number of ReadExReq miss cycles
811 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25524500 # number of ReadCleanReq miss cycles
812 system.cpu.l2cache.ReadCleanReq_miss_latency::total 25524500 # number of ReadCleanReq miss cycles
813 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7412000 # number of ReadSharedReq miss cycles
814 system.cpu.l2cache.ReadSharedReq_miss_latency::total 7412000 # number of ReadSharedReq miss cycles
815 system.cpu.l2cache.demand_miss_latency::cpu.inst 25524500 # number of demand (read+write) miss cycles
816 system.cpu.l2cache.demand_miss_latency::cpu.data 11419000 # number of demand (read+write) miss cycles
817 system.cpu.l2cache.demand_miss_latency::total 36943500 # number of demand (read+write) miss cycles
818 system.cpu.l2cache.overall_miss_latency::cpu.inst 25524500 # number of overall miss cycles
819 system.cpu.l2cache.overall_miss_latency::cpu.data 11419000 # number of overall miss cycles
820 system.cpu.l2cache.overall_miss_latency::total 36943500 # number of overall miss cycles
821 system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
822 system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
823 system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
824 system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
825 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses)
826 system.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses)
827 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses)
828 system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses)
829 system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses
830 system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses
831 system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses
832 system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses
833 system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses
834 system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses
835 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
836 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
837 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990964 # miss rate for ReadCleanReq accesses
838 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990964 # miss rate for ReadCleanReq accesses
839 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
840 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
841 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses
842 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
843 system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses
844 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses
845 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
846 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
847 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80140 # average ReadExReq miss latency
848 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80140 # average ReadExReq miss latency
849 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77582.066869 # average ReadCleanReq miss latency
850 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77582.066869 # average ReadCleanReq miss latency
851 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82355.555556 # average ReadSharedReq miss latency
852 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82355.555556 # average ReadSharedReq miss latency
853 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency
854 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency
855 system.cpu.l2cache.demand_avg_miss_latency::total 78770.788913 # average overall miss latency
856 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency
857 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency
858 system.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency
859 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
860 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
861 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
862 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
863 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
864 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
865 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
866 system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
867 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses
868 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses
869 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses
870 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses
871 system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses
872 system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
873 system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
874 system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses
875 system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
876 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
877 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507000 # number of ReadExReq MSHR miss cycles
878 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507000 # number of ReadExReq MSHR miss cycles
879 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22234500 # number of ReadCleanReq MSHR miss cycles
880 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500 # number of ReadCleanReq MSHR miss cycles
881 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles
882 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles
883 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles
884 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles
885 system.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles
886 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles
887 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles
888 system.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles
889 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
890 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
891 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses
892 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses
893 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
894 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
895 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses
896 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
897 system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
898 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses
899 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
900 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
901 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70140 # average ReadExReq mshr miss latency
902 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70140 # average ReadExReq mshr miss latency
903 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67582.066869 # average ReadCleanReq mshr miss latency
904 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67582.066869 # average ReadCleanReq mshr miss latency
905 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency
906 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency
907 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency
908 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency
909 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency
910 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency
911 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency
912 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency
913 system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
914 system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
915 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
916 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
917 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
918 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
919 system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
920 system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
921 system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
922 system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
923 system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution
924 system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution
925 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes)
926 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes)
927 system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
928 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
929 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes)
930 system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
931 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
932 system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
933 system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
934 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
935 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
936 system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
937 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
938 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
939 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
940 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
941 system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
942 system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
943 system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
944 system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
945 system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks)
946 system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
947 system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks)
948 system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
949 system.membus.trans_dist::ReadResp 419 # Transaction distribution
950 system.membus.trans_dist::ReadExReq 50 # Transaction distribution
951 system.membus.trans_dist::ReadExResp 50 # Transaction distribution
952 system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
953 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
954 system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
955 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
956 system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
957 system.membus.snoops 0 # Total snoops (count)
958 system.membus.snoop_fanout::samples 469 # Request fanout histogram
959 system.membus.snoop_fanout::mean 0 # Request fanout histogram
960 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
961 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
962 system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
963 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
964 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
965 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
966 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
967 system.membus.snoop_fanout::total 469 # Request fanout histogram
968 system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks)
969 system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
970 system.membus.respLayer1.occupancy 2494000 # Layer occupancy (ticks)
971 system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
973 ---------- End Simulation Statistics ----------
projects / gem5.git / blob