2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000022 # Number of seconds simulated
4 sim_ticks 21918500 # Number of ticks simulated
5 final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 56826 # Simulator instruction rate (inst/s)
8 host_op_rate 56817 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 241494238 # Simulator tick rate (ticks/s)
10 host_mem_usage 266500 # Number of bytes of host memory used
11 host_seconds 0.09 # Real time elapsed on the host
12 sim_insts 5156 # Number of instructions simulated
13 sim_ops 5156 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 30528 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 477 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 477 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 30 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 0 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 1 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 0 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 7 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 3 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 13 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 54 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 63 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 77 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 44 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 20 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 51 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 29 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 77 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 8 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 21839000 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 477 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation
202 system.physmem.totQLat 2715000 # Total ticks spent queuing
203 system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM
204 system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers
205 system.physmem.totBankLat 8676250 # Total ticks spent accessing banks
206 system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst
207 system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst
208 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209 system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst
210 system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s
211 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212 system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s
213 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215 system.physmem.busUtil 10.88 # Data bus utilization in percentage
216 system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads
217 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218 system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
219 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220 system.physmem.readRowHits 357 # Number of row buffer hits during reads
221 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222 system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads
223 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224 system.physmem.avgGap 45784.07 # Average gap between requests
225 system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined
226 system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
227 system.membus.throughput 1392796040 # Throughput (bytes/s)
228 system.membus.trans_dist::ReadReq 426 # Transaction distribution
229 system.membus.trans_dist::ReadResp 426 # Transaction distribution
230 system.membus.trans_dist::ReadExReq 51 # Transaction distribution
231 system.membus.trans_dist::ReadExResp 51 # Transaction distribution
232 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes)
233 system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes)
234 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes)
235 system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes)
236 system.membus.data_through_bus 30528 # Total data (bytes)
237 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
238 system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
239 system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
240 system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks)
241 system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
242 system.cpu_clk_domain.clock 500 # Clock period in ticks
243 system.cpu.branchPred.lookups 2174 # Number of BP lookups
244 system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted
245 system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect
246 system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups
247 system.cpu.branchPred.BTBHits 492 # Number of BTB hits
248 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
249 system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage
250 system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target.
251 system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions.
252 system.cpu.dtb.read_hits 0 # DTB read hits
253 system.cpu.dtb.read_misses 0 # DTB read misses
254 system.cpu.dtb.read_accesses 0 # DTB read accesses
255 system.cpu.dtb.write_hits 0 # DTB write hits
256 system.cpu.dtb.write_misses 0 # DTB write misses
257 system.cpu.dtb.write_accesses 0 # DTB write accesses
258 system.cpu.dtb.hits 0 # DTB hits
259 system.cpu.dtb.misses 0 # DTB misses
260 system.cpu.dtb.accesses 0 # DTB accesses
261 system.cpu.itb.read_hits 0 # DTB read hits
262 system.cpu.itb.read_misses 0 # DTB read misses
263 system.cpu.itb.read_accesses 0 # DTB read accesses
264 system.cpu.itb.write_hits 0 # DTB write hits
265 system.cpu.itb.write_misses 0 # DTB write misses
266 system.cpu.itb.write_accesses 0 # DTB write accesses
267 system.cpu.itb.hits 0 # DTB hits
268 system.cpu.itb.misses 0 # DTB misses
269 system.cpu.itb.accesses 0 # DTB accesses
270 system.cpu.workload.num_syscalls 8 # Number of system calls
271 system.cpu.numCycles 43838 # number of cpu cycles simulated
272 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
273 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
274 system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss
275 system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed
276 system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
277 system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
278 system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked
279 system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing
280 system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked
281 system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
282 system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched
283 system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed
284 system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total)
285 system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total)
286 system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total)
287 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
288 system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total)
289 system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total)
290 system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total)
291 system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total)
292 system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total)
293 system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total)
294 system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total)
295 system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total)
296 system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total)
297 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
298 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
299 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
300 system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total)
301 system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle
302 system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle
303 system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle
304 system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked
305 system.cpu.decode.RunCycles 3025 # Number of cycles decode is running
306 system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
307 system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing
308 system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch
309 system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
310 system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode
311 system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
312 system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing
313 system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle
314 system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking
315 system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst
316 system.cpu.rename.RunCycles 2898 # Number of cycles rename is running
317 system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
318 system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename
319 system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
320 system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
321 system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
322 system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed
323 system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made
324 system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups
325 system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
326 system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
327 system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing
328 system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
329 system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
330 system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer
331 system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit.
332 system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit.
333 system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
334 system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
335 system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec)
336 system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
337 system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued
338 system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
339 system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling
340 system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph
341 system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
342 system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle
343 system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle
344 system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle
345 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
346 system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle
347 system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle
348 system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle
349 system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle
350 system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle
351 system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle
352 system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle
353 system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle
354 system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
355 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
356 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
357 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
358 system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle
359 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
360 system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available
361 system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
362 system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
363 system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
364 system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
365 system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
366 system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
367 system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
368 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
369 system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
370 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
371 system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
372 system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
373 system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
374 system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
375 system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
376 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
377 system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
378 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
379 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
380 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
381 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
382 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
383 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
384 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
385 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
386 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
387 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
388 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
389 system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available
390 system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available
391 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
392 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
393 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
394 system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued
395 system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued
396 system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued
397 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued
398 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued
399 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued
400 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued
401 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued
402 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued
403 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued
404 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued
405 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued
406 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued
407 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued
408 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued
409 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued
410 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued
411 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued
412 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued
413 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued
414 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued
415 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued
416 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued
417 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued
418 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued
419 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued
420 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued
421 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued
422 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued
423 system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued
424 system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued
425 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
426 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
427 system.cpu.iq.FU_type_0::total 8293 # Type of FU issued
428 system.cpu.iq.rate 0.189174 # Inst issue rate
429 system.cpu.iq.fu_busy_cnt 160 # FU busy when requested
430 system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst)
431 system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads
432 system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes
433 system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses
434 system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
435 system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
436 system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
437 system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses
438 system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
439 system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
440 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
441 system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed
442 system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
443 system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
444 system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed
445 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
446 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
447 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
448 system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked
449 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
450 system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing
451 system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking
452 system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
453 system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ
454 system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
455 system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions
456 system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions
457 system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
458 system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
459 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
460 system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
461 system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
462 system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly
463 system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute
464 system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions
465 system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed
466 system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute
467 system.cpu.iew.exec_swp 0 # number of swp insts executed
468 system.cpu.iew.exec_nop 1512 # number of nop insts executed
469 system.cpu.iew.exec_refs 3186 # number of memory reference insts executed
470 system.cpu.iew.exec_branches 1344 # Number of branches executed
471 system.cpu.iew.exec_stores 1079 # Number of stores executed
472 system.cpu.iew.exec_rate 0.180483 # Inst execution rate
473 system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit
474 system.cpu.iew.wb_count 7455 # cumulative count of insts written-back
475 system.cpu.iew.wb_producers 2921 # num instructions producing a value
476 system.cpu.iew.wb_consumers 4197 # num instructions consuming a value
477 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
478 system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle
479 system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back
480 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
481 system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit
482 system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
483 system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
484 system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle
485 system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle
486 system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle
487 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
488 system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle
489 system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle
490 system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle
491 system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle
492 system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle
493 system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle
494 system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle
495 system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle
496 system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle
497 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
498 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
499 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
500 system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle
501 system.cpu.commit.committedInsts 5813 # Number of instructions committed
502 system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
503 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
504 system.cpu.commit.refs 2088 # Number of memory references committed
505 system.cpu.commit.loads 1163 # Number of loads committed
506 system.cpu.commit.membars 0 # Number of memory barriers committed
507 system.cpu.commit.branches 915 # Number of branches committed
508 system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
509 system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
510 system.cpu.commit.function_calls 87 # Number of function calls committed.
511 system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
512 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
513 system.cpu.rob.rob_reads 24245 # The number of ROB reads
514 system.cpu.rob.rob_writes 22333 # The number of ROB writes
515 system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself
516 system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling
517 system.cpu.committedInsts 5156 # Number of Instructions Simulated
518 system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
519 system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
520 system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction
521 system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads
522 system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle
523 system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads
524 system.cpu.int_regfile_reads 10743 # number of integer regfile reads
525 system.cpu.int_regfile_writes 5234 # number of integer regfile writes
526 system.cpu.fp_regfile_reads 3 # number of floating regfile reads
527 system.cpu.fp_regfile_writes 1 # number of floating regfile writes
528 system.cpu.misc_regfile_reads 148 # number of misc regfile reads
529 system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s)
530 system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution
531 system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
532 system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
533 system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
534 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
535 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes)
536 system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
537 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
538 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
539 system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes)
540 system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes)
541 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
542 system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
543 system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
544 system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks)
545 system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
546 system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks)
547 system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
548 system.cpu.icache.tags.replacements 17 # number of replacements
549 system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use
550 system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks.
551 system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
552 system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks.
553 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
554 system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor
555 system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy
556 system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy
557 system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id
558 system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
559 system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
560 system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id
561 system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses
562 system.cpu.icache.tags.data_accesses 4268 # Number of data accesses
563 system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits
564 system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits
565 system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits
566 system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits
567 system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits
568 system.cpu.icache.overall_hits::total 1514 # number of overall hits
569 system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses
570 system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses
571 system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses
572 system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses
573 system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses
574 system.cpu.icache.overall_misses::total 451 # number of overall misses
575 system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles
576 system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles
577 system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles
578 system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles
579 system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles
580 system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles
581 system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses)
582 system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses)
583 system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses
584 system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses
585 system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses
586 system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses
587 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses
588 system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses
589 system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses
590 system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses
591 system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses
592 system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses
593 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency
594 system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency
595 system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
596 system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency
597 system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
598 system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency
599 system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked
600 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
601 system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
602 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
603 system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked
604 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
605 system.cpu.icache.fast_writes 0 # number of fast writes performed
606 system.cpu.icache.cache_copies 0 # number of cache copies performed
607 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits
608 system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
609 system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits
610 system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits
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614 system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
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620 system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles
621 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles
622 system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles
623 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles
624 system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles
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626 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses
627 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses
628 system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses
629 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses
630 system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses
631 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency
632 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency
633 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
634 system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
635 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
636 system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
637 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
638 system.cpu.l2cache.tags.replacements 0 # number of replacements
639 system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use
640 system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
641 system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
642 system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
643 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
644 system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor
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650 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id
651 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
652 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
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654 system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses
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713 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency
714 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency
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717 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
718 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
719 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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721 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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723 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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726 system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses
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731 system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses
732 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
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734 system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses
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736 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles
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738 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles
739 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles
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743 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles
744 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles
745 system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles
746 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
747 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
748 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses
749 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
750 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
751 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses
752 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
753 system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses
754 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
755 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
756 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses
757 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency
758 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency
759 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency
760 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency
761 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency
762 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
763 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
764 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
765 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
766 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
767 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
768 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
769 system.cpu.dcache.tags.replacements 0 # number of replacements
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771 system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
772 system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
773 system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
774 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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783 system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses
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862 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles
863 system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles
864 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses
865 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses
866 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
867 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
868 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses
869 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses
870 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses
871 system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses
872 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency
873 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency
874 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency
875 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency
876 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
877 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
878 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
879 system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
880 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
882 ---------- End Simulation Statistics ----------
projects / gem5.git / blob