2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000012 # Number of seconds simulated
4 sim_ticks 12097500 # Number of ticks simulated
5 final_tick 12097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 46391 # Simulator instruction rate (inst/s)
8 host_op_rate 46381 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 108798708 # Simulator tick rate (ticks/s)
10 host_mem_usage 217720 # Number of bytes of host memory used
11 host_seconds 0.11 # Real time elapsed on the host
12 sim_insts 5156 # Number of instructions simulated
13 sim_ops 5156 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 30720 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 480 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1793428394 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 745939244 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 2539367638 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1793428394 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1793428394 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1793428394 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 745939244 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 2539367638 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 480 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 30720 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 12035000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 480 # Categorize read packet sizes
81 system.physmem.readPktSize::7 0 # Categorize read packet sizes
82 system.physmem.readPktSize::8 0 # Categorize read packet sizes
83 system.physmem.writePktSize::0 0 # categorize write packet sizes
84 system.physmem.writePktSize::1 0 # categorize write packet sizes
85 system.physmem.writePktSize::2 0 # categorize write packet sizes
86 system.physmem.writePktSize::3 0 # categorize write packet sizes
87 system.physmem.writePktSize::4 0 # categorize write packet sizes
88 system.physmem.writePktSize::5 0 # categorize write packet sizes
89 system.physmem.writePktSize::6 0 # categorize write packet sizes
90 system.physmem.writePktSize::7 0 # categorize write packet sizes
91 system.physmem.writePktSize::8 0 # categorize write packet sizes
92 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
93 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98 system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101 system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
134 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167 system.physmem.totQLat 3039980 # Total cycles spent in queuing delays
168 system.physmem.totMemAccLat 13667980 # Sum of mem lat for all requests
169 system.physmem.totBusLat 1920000 # Total cycles spent in databus access
170 system.physmem.totBankLat 8708000 # Total cycles spent in bank access
171 system.physmem.avgQLat 6333.29 # Average queueing delay per request
172 system.physmem.avgBankLat 18141.67 # Average bank access latency per request
173 system.physmem.avgBusLat 4000.00 # Average bus latency per request
174 system.physmem.avgMemAccLat 28474.96 # Average memory access latency
175 system.physmem.avgRdBW 2539.37 # Average achieved read bandwidth in MB/s
176 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177 system.physmem.avgConsumedRdBW 2539.37 # Average consumed read bandwidth in MB/s
178 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179 system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180 system.physmem.busUtil 15.87 # Data bus utilization in percentage
181 system.physmem.avgRdQLen 1.13 # Average read queue length over time
182 system.physmem.avgWrQLen 0.00 # Average write queue length over time
183 system.physmem.readRowHits 380 # Number of row buffer hits during reads
184 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185 system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads
186 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187 system.physmem.avgGap 25072.92 # Average gap between requests
188 system.cpu.dtb.read_hits 0 # DTB read hits
189 system.cpu.dtb.read_misses 0 # DTB read misses
190 system.cpu.dtb.read_accesses 0 # DTB read accesses
191 system.cpu.dtb.write_hits 0 # DTB write hits
192 system.cpu.dtb.write_misses 0 # DTB write misses
193 system.cpu.dtb.write_accesses 0 # DTB write accesses
194 system.cpu.dtb.hits 0 # DTB hits
195 system.cpu.dtb.misses 0 # DTB misses
196 system.cpu.dtb.accesses 0 # DTB accesses
197 system.cpu.itb.read_hits 0 # DTB read hits
198 system.cpu.itb.read_misses 0 # DTB read misses
199 system.cpu.itb.read_accesses 0 # DTB read accesses
200 system.cpu.itb.write_hits 0 # DTB write hits
201 system.cpu.itb.write_misses 0 # DTB write misses
202 system.cpu.itb.write_accesses 0 # DTB write accesses
203 system.cpu.itb.hits 0 # DTB hits
204 system.cpu.itb.misses 0 # DTB misses
205 system.cpu.itb.accesses 0 # DTB accesses
206 system.cpu.workload.num_syscalls 8 # Number of system calls
207 system.cpu.numCycles 24196 # number of cpu cycles simulated
208 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
209 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
210 system.cpu.BPredUnit.lookups 2174 # Number of BP lookups
211 system.cpu.BPredUnit.condPredicted 1443 # Number of conditional branches predicted
212 system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect
213 system.cpu.BPredUnit.BTBLookups 1705 # Number of BTB lookups
214 system.cpu.BPredUnit.BTBHits 494 # Number of BTB hits
215 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
216 system.cpu.BPredUnit.usedRAS 283 # Number of times the RAS was used to get a target.
217 system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
218 system.cpu.fetch.icacheStallCycles 8516 # Number of cycles fetch is stalled on an Icache miss
219 system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed
220 system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
221 system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken
222 system.cpu.fetch.Cycles 3260 # Number of cycles fetch has run and was not squashing or blocked
223 system.cpu.fetch.SquashCycles 1345 # Number of cycles fetch has spent squashing
224 system.cpu.fetch.BlockedCycles 699 # Number of cycles fetch has spent blocked
225 system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
226 system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps
227 system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
228 system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed
229 system.cpu.fetch.rateDist::samples 13523 # Number of instructions fetched each cycle (Total)
230 system.cpu.fetch.rateDist::mean 0.974414 # Number of instructions fetched each cycle (Total)
231 system.cpu.fetch.rateDist::stdev 2.279455 # Number of instructions fetched each cycle (Total)
232 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
233 system.cpu.fetch.rateDist::0 10263 75.89% 75.89% # Number of instructions fetched each cycle (Total)
234 system.cpu.fetch.rateDist::1 1359 10.05% 85.94% # Number of instructions fetched each cycle (Total)
235 system.cpu.fetch.rateDist::2 113 0.84% 86.78% # Number of instructions fetched each cycle (Total)
236 system.cpu.fetch.rateDist::3 150 1.11% 87.89% # Number of instructions fetched each cycle (Total)
237 system.cpu.fetch.rateDist::4 301 2.23% 90.11% # Number of instructions fetched each cycle (Total)
238 system.cpu.fetch.rateDist::5 101 0.75% 90.86% # Number of instructions fetched each cycle (Total)
239 system.cpu.fetch.rateDist::6 159 1.18% 92.04% # Number of instructions fetched each cycle (Total)
240 system.cpu.fetch.rateDist::7 137 1.01% 93.05% # Number of instructions fetched each cycle (Total)
241 system.cpu.fetch.rateDist::8 940 6.95% 100.00% # Number of instructions fetched each cycle (Total)
242 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
243 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
244 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
245 system.cpu.fetch.rateDist::total 13523 # Number of instructions fetched each cycle (Total)
246 system.cpu.fetch.branchRate 0.089850 # Number of branch fetches per cycle
247 system.cpu.fetch.rate 0.544594 # Number of inst fetches per cycle
248 system.cpu.decode.IdleCycles 8657 # Number of cycles decode is idle
249 system.cpu.decode.BlockedCycles 898 # Number of cycles decode is blocked
250 system.cpu.decode.RunCycles 3079 # Number of cycles decode is running
251 system.cpu.decode.UnblockCycles 45 # Number of cycles decode is unblocking
252 system.cpu.decode.SquashCycles 844 # Number of cycles decode is squashing
253 system.cpu.decode.BranchResolved 154 # Number of times decode resolved a branch
254 system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction
255 system.cpu.decode.DecodedInsts 12246 # Number of instructions handled by decode
256 system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode
257 system.cpu.rename.SquashCycles 844 # Number of cycles rename is squashing
258 system.cpu.rename.IdleCycles 8855 # Number of cycles rename is idle
259 system.cpu.rename.BlockCycles 196 # Number of cycles rename is blocking
260 system.cpu.rename.serializeStallCycles 599 # count of cycles rename stalled for serializing inst
261 system.cpu.rename.RunCycles 2928 # Number of cycles rename is running
262 system.cpu.rename.UnblockCycles 101 # Number of cycles rename is unblocking
263 system.cpu.rename.RenamedInsts 11668 # Number of instructions processed by rename
264 system.cpu.rename.LSQFullEvents 92 # Number of times rename has blocked due to LSQ full
265 system.cpu.rename.RenamedOperands 7112 # Number of destination operands rename has renamed
266 system.cpu.rename.RenameLookups 13873 # Number of register rename lookups that rename has made
267 system.cpu.rename.int_rename_lookups 13869 # Number of integer rename lookups
268 system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
269 system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
270 system.cpu.rename.UndoneMaps 3714 # Number of HB maps that are undone due to squashing
271 system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
272 system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed
273 system.cpu.rename.skidInsts 271 # count of insts added to the skid buffer
274 system.cpu.memDep0.insertedLoads 2456 # Number of loads inserted to the mem dependence unit.
275 system.cpu.memDep0.insertedStores 1189 # Number of stores inserted to the mem dependence unit.
276 system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
277 system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
278 system.cpu.iq.iqInstsAdded 9092 # Number of instructions added to the IQ (excludes non-spec)
279 system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ
280 system.cpu.iq.iqInstsIssued 8231 # Number of instructions issued
281 system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued
282 system.cpu.iq.iqSquashedInstsExamined 3471 # Number of squashed instructions iterated over during squash; mainly for profiling
283 system.cpu.iq.iqSquashedOperandsExamined 1958 # Number of squashed operands that are examined and possibly removed from graph
284 system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
285 system.cpu.iq.issued_per_cycle::samples 13523 # Number of insts issued each cycle
286 system.cpu.iq.issued_per_cycle::mean 0.608667 # Number of insts issued each cycle
287 system.cpu.iq.issued_per_cycle::stdev 1.271089 # Number of insts issued each cycle
288 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
289 system.cpu.iq.issued_per_cycle::0 9982 73.81% 73.81% # Number of insts issued each cycle
290 system.cpu.iq.issued_per_cycle::1 1399 10.35% 84.16% # Number of insts issued each cycle
291 system.cpu.iq.issued_per_cycle::2 867 6.41% 90.57% # Number of insts issued each cycle
292 system.cpu.iq.issued_per_cycle::3 551 4.07% 94.65% # Number of insts issued each cycle
293 system.cpu.iq.issued_per_cycle::4 358 2.65% 97.29% # Number of insts issued each cycle
294 system.cpu.iq.issued_per_cycle::5 239 1.77% 99.06% # Number of insts issued each cycle
295 system.cpu.iq.issued_per_cycle::6 85 0.63% 99.69% # Number of insts issued each cycle
296 system.cpu.iq.issued_per_cycle::7 28 0.21% 99.90% # Number of insts issued each cycle
297 system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
298 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
299 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
300 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
301 system.cpu.iq.issued_per_cycle::total 13523 # Number of insts issued each cycle
302 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
303 system.cpu.iq.fu_full::IntAlu 3 2.00% 2.00% # attempts to use FU when none available
304 system.cpu.iq.fu_full::IntMult 0 0.00% 2.00% # attempts to use FU when none available
305 system.cpu.iq.fu_full::IntDiv 0 0.00% 2.00% # attempts to use FU when none available
306 system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.00% # attempts to use FU when none available
307 system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.00% # attempts to use FU when none available
308 system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.00% # attempts to use FU when none available
309 system.cpu.iq.fu_full::FloatMult 0 0.00% 2.00% # attempts to use FU when none available
310 system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.00% # attempts to use FU when none available
311 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.00% # attempts to use FU when none available
312 system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.00% # attempts to use FU when none available
313 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.00% # attempts to use FU when none available
314 system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.00% # attempts to use FU when none available
315 system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.00% # attempts to use FU when none available
316 system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.00% # attempts to use FU when none available
317 system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.00% # attempts to use FU when none available
318 system.cpu.iq.fu_full::SimdMult 0 0.00% 2.00% # attempts to use FU when none available
319 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.00% # attempts to use FU when none available
320 system.cpu.iq.fu_full::SimdShift 0 0.00% 2.00% # attempts to use FU when none available
321 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.00% # attempts to use FU when none available
322 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.00% # attempts to use FU when none available
323 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.00% # attempts to use FU when none available
324 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.00% # attempts to use FU when none available
325 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.00% # attempts to use FU when none available
326 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.00% # attempts to use FU when none available
327 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.00% # attempts to use FU when none available
328 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.00% # attempts to use FU when none available
329 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.00% # attempts to use FU when none available
330 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.00% # attempts to use FU when none available
331 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.00% # attempts to use FU when none available
332 system.cpu.iq.fu_full::MemRead 95 63.33% 65.33% # attempts to use FU when none available
333 system.cpu.iq.fu_full::MemWrite 52 34.67% 100.00% # attempts to use FU when none available
334 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
335 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
336 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
337 system.cpu.iq.FU_type_0::IntAlu 4866 59.12% 59.12% # Type of FU issued
338 system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued
339 system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued
340 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued
341 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued
342 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued
343 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued
344 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued
345 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued
346 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued
347 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued
348 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued
349 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued
350 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued
351 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued
352 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued
353 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued
354 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued
355 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued
356 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued
357 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued
358 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued
359 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued
360 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued
361 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued
362 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued
363 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued
364 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued
365 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued
366 system.cpu.iq.FU_type_0::MemRead 2254 27.38% 86.61% # Type of FU issued
367 system.cpu.iq.FU_type_0::MemWrite 1102 13.39% 100.00% # Type of FU issued
368 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
369 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
370 system.cpu.iq.FU_type_0::total 8231 # Type of FU issued
371 system.cpu.iq.rate 0.340180 # Inst issue rate
372 system.cpu.iq.fu_busy_cnt 150 # FU busy when requested
373 system.cpu.iq.fu_busy_rate 0.018224 # FU busy rate (busy events/executed inst)
374 system.cpu.iq.int_inst_queue_reads 30186 # Number of integer instruction queue reads
375 system.cpu.iq.int_inst_queue_writes 12584 # Number of integer instruction queue writes
376 system.cpu.iq.int_inst_queue_wakeup_accesses 7378 # Number of integer instruction queue wakeup accesses
377 system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
378 system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
379 system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
380 system.cpu.iq.int_alu_accesses 8379 # Number of integer alu accesses
381 system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
382 system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
383 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
384 system.cpu.iew.lsq.thread0.squashedLoads 1293 # Number of loads squashed
385 system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
386 system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
387 system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed
388 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
389 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
390 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
391 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
392 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
393 system.cpu.iew.iewSquashCycles 844 # Number of cycles IEW is squashing
394 system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking
395 system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
396 system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ
397 system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch
398 system.cpu.iew.iewDispLoadInsts 2456 # Number of dispatched load instructions
399 system.cpu.iew.iewDispStoreInsts 1189 # Number of dispatched store instructions
400 system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions
401 system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
402 system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
403 system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
404 system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
405 system.cpu.iew.predictedNotTakenIncorrect 364 # Number of branches that were predicted not taken incorrectly
406 system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute
407 system.cpu.iew.iewExecutedInsts 7823 # Number of executed instructions
408 system.cpu.iew.iewExecLoadInsts 2103 # Number of load instructions executed
409 system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute
410 system.cpu.iew.exec_swp 0 # number of swp insts executed
411 system.cpu.iew.exec_nop 1455 # number of nop insts executed
412 system.cpu.iew.exec_refs 3177 # number of memory reference insts executed
413 system.cpu.iew.exec_branches 1335 # Number of branches executed
414 system.cpu.iew.exec_stores 1074 # Number of stores executed
415 system.cpu.iew.exec_rate 0.323318 # Inst execution rate
416 system.cpu.iew.wb_sent 7479 # cumulative count of insts sent to commit
417 system.cpu.iew.wb_count 7380 # cumulative count of insts written-back
418 system.cpu.iew.wb_producers 2890 # num instructions producing a value
419 system.cpu.iew.wb_consumers 4129 # num instructions consuming a value
420 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
421 system.cpu.iew.wb_rate 0.305009 # insts written-back per cycle
422 system.cpu.iew.wb_fanout 0.699927 # average fanout of values written-back
423 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
424 system.cpu.commit.commitSquashedInsts 4740 # The number of squashed insts skipped by commit
425 system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
426 system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted
427 system.cpu.commit.committed_per_cycle::samples 12679 # Number of insts commited each cycle
428 system.cpu.commit.committed_per_cycle::mean 0.458475 # Number of insts commited each cycle
429 system.cpu.commit.committed_per_cycle::stdev 1.250836 # Number of insts commited each cycle
430 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
431 system.cpu.commit.committed_per_cycle::0 10300 81.24% 81.24% # Number of insts commited each cycle
432 system.cpu.commit.committed_per_cycle::1 973 7.67% 88.91% # Number of insts commited each cycle
433 system.cpu.commit.committed_per_cycle::2 629 4.96% 93.87% # Number of insts commited each cycle
434 system.cpu.commit.committed_per_cycle::3 317 2.50% 96.37% # Number of insts commited each cycle
435 system.cpu.commit.committed_per_cycle::4 148 1.17% 97.54% # Number of insts commited each cycle
436 system.cpu.commit.committed_per_cycle::5 88 0.69% 98.23% # Number of insts commited each cycle
437 system.cpu.commit.committed_per_cycle::6 75 0.59% 98.82% # Number of insts commited each cycle
438 system.cpu.commit.committed_per_cycle::7 43 0.34% 99.16% # Number of insts commited each cycle
439 system.cpu.commit.committed_per_cycle::8 106 0.84% 100.00% # Number of insts commited each cycle
440 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
441 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
442 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
443 system.cpu.commit.committed_per_cycle::total 12679 # Number of insts commited each cycle
444 system.cpu.commit.committedInsts 5813 # Number of instructions committed
445 system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
446 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
447 system.cpu.commit.refs 2088 # Number of memory references committed
448 system.cpu.commit.loads 1163 # Number of loads committed
449 system.cpu.commit.membars 0 # Number of memory barriers committed
450 system.cpu.commit.branches 915 # Number of branches committed
451 system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
452 system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
453 system.cpu.commit.function_calls 87 # Number of function calls committed.
454 system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
455 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
456 system.cpu.rob.rob_reads 23113 # The number of ROB reads
457 system.cpu.rob.rob_writes 21959 # The number of ROB writes
458 system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself
459 system.cpu.idleCycles 10673 # Total number of cycles that the CPU has spent unscheduled due to idling
460 system.cpu.committedInsts 5156 # Number of Instructions Simulated
461 system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
462 system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
463 system.cpu.cpi 4.692785 # CPI: Cycles Per Instruction
464 system.cpu.cpi_total 4.692785 # CPI: Total CPI of All Threads
465 system.cpu.ipc 0.213093 # IPC: Instructions Per Cycle
466 system.cpu.ipc_total 0.213093 # IPC: Total IPC of All Threads
467 system.cpu.int_regfile_reads 10646 # number of integer regfile reads
468 system.cpu.int_regfile_writes 5184 # number of integer regfile writes
469 system.cpu.fp_regfile_reads 3 # number of floating regfile reads
470 system.cpu.fp_regfile_writes 1 # number of floating regfile writes
471 system.cpu.misc_regfile_reads 155 # number of misc regfile reads
472 system.cpu.icache.replacements 17 # number of replacements
473 system.cpu.icache.tagsinuse 162.253661 # Cycle average of tags in use
474 system.cpu.icache.total_refs 1552 # Total number of references to valid blocks.
475 system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks.
476 system.cpu.icache.avg_refs 4.538012 # Average number of references to valid blocks.
477 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
478 system.cpu.icache.occ_blocks::cpu.inst 162.253661 # Average occupied blocks per requestor
479 system.cpu.icache.occ_percent::cpu.inst 0.079225 # Average percentage of cache occupancy
480 system.cpu.icache.occ_percent::total 0.079225 # Average percentage of cache occupancy
481 system.cpu.icache.ReadReq_hits::cpu.inst 1552 # number of ReadReq hits
482 system.cpu.icache.ReadReq_hits::total 1552 # number of ReadReq hits
483 system.cpu.icache.demand_hits::cpu.inst 1552 # number of demand (read+write) hits
484 system.cpu.icache.demand_hits::total 1552 # number of demand (read+write) hits
485 system.cpu.icache.overall_hits::cpu.inst 1552 # number of overall hits
486 system.cpu.icache.overall_hits::total 1552 # number of overall hits
487 system.cpu.icache.ReadReq_misses::cpu.inst 427 # number of ReadReq misses
488 system.cpu.icache.ReadReq_misses::total 427 # number of ReadReq misses
489 system.cpu.icache.demand_misses::cpu.inst 427 # number of demand (read+write) misses
490 system.cpu.icache.demand_misses::total 427 # number of demand (read+write) misses
491 system.cpu.icache.overall_misses::cpu.inst 427 # number of overall misses
492 system.cpu.icache.overall_misses::total 427 # number of overall misses
493 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14343000 # number of ReadReq miss cycles
494 system.cpu.icache.ReadReq_miss_latency::total 14343000 # number of ReadReq miss cycles
495 system.cpu.icache.demand_miss_latency::cpu.inst 14343000 # number of demand (read+write) miss cycles
496 system.cpu.icache.demand_miss_latency::total 14343000 # number of demand (read+write) miss cycles
497 system.cpu.icache.overall_miss_latency::cpu.inst 14343000 # number of overall miss cycles
498 system.cpu.icache.overall_miss_latency::total 14343000 # number of overall miss cycles
499 system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
500 system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
501 system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses
502 system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses
503 system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses
504 system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses
505 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.215766 # miss rate for ReadReq accesses
506 system.cpu.icache.ReadReq_miss_rate::total 0.215766 # miss rate for ReadReq accesses
507 system.cpu.icache.demand_miss_rate::cpu.inst 0.215766 # miss rate for demand accesses
508 system.cpu.icache.demand_miss_rate::total 0.215766 # miss rate for demand accesses
509 system.cpu.icache.overall_miss_rate::cpu.inst 0.215766 # miss rate for overall accesses
510 system.cpu.icache.overall_miss_rate::total 0.215766 # miss rate for overall accesses
511 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33590.163934 # average ReadReq miss latency
512 system.cpu.icache.ReadReq_avg_miss_latency::total 33590.163934 # average ReadReq miss latency
513 system.cpu.icache.demand_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency
514 system.cpu.icache.demand_avg_miss_latency::total 33590.163934 # average overall miss latency
515 system.cpu.icache.overall_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency
516 system.cpu.icache.overall_avg_miss_latency::total 33590.163934 # average overall miss latency
517 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
518 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
519 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
520 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
521 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
522 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
523 system.cpu.icache.fast_writes 0 # number of fast writes performed
524 system.cpu.icache.cache_copies 0 # number of cache copies performed
525 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits
526 system.cpu.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
527 system.cpu.icache.demand_mshr_hits::cpu.inst 85 # number of demand (read+write) MSHR hits
528 system.cpu.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits
529 system.cpu.icache.overall_mshr_hits::cpu.inst 85 # number of overall MSHR hits
530 system.cpu.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
531 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses
532 system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
533 system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses
534 system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses
535 system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses
536 system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses
537 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11802500 # number of ReadReq MSHR miss cycles
538 system.cpu.icache.ReadReq_mshr_miss_latency::total 11802500 # number of ReadReq MSHR miss cycles
539 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11802500 # number of demand (read+write) MSHR miss cycles
540 system.cpu.icache.demand_mshr_miss_latency::total 11802500 # number of demand (read+write) MSHR miss cycles
541 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11802500 # number of overall MSHR miss cycles
542 system.cpu.icache.overall_mshr_miss_latency::total 11802500 # number of overall MSHR miss cycles
543 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for ReadReq accesses
544 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172815 # mshr miss rate for ReadReq accesses
545 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for demand accesses
546 system.cpu.icache.demand_mshr_miss_rate::total 0.172815 # mshr miss rate for demand accesses
547 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for overall accesses
548 system.cpu.icache.overall_mshr_miss_rate::total 0.172815 # mshr miss rate for overall accesses
549 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34510.233918 # average ReadReq mshr miss latency
550 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34510.233918 # average ReadReq mshr miss latency
551 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency
552 system.cpu.icache.demand_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency
553 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency
554 system.cpu.icache.overall_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency
555 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
556 system.cpu.dcache.replacements 0 # number of replacements
557 system.cpu.dcache.tagsinuse 91.817694 # Cycle average of tags in use
558 system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks.
559 system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
560 system.cpu.dcache.avg_refs 17.340426 # Average number of references to valid blocks.
561 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
562 system.cpu.dcache.occ_blocks::cpu.data 91.817694 # Average occupied blocks per requestor
563 system.cpu.dcache.occ_percent::cpu.data 0.022416 # Average percentage of cache occupancy
564 system.cpu.dcache.occ_percent::total 0.022416 # Average percentage of cache occupancy
565 system.cpu.dcache.ReadReq_hits::cpu.data 1868 # number of ReadReq hits
566 system.cpu.dcache.ReadReq_hits::total 1868 # number of ReadReq hits
567 system.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits
568 system.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits
569 system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits
570 system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits
571 system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits
572 system.cpu.dcache.overall_hits::total 2445 # number of overall hits
573 system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses
574 system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses
575 system.cpu.dcache.WriteReq_misses::cpu.data 348 # number of WriteReq misses
576 system.cpu.dcache.WriteReq_misses::total 348 # number of WriteReq misses
577 system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses
578 system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses
579 system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses
580 system.cpu.dcache.overall_misses::total 497 # number of overall misses
581 system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916000 # number of ReadReq miss cycles
582 system.cpu.dcache.ReadReq_miss_latency::total 5916000 # number of ReadReq miss cycles
583 system.cpu.dcache.WriteReq_miss_latency::cpu.data 9509000 # number of WriteReq miss cycles
584 system.cpu.dcache.WriteReq_miss_latency::total 9509000 # number of WriteReq miss cycles
585 system.cpu.dcache.demand_miss_latency::cpu.data 15425000 # number of demand (read+write) miss cycles
586 system.cpu.dcache.demand_miss_latency::total 15425000 # number of demand (read+write) miss cycles
587 system.cpu.dcache.overall_miss_latency::cpu.data 15425000 # number of overall miss cycles
588 system.cpu.dcache.overall_miss_latency::total 15425000 # number of overall miss cycles
589 system.cpu.dcache.ReadReq_accesses::cpu.data 2017 # number of ReadReq accesses(hits+misses)
590 system.cpu.dcache.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses)
591 system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
592 system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
593 system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses
594 system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses
595 system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses
596 system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses
597 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073872 # miss rate for ReadReq accesses
598 system.cpu.dcache.ReadReq_miss_rate::total 0.073872 # miss rate for ReadReq accesses
599 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses
600 system.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses
601 system.cpu.dcache.demand_miss_rate::cpu.data 0.168933 # miss rate for demand accesses
602 system.cpu.dcache.demand_miss_rate::total 0.168933 # miss rate for demand accesses
603 system.cpu.dcache.overall_miss_rate::cpu.data 0.168933 # miss rate for overall accesses
604 system.cpu.dcache.overall_miss_rate::total 0.168933 # miss rate for overall accesses
605 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39704.697987 # average ReadReq miss latency
606 system.cpu.dcache.ReadReq_avg_miss_latency::total 39704.697987 # average ReadReq miss latency
607 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27324.712644 # average WriteReq miss latency
608 system.cpu.dcache.WriteReq_avg_miss_latency::total 27324.712644 # average WriteReq miss latency
609 system.cpu.dcache.demand_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency
610 system.cpu.dcache.demand_avg_miss_latency::total 31036.217304 # average overall miss latency
611 system.cpu.dcache.overall_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency
612 system.cpu.dcache.overall_avg_miss_latency::total 31036.217304 # average overall miss latency
613 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
614 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
615 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
616 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
617 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
618 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
619 system.cpu.dcache.fast_writes 0 # number of fast writes performed
620 system.cpu.dcache.cache_copies 0 # number of cache copies performed
621 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
622 system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
623 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits
624 system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits
625 system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits
626 system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits
627 system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits
628 system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits
629 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
630 system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
631 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
632 system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
633 system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
634 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
635 system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
636 system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
637 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles
638 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles
639 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1859000 # number of WriteReq MSHR miss cycles
640 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1859000 # number of WriteReq MSHR miss cycles
641 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles
642 system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles
643 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles
644 system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles
645 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044621 # mshr miss rate for ReadReq accesses
646 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044621 # mshr miss rate for ReadReq accesses
647 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
648 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
649 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses
650 system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses
651 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses
652 system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses
653 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency
654 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency
655 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36450.980392 # average WriteReq mshr miss latency
656 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36450.980392 # average WriteReq mshr miss latency
657 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency
658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency
659 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency
660 system.cpu.dcache.overall_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency
661 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
662 system.cpu.l2cache.replacements 0 # number of replacements
663 system.cpu.l2cache.tagsinuse 222.617700 # Cycle average of tags in use
664 system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
665 system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks.
666 system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks.
667 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
668 system.cpu.l2cache.occ_blocks::cpu.inst 164.369429 # Average occupied blocks per requestor
669 system.cpu.l2cache.occ_blocks::cpu.data 58.248271 # Average occupied blocks per requestor
670 system.cpu.l2cache.occ_percent::cpu.inst 0.005016 # Average percentage of cache occupancy
671 system.cpu.l2cache.occ_percent::cpu.data 0.001778 # Average percentage of cache occupancy
672 system.cpu.l2cache.occ_percent::total 0.006794 # Average percentage of cache occupancy
673 system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
674 system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
675 system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
676 system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
677 system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
678 system.cpu.l2cache.overall_hits::total 3 # number of overall hits
679 system.cpu.l2cache.ReadReq_misses::cpu.inst 339 # number of ReadReq misses
680 system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses
681 system.cpu.l2cache.ReadReq_misses::total 429 # number of ReadReq misses
682 system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
683 system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
684 system.cpu.l2cache.demand_misses::cpu.inst 339 # number of demand (read+write) misses
685 system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
686 system.cpu.l2cache.demand_misses::total 480 # number of demand (read+write) misses
687 system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses
688 system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
689 system.cpu.l2cache.overall_misses::total 480 # number of overall misses
690 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11455500 # number of ReadReq miss cycles
691 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3737500 # number of ReadReq miss cycles
692 system.cpu.l2cache.ReadReq_miss_latency::total 15193000 # number of ReadReq miss cycles
693 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1807500 # number of ReadExReq miss cycles
694 system.cpu.l2cache.ReadExReq_miss_latency::total 1807500 # number of ReadExReq miss cycles
695 system.cpu.l2cache.demand_miss_latency::cpu.inst 11455500 # number of demand (read+write) miss cycles
696 system.cpu.l2cache.demand_miss_latency::cpu.data 5545000 # number of demand (read+write) miss cycles
697 system.cpu.l2cache.demand_miss_latency::total 17000500 # number of demand (read+write) miss cycles
698 system.cpu.l2cache.overall_miss_latency::cpu.inst 11455500 # number of overall miss cycles
699 system.cpu.l2cache.overall_miss_latency::cpu.data 5545000 # number of overall miss cycles
700 system.cpu.l2cache.overall_miss_latency::total 17000500 # number of overall miss cycles
701 system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses)
702 system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
703 system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses)
704 system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
705 system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
706 system.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses
707 system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
708 system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses
709 system.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses
710 system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
711 system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses
712 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses
713 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
714 system.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses
715 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
716 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
717 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses
718 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
719 system.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses
720 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses
721 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
722 system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses
723 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33792.035398 # average ReadReq miss latency
724 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41527.777778 # average ReadReq miss latency
725 system.cpu.l2cache.ReadReq_avg_miss_latency::total 35414.918415 # average ReadReq miss latency
726 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35441.176471 # average ReadExReq miss latency
727 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35441.176471 # average ReadExReq miss latency
728 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency
729 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency
730 system.cpu.l2cache.demand_avg_miss_latency::total 35417.708333 # average overall miss latency
731 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency
732 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency
733 system.cpu.l2cache.overall_avg_miss_latency::total 35417.708333 # average overall miss latency
734 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
735 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
736 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
737 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
738 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
739 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
740 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
741 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
742 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses
743 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
744 system.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses
745 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
746 system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
747 system.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses
748 system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
749 system.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses
750 system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses
751 system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
752 system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses
753 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10252004 # number of ReadReq MSHR miss cycles
754 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3439074 # number of ReadReq MSHR miss cycles
755 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13691078 # number of ReadReq MSHR miss cycles
756 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1635054 # number of ReadExReq MSHR miss cycles
757 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1635054 # number of ReadExReq MSHR miss cycles
758 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10252004 # number of demand (read+write) MSHR miss cycles
759 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5074128 # number of demand (read+write) MSHR miss cycles
760 system.cpu.l2cache.demand_mshr_miss_latency::total 15326132 # number of demand (read+write) MSHR miss cycles
761 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10252004 # number of overall MSHR miss cycles
762 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5074128 # number of overall MSHR miss cycles
763 system.cpu.l2cache.overall_mshr_miss_latency::total 15326132 # number of overall MSHR miss cycles
764 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses
765 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
766 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses
767 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
768 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
769 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses
770 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
771 system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses
772 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses
773 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
774 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses
775 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30241.899705 # average ReadReq mshr miss latency
776 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38211.933333 # average ReadReq mshr miss latency
777 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31913.934732 # average ReadReq mshr miss latency
778 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32059.882353 # average ReadExReq mshr miss latency
779 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32059.882353 # average ReadExReq mshr miss latency
780 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency
781 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency
782 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency
783 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency
784 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency
785 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency
786 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
788 ---------- End Simulation Statistics ----------
projects / gem5.git / blob