tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 exit_on_work_items=false
  19 init_param=0
  20 kernel=
  21 kernel_addr_check=true
  22 load_addr_mask=1099511627775
  23 load_offset=0
  24 mem_mode=timing
  25 mem_ranges=
  26 memories=system.physmem
  27 mmap_using_noreserve=false
  28 multi_thread=false
  29 num_work_ids=16
  30 readfile=
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[0]
  40
  41 [system.clk_domain]
  42 type=SrcClockDomain
  43 clock=1000
  44 domain_id=-1
  45 eventq_index=0
  46 init_perf_level=0
  47 voltage_domain=system.voltage_domain
  48
  49 [system.cpu]
  50 type=TimingSimpleCPU
  51 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  52 branchPred=Null
  53 checker=Null
  54 clk_domain=system.cpu_clk_domain
  55 cpu_id=0
  56 do_checkpoint_insts=true
  57 do_quiesce=true
  58 do_statistics_insts=true
  59 dtb=system.cpu.dtb
  60 eventq_index=0
  61 function_trace=false
  62 function_trace_start=0
  63 interrupts=system.cpu.interrupts
  64 isa=system.cpu.isa
  65 itb=system.cpu.itb
  66 max_insts_all_threads=0
  67 max_insts_any_thread=0
  68 max_loads_all_threads=0
  69 max_loads_any_thread=0
  70 numThreads=1
  71 profile=0
  72 progress_interval=0
  73 simpoint_start_insts=
  74 socket_id=0
  75 switched_out=false
  76 system=system
  77 tracer=system.cpu.tracer
  78 workload=system.cpu.workload
  79 dcache_port=system.cpu.dcache.cpu_side
  80 icache_port=system.cpu.icache.cpu_side
  81
  82 [system.cpu.dcache]
  83 type=Cache
  84 children=tags
  85 addr_ranges=0:18446744073709551615
  86 assoc=2
  87 clk_domain=system.cpu_clk_domain
  88 clusivity=mostly_incl
  89 demand_mshr_reserve=1
  90 eventq_index=0
  91 forward_snoops=true
  92 hit_latency=2
  93 is_read_only=false
  94 max_miss_count=0
  95 mshrs=4
  96 prefetch_on_access=false
  97 prefetcher=Null
  98 response_latency=2
  99 sequential_access=false
 100 size=262144
 101 system=system
 102 tags=system.cpu.dcache.tags
 103 tgts_per_mshr=20
 104 write_buffers=8
 105 writeback_clean=false
 106 cpu_side=system.cpu.dcache_port
 107 mem_side=system.cpu.toL2Bus.slave[1]
 108
 109 [system.cpu.dcache.tags]
 110 type=LRU
 111 assoc=2
 112 block_size=64
 113 clk_domain=system.cpu_clk_domain
 114 eventq_index=0
 115 hit_latency=2
 116 sequential_access=false
 117 size=262144
 118
 119 [system.cpu.dtb]
 120 type=MipsTLB
 121 eventq_index=0
 122 size=64
 123
 124 [system.cpu.icache]
 125 type=Cache
 126 children=tags
 127 addr_ranges=0:18446744073709551615
 128 assoc=2
 129 clk_domain=system.cpu_clk_domain
 130 clusivity=mostly_incl
 131 demand_mshr_reserve=1
 132 eventq_index=0
 133 forward_snoops=true
 134 hit_latency=2
 135 is_read_only=true
 136 max_miss_count=0
 137 mshrs=4
 138 prefetch_on_access=false
 139 prefetcher=Null
 140 response_latency=2
 141 sequential_access=false
 142 size=131072
 143 system=system
 144 tags=system.cpu.icache.tags
 145 tgts_per_mshr=20
 146 write_buffers=8
 147 writeback_clean=true
 148 cpu_side=system.cpu.icache_port
 149 mem_side=system.cpu.toL2Bus.slave[0]
 150
 151 [system.cpu.icache.tags]
 152 type=LRU
 153 assoc=2
 154 block_size=64
 155 clk_domain=system.cpu_clk_domain
 156 eventq_index=0
 157 hit_latency=2
 158 sequential_access=false
 159 size=131072
 160
 161 [system.cpu.interrupts]
 162 type=MipsInterrupts
 163 eventq_index=0
 164
 165 [system.cpu.isa]
 166 type=MipsISA
 167 eventq_index=0
 168 num_threads=1
 169 num_vpes=1
 170 system=system
 171
 172 [system.cpu.itb]
 173 type=MipsTLB
 174 eventq_index=0
 175 size=64
 176
 177 [system.cpu.l2cache]
 178 type=Cache
 179 children=tags
 180 addr_ranges=0:18446744073709551615
 181 assoc=8
 182 clk_domain=system.cpu_clk_domain
 183 clusivity=mostly_incl
 184 demand_mshr_reserve=1
 185 eventq_index=0
 186 forward_snoops=true
 187 hit_latency=20
 188 is_read_only=false
 189 max_miss_count=0
 190 mshrs=20
 191 prefetch_on_access=false
 192 prefetcher=Null
 193 response_latency=20
 194 sequential_access=false
 195 size=2097152
 196 system=system
 197 tags=system.cpu.l2cache.tags
 198 tgts_per_mshr=12
 199 write_buffers=8
 200 writeback_clean=false
 201 cpu_side=system.cpu.toL2Bus.master[0]
 202 mem_side=system.membus.slave[1]
 203
 204 [system.cpu.l2cache.tags]
 205 type=LRU
 206 assoc=8
 207 block_size=64
 208 clk_domain=system.cpu_clk_domain
 209 eventq_index=0
 210 hit_latency=20
 211 sequential_access=false
 212 size=2097152
 213
 214 [system.cpu.toL2Bus]
 215 type=CoherentXBar
 216 children=snoop_filter
 217 clk_domain=system.cpu_clk_domain
 218 eventq_index=0
 219 forward_latency=0
 220 frontend_latency=1
 221 response_latency=1
 222 snoop_filter=system.cpu.toL2Bus.snoop_filter
 223 snoop_response_latency=1
 224 system=system
 225 use_default_range=false
 226 width=32
 227 master=system.cpu.l2cache.cpu_side
 228 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 229
 230 [system.cpu.toL2Bus.snoop_filter]
 231 type=SnoopFilter
 232 eventq_index=0
 233 lookup_latency=0
 234 max_capacity=8388608
 235 system=system
 236
 237 [system.cpu.tracer]
 238 type=ExeTracer
 239 eventq_index=0
 240
 241 [system.cpu.workload]
 242 type=LiveProcess
 243 cmd=hello
 244 cwd=
 245 drivers=
 246 egid=100
 247 env=
 248 errout=cerr
 249 euid=100
 250 eventq_index=0
 251 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 252 gid=100
 253 input=cin
 254 kvmInSE=false
 255 max_stack_size=67108864
 256 output=cout
 257 pid=100
 258 ppid=99
 259 simpoint=0
 260 system=system
 261 uid=100
 262 useArchPT=false
 263
 264 [system.cpu_clk_domain]
 265 type=SrcClockDomain
 266 clock=500
 267 domain_id=-1
 268 eventq_index=0
 269 init_perf_level=0
 270 voltage_domain=system.voltage_domain
 271
 272 [system.dvfs_handler]
 273 type=DVFSHandler
 274 domains=
 275 enable=false
 276 eventq_index=0
 277 sys_clk_domain=system.clk_domain
 278 transition_latency=100000000
 279
 280 [system.membus]
 281 type=CoherentXBar
 282 clk_domain=system.clk_domain
 283 eventq_index=0
 284 forward_latency=4
 285 frontend_latency=3
 286 response_latency=2
 287 snoop_filter=Null
 288 snoop_response_latency=4
 289 system=system
 290 use_default_range=false
 291 width=16
 292 master=system.physmem.port
 293 slave=system.system_port system.cpu.l2cache.mem_side
 294
 295 [system.physmem]
 296 type=SimpleMemory
 297 bandwidth=73.000000
 298 clk_domain=system.clk_domain
 299 conf_table_reported=true
 300 eventq_index=0
 301 in_addr_map=true
 302 latency=30000
 303 latency_var=0
 304 null=false
 305 range=0:134217727
 306 port=system.membus.master[0]
 307
 308 [system.voltage_domain]
 309 type=VoltageDomain
 310 eventq_index=0
 311 voltage=1.000000
 312