8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 kernel_addr_check=true
21 load_addr_mask=1099511627775
25 memories=system.physmem
29 work_begin_ckpt_count=0
30 work_begin_cpu_id_exit=-1
31 work_begin_exit_count=0
32 work_cpus_ckpt_count=0
36 system_port=system.membus.slave[0]
44 voltage_domain=system.voltage_domain
48 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
51 clk_domain=system.cpu_clk_domain
53 do_checkpoint_insts=true
55 do_statistics_insts=true
59 function_trace_start=0
60 interrupts=system.cpu.interrupts
63 max_insts_all_threads=0
64 max_insts_any_thread=0
65 max_loads_all_threads=0
66 max_loads_any_thread=0
74 tracer=system.cpu.tracer
75 workload=system.cpu.workload
76 dcache_port=system.cpu.dcache.cpu_side
77 icache_port=system.cpu.icache.cpu_side
82 addr_ranges=0:18446744073709551615
84 clk_domain=system.cpu_clk_domain
91 prefetch_on_access=false
94 sequential_access=false
97 tags=system.cpu.dcache.tags
101 cpu_side=system.cpu.dcache_port
102 mem_side=system.cpu.toL2Bus.slave[1]
104 [system.cpu.dcache.tags]
108 clk_domain=system.cpu_clk_domain
111 sequential_access=false
122 addr_ranges=0:18446744073709551615
124 clk_domain=system.cpu_clk_domain
131 prefetch_on_access=false
134 sequential_access=false
137 tags=system.cpu.icache.tags
141 cpu_side=system.cpu.icache_port
142 mem_side=system.cpu.toL2Bus.slave[0]
144 [system.cpu.icache.tags]
148 clk_domain=system.cpu_clk_domain
151 sequential_access=false
154 [system.cpu.interrupts]
173 addr_ranges=0:18446744073709551615
175 clk_domain=system.cpu_clk_domain
182 prefetch_on_access=false
185 sequential_access=false
188 tags=system.cpu.l2cache.tags
192 cpu_side=system.cpu.toL2Bus.master[0]
193 mem_side=system.membus.slave[1]
195 [system.cpu.l2cache.tags]
199 clk_domain=system.cpu_clk_domain
202 sequential_access=false
207 clk_domain=system.cpu_clk_domain
212 use_default_range=false
214 master=system.cpu.l2cache.cpu_side
215 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
221 [system.cpu.workload]
230 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
233 max_stack_size=67108864
242 [system.cpu_clk_domain]
248 voltage_domain=system.voltage_domain
250 [system.dvfs_handler]
255 sys_clk_domain=system.clk_domain
256 transition_latency=100000000
260 clk_domain=system.clk_domain
265 use_default_range=false
267 master=system.physmem.port
268 slave=system.system_port system.cpu.l2cache.mem_side
273 clk_domain=system.clk_domain
274 conf_table_reported=true
281 port=system.membus.master[0]
283 [system.voltage_domain]