2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000034 # Number of seconds simulated
4 sim_ticks 34362500 # Number of ticks simulated
5 final_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 587904 # Simulator instruction rate (inst/s)
8 host_op_rate 587165 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 3572983060 # Simulator tick rate (ticks/s)
10 host_mem_usage 249352 # Number of bytes of host memory used
11 host_seconds 0.01 # Real time elapsed on the host
12 sim_insts 5641 # Number of instructions simulated
13 sim_ops 5641 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 27520 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 430 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 545711168 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 255161877 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 800873045 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 545711168 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 545711168 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 545711168 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 255161877 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 800873045 # Total bandwidth to/from this memory (bytes/s)
33 system.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
34 system.cpu_clk_domain.clock 500 # Clock period in ticks
35 system.cpu.dtb.read_hits 0 # DTB read hits
36 system.cpu.dtb.read_misses 0 # DTB read misses
37 system.cpu.dtb.read_accesses 0 # DTB read accesses
38 system.cpu.dtb.write_hits 0 # DTB write hits
39 system.cpu.dtb.write_misses 0 # DTB write misses
40 system.cpu.dtb.write_accesses 0 # DTB write accesses
41 system.cpu.dtb.hits 0 # DTB hits
42 system.cpu.dtb.misses 0 # DTB misses
43 system.cpu.dtb.accesses 0 # DTB accesses
44 system.cpu.itb.read_hits 0 # DTB read hits
45 system.cpu.itb.read_misses 0 # DTB read misses
46 system.cpu.itb.read_accesses 0 # DTB read accesses
47 system.cpu.itb.write_hits 0 # DTB write hits
48 system.cpu.itb.write_misses 0 # DTB write misses
49 system.cpu.itb.write_accesses 0 # DTB write accesses
50 system.cpu.itb.hits 0 # DTB hits
51 system.cpu.itb.misses 0 # DTB misses
52 system.cpu.itb.accesses 0 # DTB accesses
53 system.cpu.workload.numSyscalls 7 # Number of system calls
54 system.cpu.pwrStateResidencyTicks::ON 34362500 # Cumulative time (in ticks) in various power states
55 system.cpu.numCycles 68725 # number of cpu cycles simulated
56 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
57 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
58 system.cpu.committedInsts 5641 # Number of instructions committed
59 system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
60 system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
61 system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
62 system.cpu.num_func_calls 191 # number of times a function call or return occured
63 system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
64 system.cpu.num_int_insts 4957 # number of integer instructions
65 system.cpu.num_fp_insts 2 # number of float instructions
66 system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
67 system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
68 system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
69 system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
70 system.cpu.num_mem_refs 2037 # number of memory refs
71 system.cpu.num_load_insts 1135 # Number of load instructions
72 system.cpu.num_store_insts 902 # Number of store instructions
73 system.cpu.num_idle_cycles 0 # Number of idle cycles
74 system.cpu.num_busy_cycles 68725 # Number of busy cycles
75 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
76 system.cpu.idle_fraction 0 # Percentage of idle cycles
77 system.cpu.Branches 886 # Number of branches fetched
78 system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
79 system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
80 system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
81 system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
82 system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
83 system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
84 system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
85 system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
86 system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction
87 system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
88 system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction
89 system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
90 system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
91 system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
92 system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
93 system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
94 system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
95 system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
96 system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
97 system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
98 system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
99 system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
100 system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
101 system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
102 system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
103 system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
104 system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
105 system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
106 system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
107 system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
108 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
109 system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
110 system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
111 system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
112 system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
113 system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
114 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
115 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
116 system.cpu.op_class::total 5642 # Class of executed instruction
117 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
118 system.cpu.dcache.tags.replacements 0 # number of replacements
119 system.cpu.dcache.tags.tagsinuse 86.019878 # Cycle average of tags in use
120 system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
121 system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
122 system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
123 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
124 system.cpu.dcache.tags.occ_blocks::cpu.data 86.019878 # Average occupied blocks per requestor
125 system.cpu.dcache.tags.occ_percent::cpu.data 0.021001 # Average percentage of cache occupancy
126 system.cpu.dcache.tags.occ_percent::total 0.021001 # Average percentage of cache occupancy
127 system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
128 system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
129 system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
130 system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
131 system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
132 system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
133 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
134 system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
135 system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
136 system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
137 system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
138 system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
139 system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
140 system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
141 system.cpu.dcache.overall_hits::total 1899 # number of overall hits
142 system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
143 system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
144 system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
145 system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
146 system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
147 system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
148 system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
149 system.cpu.dcache.overall_misses::total 137 # number of overall misses
150 system.cpu.dcache.ReadReq_miss_latency::cpu.data 5481000 # number of ReadReq miss cycles
151 system.cpu.dcache.ReadReq_miss_latency::total 5481000 # number of ReadReq miss cycles
152 system.cpu.dcache.WriteReq_miss_latency::cpu.data 3150000 # number of WriteReq miss cycles
153 system.cpu.dcache.WriteReq_miss_latency::total 3150000 # number of WriteReq miss cycles
154 system.cpu.dcache.demand_miss_latency::cpu.data 8631000 # number of demand (read+write) miss cycles
155 system.cpu.dcache.demand_miss_latency::total 8631000 # number of demand (read+write) miss cycles
156 system.cpu.dcache.overall_miss_latency::cpu.data 8631000 # number of overall miss cycles
157 system.cpu.dcache.overall_miss_latency::total 8631000 # number of overall miss cycles
158 system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
159 system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
160 system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
161 system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
162 system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
163 system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
164 system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
165 system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
166 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
167 system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
168 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
169 system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
170 system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
171 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
172 system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
173 system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
174 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
175 system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
176 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
177 system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
178 system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
179 system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
180 system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
181 system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
182 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
183 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
184 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
185 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
186 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
187 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
188 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
189 system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
190 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
191 system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
192 system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
193 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
194 system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
195 system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
196 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5394000 # number of ReadReq MSHR miss cycles
197 system.cpu.dcache.ReadReq_mshr_miss_latency::total 5394000 # number of ReadReq MSHR miss cycles
198 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3100000 # number of WriteReq MSHR miss cycles
199 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3100000 # number of WriteReq MSHR miss cycles
200 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8494000 # number of demand (read+write) MSHR miss cycles
201 system.cpu.dcache.demand_mshr_miss_latency::total 8494000 # number of demand (read+write) MSHR miss cycles
202 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8494000 # number of overall MSHR miss cycles
203 system.cpu.dcache.overall_mshr_miss_latency::total 8494000 # number of overall MSHR miss cycles
204 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
205 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
206 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
207 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
208 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
209 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
210 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
211 system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
212 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
213 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
214 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
215 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
216 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
217 system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
218 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
219 system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
220 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
221 system.cpu.icache.tags.replacements 13 # number of replacements
222 system.cpu.icache.tags.tagsinuse 128.944610 # Cycle average of tags in use
223 system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks.
224 system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
225 system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks.
226 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
227 system.cpu.icache.tags.occ_blocks::cpu.inst 128.944610 # Average occupied blocks per requestor
228 system.cpu.icache.tags.occ_percent::cpu.inst 0.062961 # Average percentage of cache occupancy
229 system.cpu.icache.tags.occ_percent::total 0.062961 # Average percentage of cache occupancy
230 system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
231 system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
232 system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
233 system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
234 system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses
235 system.cpu.icache.tags.data_accesses 11581 # Number of data accesses
236 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
237 system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits
238 system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits
239 system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits
240 system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits
241 system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits
242 system.cpu.icache.overall_hits::total 5348 # number of overall hits
243 system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses
244 system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses
245 system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses
246 system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses
247 system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses
248 system.cpu.icache.overall_misses::total 295 # number of overall misses
249 system.cpu.icache.ReadReq_miss_latency::cpu.inst 18485500 # number of ReadReq miss cycles
250 system.cpu.icache.ReadReq_miss_latency::total 18485500 # number of ReadReq miss cycles
251 system.cpu.icache.demand_miss_latency::cpu.inst 18485500 # number of demand (read+write) miss cycles
252 system.cpu.icache.demand_miss_latency::total 18485500 # number of demand (read+write) miss cycles
253 system.cpu.icache.overall_miss_latency::cpu.inst 18485500 # number of overall miss cycles
254 system.cpu.icache.overall_miss_latency::total 18485500 # number of overall miss cycles
255 system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
256 system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
257 system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
258 system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
259 system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
260 system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
261 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses
262 system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses
263 system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses
264 system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses
265 system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses
266 system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses
267 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62662.711864 # average ReadReq miss latency
268 system.cpu.icache.ReadReq_avg_miss_latency::total 62662.711864 # average ReadReq miss latency
269 system.cpu.icache.demand_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency
270 system.cpu.icache.demand_avg_miss_latency::total 62662.711864 # average overall miss latency
271 system.cpu.icache.overall_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency
272 system.cpu.icache.overall_avg_miss_latency::total 62662.711864 # average overall miss latency
273 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
274 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
275 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
276 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
277 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
278 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
279 system.cpu.icache.writebacks::writebacks 13 # number of writebacks
280 system.cpu.icache.writebacks::total 13 # number of writebacks
281 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
282 system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
283 system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
284 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
285 system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
286 system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
287 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18190500 # number of ReadReq MSHR miss cycles
288 system.cpu.icache.ReadReq_mshr_miss_latency::total 18190500 # number of ReadReq MSHR miss cycles
289 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18190500 # number of demand (read+write) MSHR miss cycles
290 system.cpu.icache.demand_mshr_miss_latency::total 18190500 # number of demand (read+write) MSHR miss cycles
291 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18190500 # number of overall MSHR miss cycles
292 system.cpu.icache.overall_mshr_miss_latency::total 18190500 # number of overall MSHR miss cycles
293 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses
294 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses
295 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses
296 system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses
297 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses
298 system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses
299 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61662.711864 # average ReadReq mshr miss latency
300 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61662.711864 # average ReadReq mshr miss latency
301 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency
302 system.cpu.icache.demand_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency
303 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency
304 system.cpu.icache.overall_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency
305 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
306 system.cpu.l2cache.tags.replacements 0 # number of replacements
307 system.cpu.l2cache.tags.tagsinuse 216.139082 # Cycle average of tags in use
308 system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
309 system.cpu.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
310 system.cpu.l2cache.tags.avg_refs 0.034884 # Average number of references to valid blocks.
311 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
312 system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.077342 # Average occupied blocks per requestor
313 system.cpu.l2cache.tags.occ_blocks::cpu.data 86.061740 # Average occupied blocks per requestor
314 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy
315 system.cpu.l2cache.tags.occ_percent::cpu.data 0.002626 # Average percentage of cache occupancy
316 system.cpu.l2cache.tags.occ_percent::total 0.006596 # Average percentage of cache occupancy
317 system.cpu.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
318 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
319 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
320 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013123 # Percentage of cache occupancy per task id
321 system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses
322 system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses
323 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
324 system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits
325 system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits
326 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
327 system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
328 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
329 system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
330 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
331 system.cpu.l2cache.overall_hits::total 2 # number of overall hits
332 system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
333 system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
334 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 293 # number of ReadCleanReq misses
335 system.cpu.l2cache.ReadCleanReq_misses::total 293 # number of ReadCleanReq misses
336 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses
337 system.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses
338 system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses
339 system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses
340 system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses
341 system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses
342 system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses
343 system.cpu.l2cache.overall_misses::total 430 # number of overall misses
344 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3025000 # number of ReadExReq miss cycles
345 system.cpu.l2cache.ReadExReq_miss_latency::total 3025000 # number of ReadExReq miss cycles
346 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17727000 # number of ReadCleanReq miss cycles
347 system.cpu.l2cache.ReadCleanReq_miss_latency::total 17727000 # number of ReadCleanReq miss cycles
348 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5263500 # number of ReadSharedReq miss cycles
349 system.cpu.l2cache.ReadSharedReq_miss_latency::total 5263500 # number of ReadSharedReq miss cycles
350 system.cpu.l2cache.demand_miss_latency::cpu.inst 17727000 # number of demand (read+write) miss cycles
351 system.cpu.l2cache.demand_miss_latency::cpu.data 8288500 # number of demand (read+write) miss cycles
352 system.cpu.l2cache.demand_miss_latency::total 26015500 # number of demand (read+write) miss cycles
353 system.cpu.l2cache.overall_miss_latency::cpu.inst 17727000 # number of overall miss cycles
354 system.cpu.l2cache.overall_miss_latency::cpu.data 8288500 # number of overall miss cycles
355 system.cpu.l2cache.overall_miss_latency::total 26015500 # number of overall miss cycles
356 system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses)
357 system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses)
358 system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
359 system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
360 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses)
361 system.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses)
362 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses)
363 system.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses)
364 system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses
365 system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses
366 system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses
367 system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses
368 system.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses
369 system.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses
370 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
371 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
372 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadCleanReq accesses
373 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993220 # miss rate for ReadCleanReq accesses
374 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
375 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
376 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses
377 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
378 system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses
379 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses
380 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
381 system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses
382 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
383 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
384 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.706485 # average ReadCleanReq miss latency
385 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.706485 # average ReadCleanReq miss latency
386 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
387 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
388 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency
389 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
390 system.cpu.l2cache.demand_avg_miss_latency::total 60501.162791 # average overall miss latency
391 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency
392 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
393 system.cpu.l2cache.overall_avg_miss_latency::total 60501.162791 # average overall miss latency
394 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
395 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
396 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
397 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
398 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
399 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
400 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
401 system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
402 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses
403 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses
404 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
405 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses
406 system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
407 system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
408 system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
409 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
410 system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
411 system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
412 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2525000 # number of ReadExReq MSHR miss cycles
413 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2525000 # number of ReadExReq MSHR miss cycles
414 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14797000 # number of ReadCleanReq MSHR miss cycles
415 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14797000 # number of ReadCleanReq MSHR miss cycles
416 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4393500 # number of ReadSharedReq MSHR miss cycles
417 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4393500 # number of ReadSharedReq MSHR miss cycles
418 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14797000 # number of demand (read+write) MSHR miss cycles
419 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6918500 # number of demand (read+write) MSHR miss cycles
420 system.cpu.l2cache.demand_mshr_miss_latency::total 21715500 # number of demand (read+write) MSHR miss cycles
421 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14797000 # number of overall MSHR miss cycles
422 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6918500 # number of overall MSHR miss cycles
423 system.cpu.l2cache.overall_mshr_miss_latency::total 21715500 # number of overall MSHR miss cycles
424 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
425 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
426 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses
427 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses
428 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
429 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
430 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses
431 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
432 system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses
433 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses
434 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
435 system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses
436 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
437 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
438 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.706485 # average ReadCleanReq mshr miss latency
439 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.706485 # average ReadCleanReq mshr miss latency
440 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
441 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
442 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency
443 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
444 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency
445 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency
446 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
447 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency
448 system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
449 system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data.
450 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
451 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
452 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
453 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
454 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
455 system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
456 system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution
457 system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
458 system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
459 system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution
460 system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution
461 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
462 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
463 system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes)
464 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes)
465 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
466 system.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes)
467 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
468 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
469 system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram
470 system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
471 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
472 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
473 system.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram
474 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
475 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
476 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
477 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
478 system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
479 system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram
480 system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks)
481 system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
482 system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks)
483 system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
484 system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks)
485 system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
486 system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
487 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
488 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
489 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
490 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
491 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
492 system.membus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
493 system.membus.trans_dist::ReadResp 380 # Transaction distribution
494 system.membus.trans_dist::ReadExReq 50 # Transaction distribution
495 system.membus.trans_dist::ReadExResp 50 # Transaction distribution
496 system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution
497 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes)
498 system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
499 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes)
500 system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
501 system.membus.snoops 0 # Total snoops (count)
502 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
503 system.membus.snoop_fanout::samples 430 # Request fanout histogram
504 system.membus.snoop_fanout::mean 0 # Request fanout histogram
505 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
506 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
507 system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
508 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
509 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
510 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
511 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
512 system.membus.snoop_fanout::total 430 # Request fanout histogram
513 system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks)
514 system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
515 system.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks)
516 system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
518 ---------- End Simulation Statistics ----------
projects / gem5.git / blob