tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=DerivO3CPU
  48 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  49 LFSTSize=1024
  50 LQEntries=32
  51 LSQCheckLoads=true
  52 LSQDepCheckShift=4
  53 SQEntries=32
  54 SSITSize=1024
  55 UnifiedTLB=true
  56 activity=0
  57 backComSize=5
  58 branchPred=system.cpu.branchPred
  59 cachePorts=200
  60 checker=Null
  61 clk_domain=system.cpu_clk_domain
  62 commitToDecodeDelay=1
  63 commitToFetchDelay=1
  64 commitToIEWDelay=1
  65 commitToRenameDelay=1
  66 commitWidth=8
  67 cpu_id=0
  68 decodeToFetchDelay=1
  69 decodeToRenameDelay=1
  70 decodeWidth=8
  71 dispatchWidth=8
  72 do_checkpoint_insts=true
  73 do_quiesce=true
  74 do_statistics_insts=true
  75 dtb=system.cpu.dtb
  76 eventq_index=0
  77 fetchBufferSize=64
  78 fetchQueueSize=32
  79 fetchToDecodeDelay=1
  80 fetchTrapLatency=1
  81 fetchWidth=8
  82 forwardComSize=5
  83 fuPool=system.cpu.fuPool
  84 function_trace=false
  85 function_trace_start=0
  86 iewToCommitDelay=1
  87 iewToDecodeDelay=1
  88 iewToFetchDelay=1
  89 iewToRenameDelay=1
  90 interrupts=system.cpu.interrupts
  91 isa=system.cpu.isa
  92 issueToExecuteDelay=1
  93 issueWidth=8
  94 itb=system.cpu.itb
  95 max_insts_all_threads=0
  96 max_insts_any_thread=0
  97 max_loads_all_threads=0
  98 max_loads_any_thread=0
  99 needsTSO=false
 100 numIQEntries=64
 101 numPhysCCRegs=0
 102 numPhysFloatRegs=256
 103 numPhysIntRegs=256
 104 numROBEntries=192
 105 numRobs=1
 106 numThreads=1
 107 profile=0
 108 progress_interval=0
 109 renameToDecodeDelay=1
 110 renameToFetchDelay=1
 111 renameToIEWDelay=2
 112 renameToROBDelay=1
 113 renameWidth=8
 114 simpoint_start_insts=
 115 smtCommitPolicy=RoundRobin
 116 smtFetchPolicy=SingleThread
 117 smtIQPolicy=Partitioned
 118 smtIQThreshold=100
 119 smtLSQPolicy=Partitioned
 120 smtLSQThreshold=100
 121 smtNumFetchingThreads=1
 122 smtROBPolicy=Partitioned
 123 smtROBThreshold=100
 124 socket_id=0
 125 squashWidth=8
 126 store_set_clear_period=250000
 127 switched_out=false
 128 system=system
 129 tracer=system.cpu.tracer
 130 trapLatency=13
 131 wbWidth=8
 132 workload=system.cpu.workload
 133 dcache_port=system.cpu.dcache.cpu_side
 134 icache_port=system.cpu.icache.cpu_side
 135
 136 [system.cpu.branchPred]
 137 type=BranchPredictor
 138 BTBEntries=4096
 139 BTBTagSize=16
 140 RASSize=16
 141 choiceCtrBits=2
 142 choicePredictorSize=8192
 143 eventq_index=0
 144 globalCtrBits=2
 145 globalPredictorSize=8192
 146 instShiftAmt=2
 147 localCtrBits=2
 148 localHistoryTableSize=2048
 149 localPredictorSize=2048
 150 numThreads=1
 151 predType=tournament
 152
 153 [system.cpu.dcache]
 154 type=BaseCache
 155 children=tags
 156 addr_ranges=0:18446744073709551615
 157 assoc=2
 158 clk_domain=system.cpu_clk_domain
 159 eventq_index=0
 160 forward_snoops=true
 161 hit_latency=2
 162 is_top_level=true
 163 max_miss_count=0
 164 mshrs=4
 165 prefetch_on_access=false
 166 prefetcher=Null
 167 response_latency=2
 168 sequential_access=false
 169 size=262144
 170 system=system
 171 tags=system.cpu.dcache.tags
 172 tgts_per_mshr=20
 173 two_queue=false
 174 write_buffers=8
 175 cpu_side=system.cpu.dcache_port
 176 mem_side=system.cpu.toL2Bus.slave[1]
 177
 178 [system.cpu.dcache.tags]
 179 type=LRU
 180 assoc=2
 181 block_size=64
 182 clk_domain=system.cpu_clk_domain
 183 eventq_index=0
 184 hit_latency=2
 185 sequential_access=false
 186 size=262144
 187
 188 [system.cpu.dtb]
 189 type=PowerTLB
 190 eventq_index=0
 191 size=64
 192
 193 [system.cpu.fuPool]
 194 type=FUPool
 195 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 196 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 197 eventq_index=0
 198
 199 [system.cpu.fuPool.FUList0]
 200 type=FUDesc
 201 children=opList
 202 count=6
 203 eventq_index=0
 204 opList=system.cpu.fuPool.FUList0.opList
 205
 206 [system.cpu.fuPool.FUList0.opList]
 207 type=OpDesc
 208 eventq_index=0
 209 issueLat=1
 210 opClass=IntAlu
 211 opLat=1
 212
 213 [system.cpu.fuPool.FUList1]
 214 type=FUDesc
 215 children=opList0 opList1
 216 count=2
 217 eventq_index=0
 218 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 219
 220 [system.cpu.fuPool.FUList1.opList0]
 221 type=OpDesc
 222 eventq_index=0
 223 issueLat=1
 224 opClass=IntMult
 225 opLat=3
 226
 227 [system.cpu.fuPool.FUList1.opList1]
 228 type=OpDesc
 229 eventq_index=0
 230 issueLat=19
 231 opClass=IntDiv
 232 opLat=20
 233
 234 [system.cpu.fuPool.FUList2]
 235 type=FUDesc
 236 children=opList0 opList1 opList2
 237 count=4
 238 eventq_index=0
 239 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 240
 241 [system.cpu.fuPool.FUList2.opList0]
 242 type=OpDesc
 243 eventq_index=0
 244 issueLat=1
 245 opClass=FloatAdd
 246 opLat=2
 247
 248 [system.cpu.fuPool.FUList2.opList1]
 249 type=OpDesc
 250 eventq_index=0
 251 issueLat=1
 252 opClass=FloatCmp
 253 opLat=2
 254
 255 [system.cpu.fuPool.FUList2.opList2]
 256 type=OpDesc
 257 eventq_index=0
 258 issueLat=1
 259 opClass=FloatCvt
 260 opLat=2
 261
 262 [system.cpu.fuPool.FUList3]
 263 type=FUDesc
 264 children=opList0 opList1 opList2
 265 count=2
 266 eventq_index=0
 267 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 268
 269 [system.cpu.fuPool.FUList3.opList0]
 270 type=OpDesc
 271 eventq_index=0
 272 issueLat=1
 273 opClass=FloatMult
 274 opLat=4
 275
 276 [system.cpu.fuPool.FUList3.opList1]
 277 type=OpDesc
 278 eventq_index=0
 279 issueLat=12
 280 opClass=FloatDiv
 281 opLat=12
 282
 283 [system.cpu.fuPool.FUList3.opList2]
 284 type=OpDesc
 285 eventq_index=0
 286 issueLat=24
 287 opClass=FloatSqrt
 288 opLat=24
 289
 290 [system.cpu.fuPool.FUList4]
 291 type=FUDesc
 292 children=opList
 293 count=0
 294 eventq_index=0
 295 opList=system.cpu.fuPool.FUList4.opList
 296
 297 [system.cpu.fuPool.FUList4.opList]
 298 type=OpDesc
 299 eventq_index=0
 300 issueLat=1
 301 opClass=MemRead
 302 opLat=1
 303
 304 [system.cpu.fuPool.FUList5]
 305 type=FUDesc
 306 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 307 count=4
 308 eventq_index=0
 309 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 310
 311 [system.cpu.fuPool.FUList5.opList00]
 312 type=OpDesc
 313 eventq_index=0
 314 issueLat=1
 315 opClass=SimdAdd
 316 opLat=1
 317
 318 [system.cpu.fuPool.FUList5.opList01]
 319 type=OpDesc
 320 eventq_index=0
 321 issueLat=1
 322 opClass=SimdAddAcc
 323 opLat=1
 324
 325 [system.cpu.fuPool.FUList5.opList02]
 326 type=OpDesc
 327 eventq_index=0
 328 issueLat=1
 329 opClass=SimdAlu
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList03]
 333 type=OpDesc
 334 eventq_index=0
 335 issueLat=1
 336 opClass=SimdCmp
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList04]
 340 type=OpDesc
 341 eventq_index=0
 342 issueLat=1
 343 opClass=SimdCvt
 344 opLat=1
 345
 346 [system.cpu.fuPool.FUList5.opList05]
 347 type=OpDesc
 348 eventq_index=0
 349 issueLat=1
 350 opClass=SimdMisc
 351 opLat=1
 352
 353 [system.cpu.fuPool.FUList5.opList06]
 354 type=OpDesc
 355 eventq_index=0
 356 issueLat=1
 357 opClass=SimdMult
 358 opLat=1
 359
 360 [system.cpu.fuPool.FUList5.opList07]
 361 type=OpDesc
 362 eventq_index=0
 363 issueLat=1
 364 opClass=SimdMultAcc
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList5.opList08]
 368 type=OpDesc
 369 eventq_index=0
 370 issueLat=1
 371 opClass=SimdShift
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList5.opList09]
 375 type=OpDesc
 376 eventq_index=0
 377 issueLat=1
 378 opClass=SimdShiftAcc
 379 opLat=1
 380
 381 [system.cpu.fuPool.FUList5.opList10]
 382 type=OpDesc
 383 eventq_index=0
 384 issueLat=1
 385 opClass=SimdSqrt
 386 opLat=1
 387
 388 [system.cpu.fuPool.FUList5.opList11]
 389 type=OpDesc
 390 eventq_index=0
 391 issueLat=1
 392 opClass=SimdFloatAdd
 393 opLat=1
 394
 395 [system.cpu.fuPool.FUList5.opList12]
 396 type=OpDesc
 397 eventq_index=0
 398 issueLat=1
 399 opClass=SimdFloatAlu
 400 opLat=1
 401
 402 [system.cpu.fuPool.FUList5.opList13]
 403 type=OpDesc
 404 eventq_index=0
 405 issueLat=1
 406 opClass=SimdFloatCmp
 407 opLat=1
 408
 409 [system.cpu.fuPool.FUList5.opList14]
 410 type=OpDesc
 411 eventq_index=0
 412 issueLat=1
 413 opClass=SimdFloatCvt
 414 opLat=1
 415
 416 [system.cpu.fuPool.FUList5.opList15]
 417 type=OpDesc
 418 eventq_index=0
 419 issueLat=1
 420 opClass=SimdFloatDiv
 421 opLat=1
 422
 423 [system.cpu.fuPool.FUList5.opList16]
 424 type=OpDesc
 425 eventq_index=0
 426 issueLat=1
 427 opClass=SimdFloatMisc
 428 opLat=1
 429
 430 [system.cpu.fuPool.FUList5.opList17]
 431 type=OpDesc
 432 eventq_index=0
 433 issueLat=1
 434 opClass=SimdFloatMult
 435 opLat=1
 436
 437 [system.cpu.fuPool.FUList5.opList18]
 438 type=OpDesc
 439 eventq_index=0
 440 issueLat=1
 441 opClass=SimdFloatMultAcc
 442 opLat=1
 443
 444 [system.cpu.fuPool.FUList5.opList19]
 445 type=OpDesc
 446 eventq_index=0
 447 issueLat=1
 448 opClass=SimdFloatSqrt
 449 opLat=1
 450
 451 [system.cpu.fuPool.FUList6]
 452 type=FUDesc
 453 children=opList
 454 count=0
 455 eventq_index=0
 456 opList=system.cpu.fuPool.FUList6.opList
 457
 458 [system.cpu.fuPool.FUList6.opList]
 459 type=OpDesc
 460 eventq_index=0
 461 issueLat=1
 462 opClass=MemWrite
 463 opLat=1
 464
 465 [system.cpu.fuPool.FUList7]
 466 type=FUDesc
 467 children=opList0 opList1
 468 count=4
 469 eventq_index=0
 470 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 471
 472 [system.cpu.fuPool.FUList7.opList0]
 473 type=OpDesc
 474 eventq_index=0
 475 issueLat=1
 476 opClass=MemRead
 477 opLat=1
 478
 479 [system.cpu.fuPool.FUList7.opList1]
 480 type=OpDesc
 481 eventq_index=0
 482 issueLat=1
 483 opClass=MemWrite
 484 opLat=1
 485
 486 [system.cpu.fuPool.FUList8]
 487 type=FUDesc
 488 children=opList
 489 count=1
 490 eventq_index=0
 491 opList=system.cpu.fuPool.FUList8.opList
 492
 493 [system.cpu.fuPool.FUList8.opList]
 494 type=OpDesc
 495 eventq_index=0
 496 issueLat=3
 497 opClass=IprAccess
 498 opLat=3
 499
 500 [system.cpu.icache]
 501 type=BaseCache
 502 children=tags
 503 addr_ranges=0:18446744073709551615
 504 assoc=2
 505 clk_domain=system.cpu_clk_domain
 506 eventq_index=0
 507 forward_snoops=true
 508 hit_latency=2
 509 is_top_level=true
 510 max_miss_count=0
 511 mshrs=4
 512 prefetch_on_access=false
 513 prefetcher=Null
 514 response_latency=2
 515 sequential_access=false
 516 size=131072
 517 system=system
 518 tags=system.cpu.icache.tags
 519 tgts_per_mshr=20
 520 two_queue=false
 521 write_buffers=8
 522 cpu_side=system.cpu.icache_port
 523 mem_side=system.cpu.toL2Bus.slave[0]
 524
 525 [system.cpu.icache.tags]
 526 type=LRU
 527 assoc=2
 528 block_size=64
 529 clk_domain=system.cpu_clk_domain
 530 eventq_index=0
 531 hit_latency=2
 532 sequential_access=false
 533 size=131072
 534
 535 [system.cpu.interrupts]
 536 type=PowerInterrupts
 537 eventq_index=0
 538
 539 [system.cpu.isa]
 540 type=PowerISA
 541 eventq_index=0
 542
 543 [system.cpu.itb]
 544 type=PowerTLB
 545 eventq_index=0
 546 size=64
 547
 548 [system.cpu.l2cache]
 549 type=BaseCache
 550 children=tags
 551 addr_ranges=0:18446744073709551615
 552 assoc=8
 553 clk_domain=system.cpu_clk_domain
 554 eventq_index=0
 555 forward_snoops=true
 556 hit_latency=20
 557 is_top_level=false
 558 max_miss_count=0
 559 mshrs=20
 560 prefetch_on_access=false
 561 prefetcher=Null
 562 response_latency=20
 563 sequential_access=false
 564 size=2097152
 565 system=system
 566 tags=system.cpu.l2cache.tags
 567 tgts_per_mshr=12
 568 two_queue=false
 569 write_buffers=8
 570 cpu_side=system.cpu.toL2Bus.master[0]
 571 mem_side=system.membus.slave[1]
 572
 573 [system.cpu.l2cache.tags]
 574 type=LRU
 575 assoc=8
 576 block_size=64
 577 clk_domain=system.cpu_clk_domain
 578 eventq_index=0
 579 hit_latency=20
 580 sequential_access=false
 581 size=2097152
 582
 583 [system.cpu.toL2Bus]
 584 type=CoherentXBar
 585 clk_domain=system.cpu_clk_domain
 586 eventq_index=0
 587 header_cycles=1
 588 snoop_filter=Null
 589 system=system
 590 use_default_range=false
 591 width=32
 592 master=system.cpu.l2cache.cpu_side
 593 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 594
 595 [system.cpu.tracer]
 596 type=ExeTracer
 597 eventq_index=0
 598
 599 [system.cpu.workload]
 600 type=LiveProcess
 601 cmd=hello
 602 cwd=
 603 egid=100
 604 env=
 605 errout=cerr
 606 euid=100
 607 eventq_index=0
 608 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
 609 gid=100
 610 input=cin
 611 max_stack_size=67108864
 612 output=cout
 613 pid=100
 614 ppid=99
 615 simpoint=0
 616 system=system
 617 uid=100
 618 useArchPT=false
 619
 620 [system.cpu_clk_domain]
 621 type=SrcClockDomain
 622 clock=500
 623 domain_id=-1
 624 eventq_index=0
 625 init_perf_level=0
 626 voltage_domain=system.voltage_domain
 627
 628 [system.dvfs_handler]
 629 type=DVFSHandler
 630 domains=
 631 enable=false
 632 eventq_index=0
 633 sys_clk_domain=system.clk_domain
 634 transition_latency=100000000
 635
 636 [system.membus]
 637 type=CoherentXBar
 638 clk_domain=system.clk_domain
 639 eventq_index=0
 640 header_cycles=1
 641 snoop_filter=Null
 642 system=system
 643 use_default_range=false
 644 width=8
 645 master=system.physmem.port
 646 slave=system.system_port system.cpu.l2cache.mem_side
 647
 648 [system.physmem]
 649 type=DRAMCtrl
 650 IDD0=0.075000
 651 IDD02=0.000000
 652 IDD2N=0.050000
 653 IDD2N2=0.000000
 654 IDD2P0=0.000000
 655 IDD2P02=0.000000
 656 IDD2P1=0.000000
 657 IDD2P12=0.000000
 658 IDD3N=0.057000
 659 IDD3N2=0.000000
 660 IDD3P0=0.000000
 661 IDD3P02=0.000000
 662 IDD3P1=0.000000
 663 IDD3P12=0.000000
 664 IDD4R=0.187000
 665 IDD4R2=0.000000
 666 IDD4W=0.165000
 667 IDD4W2=0.000000
 668 IDD5=0.220000
 669 IDD52=0.000000
 670 IDD6=0.000000
 671 IDD62=0.000000
 672 VDD=1.500000
 673 VDD2=0.000000
 674 activation_limit=4
 675 addr_mapping=RoRaBaChCo
 676 bank_groups_per_rank=0
 677 banks_per_rank=8
 678 burst_length=8
 679 channels=1
 680 clk_domain=system.clk_domain
 681 conf_table_reported=true
 682 device_bus_width=8
 683 device_rowbuffer_size=1024
 684 devices_per_rank=8
 685 dll=true
 686 eventq_index=0
 687 in_addr_map=true
 688 max_accesses_per_row=16
 689 mem_sched_policy=frfcfs
 690 min_writes_per_switch=16
 691 null=false
 692 page_policy=open_adaptive
 693 range=0:134217727
 694 ranks_per_channel=2
 695 read_buffer_size=32
 696 static_backend_latency=10000
 697 static_frontend_latency=10000
 698 tBURST=5000
 699 tCCD_L=0
 700 tCK=1250
 701 tCL=13750
 702 tCS=2500
 703 tRAS=35000
 704 tRCD=13750
 705 tREFI=7800000
 706 tRFC=260000
 707 tRP=13750
 708 tRRD=6000
 709 tRRD_L=0
 710 tRTP=7500
 711 tRTW=2500
 712 tWR=15000
 713 tWTR=7500
 714 tXAW=30000
 715 tXP=0
 716 tXPDLL=0
 717 tXS=0
 718 tXSDLL=0
 719 write_buffer_size=64
 720 write_high_thresh_perc=85
 721 write_low_thresh_perc=50
 722 port=system.membus.master[0]
 723
 724 [system.voltage_domain]
 725 type=VoltageDomain
 726 eventq_index=0
 727 voltage=1.000000
 728