tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 multi_thread=false
  28 num_work_ids=16
  29 readfile=
  30 symbolfile=
  31 work_begin_ckpt_count=0
  32 work_begin_cpu_id_exit=-1
  33 work_begin_exit_count=0
  34 work_cpus_ckpt_count=0
  35 work_end_ckpt_count=0
  36 work_end_exit_count=0
  37 work_item_id=-1
  38 system_port=system.membus.slave[0]
  39
  40 [system.clk_domain]
  41 type=SrcClockDomain
  42 clock=1000
  43 domain_id=-1
  44 eventq_index=0
  45 init_perf_level=0
  46 voltage_domain=system.voltage_domain
  47
  48 [system.cpu]
  49 type=DerivO3CPU
  50 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  51 LFSTSize=1024
  52 LQEntries=32
  53 LSQCheckLoads=true
  54 LSQDepCheckShift=4
  55 SQEntries=32
  56 SSITSize=1024
  57 UnifiedTLB=true
  58 activity=0
  59 backComSize=5
  60 branchPred=system.cpu.branchPred
  61 cachePorts=200
  62 checker=Null
  63 clk_domain=system.cpu_clk_domain
  64 commitToDecodeDelay=1
  65 commitToFetchDelay=1
  66 commitToIEWDelay=1
  67 commitToRenameDelay=1
  68 commitWidth=8
  69 cpu_id=0
  70 decodeToFetchDelay=1
  71 decodeToRenameDelay=1
  72 decodeWidth=8
  73 dispatchWidth=8
  74 do_checkpoint_insts=true
  75 do_quiesce=true
  76 do_statistics_insts=true
  77 dtb=system.cpu.dtb
  78 eventq_index=0
  79 fetchBufferSize=64
  80 fetchQueueSize=32
  81 fetchToDecodeDelay=1
  82 fetchTrapLatency=1
  83 fetchWidth=8
  84 forwardComSize=5
  85 fuPool=system.cpu.fuPool
  86 function_trace=false
  87 function_trace_start=0
  88 iewToCommitDelay=1
  89 iewToDecodeDelay=1
  90 iewToFetchDelay=1
  91 iewToRenameDelay=1
  92 interrupts=system.cpu.interrupts
  93 isa=system.cpu.isa
  94 issueToExecuteDelay=1
  95 issueWidth=8
  96 itb=system.cpu.itb
  97 max_insts_all_threads=0
  98 max_insts_any_thread=0
  99 max_loads_all_threads=0
 100 max_loads_any_thread=0
 101 needsTSO=false
 102 numIQEntries=64
 103 numPhysCCRegs=0
 104 numPhysFloatRegs=256
 105 numPhysIntRegs=256
 106 numROBEntries=192
 107 numRobs=1
 108 numThreads=1
 109 profile=0
 110 progress_interval=0
 111 renameToDecodeDelay=1
 112 renameToFetchDelay=1
 113 renameToIEWDelay=2
 114 renameToROBDelay=1
 115 renameWidth=8
 116 simpoint_start_insts=
 117 smtCommitPolicy=RoundRobin
 118 smtFetchPolicy=SingleThread
 119 smtIQPolicy=Partitioned
 120 smtIQThreshold=100
 121 smtLSQPolicy=Partitioned
 122 smtLSQThreshold=100
 123 smtNumFetchingThreads=1
 124 smtROBPolicy=Partitioned
 125 smtROBThreshold=100
 126 socket_id=0
 127 squashWidth=8
 128 store_set_clear_period=250000
 129 switched_out=false
 130 system=system
 131 tracer=system.cpu.tracer
 132 trapLatency=13
 133 wbWidth=8
 134 workload=system.cpu.workload
 135 dcache_port=system.cpu.dcache.cpu_side
 136 icache_port=system.cpu.icache.cpu_side
 137
 138 [system.cpu.branchPred]
 139 type=TournamentBP
 140 BTBEntries=4096
 141 BTBTagSize=16
 142 RASSize=16
 143 choiceCtrBits=2
 144 choicePredictorSize=8192
 145 eventq_index=0
 146 globalCtrBits=2
 147 globalPredictorSize=8192
 148 instShiftAmt=2
 149 localCtrBits=2
 150 localHistoryTableSize=2048
 151 localPredictorSize=2048
 152 numThreads=1
 153
 154 [system.cpu.dcache]
 155 type=Cache
 156 children=tags
 157 addr_ranges=0:18446744073709551615
 158 assoc=2
 159 clk_domain=system.cpu_clk_domain
 160 clusivity=mostly_incl
 161 demand_mshr_reserve=1
 162 eventq_index=0
 163 forward_snoops=true
 164 hit_latency=2
 165 is_read_only=false
 166 max_miss_count=0
 167 mshrs=4
 168 prefetch_on_access=false
 169 prefetcher=Null
 170 response_latency=2
 171 sequential_access=false
 172 size=262144
 173 system=system
 174 tags=system.cpu.dcache.tags
 175 tgts_per_mshr=20
 176 write_buffers=8
 177 writeback_clean=false
 178 cpu_side=system.cpu.dcache_port
 179 mem_side=system.cpu.toL2Bus.slave[1]
 180
 181 [system.cpu.dcache.tags]
 182 type=LRU
 183 assoc=2
 184 block_size=64
 185 clk_domain=system.cpu_clk_domain
 186 eventq_index=0
 187 hit_latency=2
 188 sequential_access=false
 189 size=262144
 190
 191 [system.cpu.dtb]
 192 type=PowerTLB
 193 eventq_index=0
 194 size=64
 195
 196 [system.cpu.fuPool]
 197 type=FUPool
 198 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 199 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 200 eventq_index=0
 201
 202 [system.cpu.fuPool.FUList0]
 203 type=FUDesc
 204 children=opList
 205 count=6
 206 eventq_index=0
 207 opList=system.cpu.fuPool.FUList0.opList
 208
 209 [system.cpu.fuPool.FUList0.opList]
 210 type=OpDesc
 211 eventq_index=0
 212 opClass=IntAlu
 213 opLat=1
 214 pipelined=true
 215
 216 [system.cpu.fuPool.FUList1]
 217 type=FUDesc
 218 children=opList0 opList1
 219 count=2
 220 eventq_index=0
 221 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 222
 223 [system.cpu.fuPool.FUList1.opList0]
 224 type=OpDesc
 225 eventq_index=0
 226 opClass=IntMult
 227 opLat=3
 228 pipelined=true
 229
 230 [system.cpu.fuPool.FUList1.opList1]
 231 type=OpDesc
 232 eventq_index=0
 233 opClass=IntDiv
 234 opLat=20
 235 pipelined=false
 236
 237 [system.cpu.fuPool.FUList2]
 238 type=FUDesc
 239 children=opList0 opList1 opList2
 240 count=4
 241 eventq_index=0
 242 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 243
 244 [system.cpu.fuPool.FUList2.opList0]
 245 type=OpDesc
 246 eventq_index=0
 247 opClass=FloatAdd
 248 opLat=2
 249 pipelined=true
 250
 251 [system.cpu.fuPool.FUList2.opList1]
 252 type=OpDesc
 253 eventq_index=0
 254 opClass=FloatCmp
 255 opLat=2
 256 pipelined=true
 257
 258 [system.cpu.fuPool.FUList2.opList2]
 259 type=OpDesc
 260 eventq_index=0
 261 opClass=FloatCvt
 262 opLat=2
 263 pipelined=true
 264
 265 [system.cpu.fuPool.FUList3]
 266 type=FUDesc
 267 children=opList0 opList1 opList2
 268 count=2
 269 eventq_index=0
 270 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 271
 272 [system.cpu.fuPool.FUList3.opList0]
 273 type=OpDesc
 274 eventq_index=0
 275 opClass=FloatMult
 276 opLat=4
 277 pipelined=true
 278
 279 [system.cpu.fuPool.FUList3.opList1]
 280 type=OpDesc
 281 eventq_index=0
 282 opClass=FloatDiv
 283 opLat=12
 284 pipelined=false
 285
 286 [system.cpu.fuPool.FUList3.opList2]
 287 type=OpDesc
 288 eventq_index=0
 289 opClass=FloatSqrt
 290 opLat=24
 291 pipelined=false
 292
 293 [system.cpu.fuPool.FUList4]
 294 type=FUDesc
 295 children=opList
 296 count=0
 297 eventq_index=0
 298 opList=system.cpu.fuPool.FUList4.opList
 299
 300 [system.cpu.fuPool.FUList4.opList]
 301 type=OpDesc
 302 eventq_index=0
 303 opClass=MemRead
 304 opLat=1
 305 pipelined=true
 306
 307 [system.cpu.fuPool.FUList5]
 308 type=FUDesc
 309 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 310 count=4
 311 eventq_index=0
 312 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 313
 314 [system.cpu.fuPool.FUList5.opList00]
 315 type=OpDesc
 316 eventq_index=0
 317 opClass=SimdAdd
 318 opLat=1
 319 pipelined=true
 320
 321 [system.cpu.fuPool.FUList5.opList01]
 322 type=OpDesc
 323 eventq_index=0
 324 opClass=SimdAddAcc
 325 opLat=1
 326 pipelined=true
 327
 328 [system.cpu.fuPool.FUList5.opList02]
 329 type=OpDesc
 330 eventq_index=0
 331 opClass=SimdAlu
 332 opLat=1
 333 pipelined=true
 334
 335 [system.cpu.fuPool.FUList5.opList03]
 336 type=OpDesc
 337 eventq_index=0
 338 opClass=SimdCmp
 339 opLat=1
 340 pipelined=true
 341
 342 [system.cpu.fuPool.FUList5.opList04]
 343 type=OpDesc
 344 eventq_index=0
 345 opClass=SimdCvt
 346 opLat=1
 347 pipelined=true
 348
 349 [system.cpu.fuPool.FUList5.opList05]
 350 type=OpDesc
 351 eventq_index=0
 352 opClass=SimdMisc
 353 opLat=1
 354 pipelined=true
 355
 356 [system.cpu.fuPool.FUList5.opList06]
 357 type=OpDesc
 358 eventq_index=0
 359 opClass=SimdMult
 360 opLat=1
 361 pipelined=true
 362
 363 [system.cpu.fuPool.FUList5.opList07]
 364 type=OpDesc
 365 eventq_index=0
 366 opClass=SimdMultAcc
 367 opLat=1
 368 pipelined=true
 369
 370 [system.cpu.fuPool.FUList5.opList08]
 371 type=OpDesc
 372 eventq_index=0
 373 opClass=SimdShift
 374 opLat=1
 375 pipelined=true
 376
 377 [system.cpu.fuPool.FUList5.opList09]
 378 type=OpDesc
 379 eventq_index=0
 380 opClass=SimdShiftAcc
 381 opLat=1
 382 pipelined=true
 383
 384 [system.cpu.fuPool.FUList5.opList10]
 385 type=OpDesc
 386 eventq_index=0
 387 opClass=SimdSqrt
 388 opLat=1
 389 pipelined=true
 390
 391 [system.cpu.fuPool.FUList5.opList11]
 392 type=OpDesc
 393 eventq_index=0
 394 opClass=SimdFloatAdd
 395 opLat=1
 396 pipelined=true
 397
 398 [system.cpu.fuPool.FUList5.opList12]
 399 type=OpDesc
 400 eventq_index=0
 401 opClass=SimdFloatAlu
 402 opLat=1
 403 pipelined=true
 404
 405 [system.cpu.fuPool.FUList5.opList13]
 406 type=OpDesc
 407 eventq_index=0
 408 opClass=SimdFloatCmp
 409 opLat=1
 410 pipelined=true
 411
 412 [system.cpu.fuPool.FUList5.opList14]
 413 type=OpDesc
 414 eventq_index=0
 415 opClass=SimdFloatCvt
 416 opLat=1
 417 pipelined=true
 418
 419 [system.cpu.fuPool.FUList5.opList15]
 420 type=OpDesc
 421 eventq_index=0
 422 opClass=SimdFloatDiv
 423 opLat=1
 424 pipelined=true
 425
 426 [system.cpu.fuPool.FUList5.opList16]
 427 type=OpDesc
 428 eventq_index=0
 429 opClass=SimdFloatMisc
 430 opLat=1
 431 pipelined=true
 432
 433 [system.cpu.fuPool.FUList5.opList17]
 434 type=OpDesc
 435 eventq_index=0
 436 opClass=SimdFloatMult
 437 opLat=1
 438 pipelined=true
 439
 440 [system.cpu.fuPool.FUList5.opList18]
 441 type=OpDesc
 442 eventq_index=0
 443 opClass=SimdFloatMultAcc
 444 opLat=1
 445 pipelined=true
 446
 447 [system.cpu.fuPool.FUList5.opList19]
 448 type=OpDesc
 449 eventq_index=0
 450 opClass=SimdFloatSqrt
 451 opLat=1
 452 pipelined=true
 453
 454 [system.cpu.fuPool.FUList6]
 455 type=FUDesc
 456 children=opList
 457 count=0
 458 eventq_index=0
 459 opList=system.cpu.fuPool.FUList6.opList
 460
 461 [system.cpu.fuPool.FUList6.opList]
 462 type=OpDesc
 463 eventq_index=0
 464 opClass=MemWrite
 465 opLat=1
 466 pipelined=true
 467
 468 [system.cpu.fuPool.FUList7]
 469 type=FUDesc
 470 children=opList0 opList1
 471 count=4
 472 eventq_index=0
 473 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 474
 475 [system.cpu.fuPool.FUList7.opList0]
 476 type=OpDesc
 477 eventq_index=0
 478 opClass=MemRead
 479 opLat=1
 480 pipelined=true
 481
 482 [system.cpu.fuPool.FUList7.opList1]
 483 type=OpDesc
 484 eventq_index=0
 485 opClass=MemWrite
 486 opLat=1
 487 pipelined=true
 488
 489 [system.cpu.fuPool.FUList8]
 490 type=FUDesc
 491 children=opList
 492 count=1
 493 eventq_index=0
 494 opList=system.cpu.fuPool.FUList8.opList
 495
 496 [system.cpu.fuPool.FUList8.opList]
 497 type=OpDesc
 498 eventq_index=0
 499 opClass=IprAccess
 500 opLat=3
 501 pipelined=false
 502
 503 [system.cpu.icache]
 504 type=Cache
 505 children=tags
 506 addr_ranges=0:18446744073709551615
 507 assoc=2
 508 clk_domain=system.cpu_clk_domain
 509 clusivity=mostly_incl
 510 demand_mshr_reserve=1
 511 eventq_index=0
 512 forward_snoops=true
 513 hit_latency=2
 514 is_read_only=true
 515 max_miss_count=0
 516 mshrs=4
 517 prefetch_on_access=false
 518 prefetcher=Null
 519 response_latency=2
 520 sequential_access=false
 521 size=131072
 522 system=system
 523 tags=system.cpu.icache.tags
 524 tgts_per_mshr=20
 525 write_buffers=8
 526 writeback_clean=true
 527 cpu_side=system.cpu.icache_port
 528 mem_side=system.cpu.toL2Bus.slave[0]
 529
 530 [system.cpu.icache.tags]
 531 type=LRU
 532 assoc=2
 533 block_size=64
 534 clk_domain=system.cpu_clk_domain
 535 eventq_index=0
 536 hit_latency=2
 537 sequential_access=false
 538 size=131072
 539
 540 [system.cpu.interrupts]
 541 type=PowerInterrupts
 542 eventq_index=0
 543
 544 [system.cpu.isa]
 545 type=PowerISA
 546 eventq_index=0
 547
 548 [system.cpu.itb]
 549 type=PowerTLB
 550 eventq_index=0
 551 size=64
 552
 553 [system.cpu.l2cache]
 554 type=Cache
 555 children=tags
 556 addr_ranges=0:18446744073709551615
 557 assoc=8
 558 clk_domain=system.cpu_clk_domain
 559 clusivity=mostly_incl
 560 demand_mshr_reserve=1
 561 eventq_index=0
 562 forward_snoops=true
 563 hit_latency=20
 564 is_read_only=false
 565 max_miss_count=0
 566 mshrs=20
 567 prefetch_on_access=false
 568 prefetcher=Null
 569 response_latency=20
 570 sequential_access=false
 571 size=2097152
 572 system=system
 573 tags=system.cpu.l2cache.tags
 574 tgts_per_mshr=12
 575 write_buffers=8
 576 writeback_clean=false
 577 cpu_side=system.cpu.toL2Bus.master[0]
 578 mem_side=system.membus.slave[1]
 579
 580 [system.cpu.l2cache.tags]
 581 type=LRU
 582 assoc=8
 583 block_size=64
 584 clk_domain=system.cpu_clk_domain
 585 eventq_index=0
 586 hit_latency=20
 587 sequential_access=false
 588 size=2097152
 589
 590 [system.cpu.toL2Bus]
 591 type=CoherentXBar
 592 children=snoop_filter
 593 clk_domain=system.cpu_clk_domain
 594 eventq_index=0
 595 forward_latency=0
 596 frontend_latency=1
 597 response_latency=1
 598 snoop_filter=system.cpu.toL2Bus.snoop_filter
 599 snoop_response_latency=1
 600 system=system
 601 use_default_range=false
 602 width=32
 603 master=system.cpu.l2cache.cpu_side
 604 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 605
 606 [system.cpu.toL2Bus.snoop_filter]
 607 type=SnoopFilter
 608 eventq_index=0
 609 lookup_latency=0
 610 max_capacity=8388608
 611 system=system
 612
 613 [system.cpu.tracer]
 614 type=ExeTracer
 615 eventq_index=0
 616
 617 [system.cpu.workload]
 618 type=LiveProcess
 619 cmd=hello
 620 cwd=
 621 drivers=
 622 egid=100
 623 env=
 624 errout=cerr
 625 euid=100
 626 eventq_index=0
 627 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
 628 gid=100
 629 input=cin
 630 kvmInSE=false
 631 max_stack_size=67108864
 632 output=cout
 633 pid=100
 634 ppid=99
 635 simpoint=0
 636 system=system
 637 uid=100
 638 useArchPT=false
 639
 640 [system.cpu_clk_domain]
 641 type=SrcClockDomain
 642 clock=500
 643 domain_id=-1
 644 eventq_index=0
 645 init_perf_level=0
 646 voltage_domain=system.voltage_domain
 647
 648 [system.dvfs_handler]
 649 type=DVFSHandler
 650 domains=
 651 enable=false
 652 eventq_index=0
 653 sys_clk_domain=system.clk_domain
 654 transition_latency=100000000
 655
 656 [system.membus]
 657 type=CoherentXBar
 658 clk_domain=system.clk_domain
 659 eventq_index=0
 660 forward_latency=4
 661 frontend_latency=3
 662 response_latency=2
 663 snoop_filter=Null
 664 snoop_response_latency=4
 665 system=system
 666 use_default_range=false
 667 width=16
 668 master=system.physmem.port
 669 slave=system.system_port system.cpu.l2cache.mem_side
 670
 671 [system.physmem]
 672 type=DRAMCtrl
 673 IDD0=0.075000
 674 IDD02=0.000000
 675 IDD2N=0.050000
 676 IDD2N2=0.000000
 677 IDD2P0=0.000000
 678 IDD2P02=0.000000
 679 IDD2P1=0.000000
 680 IDD2P12=0.000000
 681 IDD3N=0.057000
 682 IDD3N2=0.000000
 683 IDD3P0=0.000000
 684 IDD3P02=0.000000
 685 IDD3P1=0.000000
 686 IDD3P12=0.000000
 687 IDD4R=0.187000
 688 IDD4R2=0.000000
 689 IDD4W=0.165000
 690 IDD4W2=0.000000
 691 IDD5=0.220000
 692 IDD52=0.000000
 693 IDD6=0.000000
 694 IDD62=0.000000
 695 VDD=1.500000
 696 VDD2=0.000000
 697 activation_limit=4
 698 addr_mapping=RoRaBaCoCh
 699 bank_groups_per_rank=0
 700 banks_per_rank=8
 701 burst_length=8
 702 channels=1
 703 clk_domain=system.clk_domain
 704 conf_table_reported=true
 705 device_bus_width=8
 706 device_rowbuffer_size=1024
 707 device_size=536870912
 708 devices_per_rank=8
 709 dll=true
 710 eventq_index=0
 711 in_addr_map=true
 712 max_accesses_per_row=16
 713 mem_sched_policy=frfcfs
 714 min_writes_per_switch=16
 715 null=false
 716 page_policy=open_adaptive
 717 range=0:134217727
 718 ranks_per_channel=2
 719 read_buffer_size=32
 720 static_backend_latency=10000
 721 static_frontend_latency=10000
 722 tBURST=5000
 723 tCCD_L=0
 724 tCK=1250
 725 tCL=13750
 726 tCS=2500
 727 tRAS=35000
 728 tRCD=13750
 729 tREFI=7800000
 730 tRFC=260000
 731 tRP=13750
 732 tRRD=6000
 733 tRRD_L=0
 734 tRTP=7500
 735 tRTW=2500
 736 tWR=15000
 737 tWTR=7500
 738 tXAW=30000
 739 tXP=0
 740 tXPDLL=0
 741 tXS=0
 742 tXSDLL=0
 743 write_buffer_size=64
 744 write_high_thresh_perc=85
 745 write_low_thresh_perc=50
 746 port=system.membus.master[0]
 747
 748 [system.voltage_domain]
 749 type=VoltageDomain
 750 eventq_index=0
 751 voltage=1.000000
 752