2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000018 # Number of seconds simulated
4 sim_ticks 18326500 # Number of ticks simulated
5 final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 41507 # Simulator instruction rate (inst/s)
8 host_op_rate 41499 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 131284333 # Simulator tick rate (ticks/s)
10 host_mem_usage 224304 # Number of bytes of host memory used
11 host_seconds 0.14 # Real time elapsed on the host
12 sim_insts 5792 # Number of instructions simulated
13 sim_ops 5792 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 446 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 28544 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 18199000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 446 # Categorize read packet sizes
81 system.physmem.writePktSize::0 0 # Categorize write packet sizes
82 system.physmem.writePktSize::1 0 # Categorize write packet sizes
83 system.physmem.writePktSize::2 0 # Categorize write packet sizes
84 system.physmem.writePktSize::3 0 # Categorize write packet sizes
85 system.physmem.writePktSize::4 0 # Categorize write packet sizes
86 system.physmem.writePktSize::5 0 # Categorize write packet sizes
87 system.physmem.writePktSize::6 0 # Categorize write packet sizes
88 system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
89 system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152 system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation
153 system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation
154 system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation
155 system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation
172 system.physmem.totQLat 2004500 # Total cycles spent in queuing delays
173 system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests
174 system.physmem.totBusLat 2230000 # Total cycles spent in databus access
175 system.physmem.totBankLat 6737500 # Total cycles spent in bank access
176 system.physmem.avgQLat 4494.39 # Average queueing delay per request
177 system.physmem.avgBankLat 15106.50 # Average bank access latency per request
178 system.physmem.avgBusLat 5000.00 # Average bus latency per request
179 system.physmem.avgMemAccLat 24600.90 # Average memory access latency
180 system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s
181 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
182 system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s
183 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
184 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
185 system.physmem.busUtil 12.17 # Data bus utilization in percentage
186 system.physmem.avgRdQLen 0.60 # Average read queue length over time
187 system.physmem.avgWrQLen 0.00 # Average write queue length over time
188 system.physmem.readRowHits 380 # Number of row buffer hits during reads
189 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
190 system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads
191 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
192 system.physmem.avgGap 40804.93 # Average gap between requests
193 system.membus.throughput 1557525987 # Throughput (bytes/s)
194 system.membus.trans_dist::ReadReq 399 # Transaction distribution
195 system.membus.trans_dist::ReadResp 399 # Transaction distribution
196 system.membus.trans_dist::ReadExReq 47 # Transaction distribution
197 system.membus.trans_dist::ReadExResp 47 # Transaction distribution
198 system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
199 system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
200 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
201 system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
202 system.membus.data_through_bus 28544 # Total data (bytes)
203 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
204 system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks)
205 system.membus.reqLayer0.utilization 3.1 # Layer utilization (%)
206 system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks)
207 system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
208 system.cpu.branchPred.lookups 2238 # Number of BP lookups
209 system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted
210 system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
211 system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups
212 system.cpu.branchPred.BTBHits 603 # Number of BTB hits
213 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
214 system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage
215 system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target.
216 system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
217 system.cpu.dtb.read_hits 0 # DTB read hits
218 system.cpu.dtb.read_misses 0 # DTB read misses
219 system.cpu.dtb.read_accesses 0 # DTB read accesses
220 system.cpu.dtb.write_hits 0 # DTB write hits
221 system.cpu.dtb.write_misses 0 # DTB write misses
222 system.cpu.dtb.write_accesses 0 # DTB write accesses
223 system.cpu.dtb.hits 0 # DTB hits
224 system.cpu.dtb.misses 0 # DTB misses
225 system.cpu.dtb.accesses 0 # DTB accesses
226 system.cpu.itb.read_hits 0 # DTB read hits
227 system.cpu.itb.read_misses 0 # DTB read misses
228 system.cpu.itb.read_accesses 0 # DTB read accesses
229 system.cpu.itb.write_hits 0 # DTB write hits
230 system.cpu.itb.write_misses 0 # DTB write misses
231 system.cpu.itb.write_accesses 0 # DTB write accesses
232 system.cpu.itb.hits 0 # DTB hits
233 system.cpu.itb.misses 0 # DTB misses
234 system.cpu.itb.accesses 0 # DTB accesses
235 system.cpu.workload.num_syscalls 9 # Number of system calls
236 system.cpu.numCycles 36654 # number of cpu cycles simulated
237 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
238 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
239 system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss
240 system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed
241 system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered
242 system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken
243 system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked
244 system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing
245 system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked
246 system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched
247 system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed
248 system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total)
249 system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total)
250 system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total)
251 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
252 system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total)
253 system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total)
254 system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total)
255 system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total)
256 system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total)
257 system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total)
258 system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total)
259 system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total)
260 system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total)
261 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
264 system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total)
265 system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle
266 system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle
267 system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle
268 system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked
269 system.cpu.decode.RunCycles 2096 # Number of cycles decode is running
270 system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking
271 system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing
272 system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch
273 system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
274 system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode
275 system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
276 system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing
277 system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle
278 system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking
279 system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
280 system.cpu.rename.RunCycles 1984 # Number of cycles rename is running
281 system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking
282 system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename
283 system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
284 system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full
285 system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed
286 system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made
287 system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups
288 system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
289 system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
290 system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing
291 system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
292 system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
293 system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer
294 system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit.
295 system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
296 system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
297 system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
298 system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec)
299 system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
300 system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued
301 system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
302 system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling
303 system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph
304 system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
305 system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle
306 system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle
307 system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle
308 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
309 system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle
310 system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle
311 system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle
312 system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle
313 system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle
314 system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle
315 system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle
316 system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
317 system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle
318 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
319 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
320 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle
322 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
323 system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available
324 system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available
325 system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available
326 system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available
327 system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available
328 system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available
329 system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available
330 system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available
331 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available
332 system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available
333 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available
334 system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available
335 system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available
336 system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available
337 system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available
338 system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available
340 system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available
341 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available
342 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available
343 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available
344 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available
352 system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available
353 system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available
354 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
355 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
356 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
357 system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued
358 system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued
359 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued
360 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued
361 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued
362 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued
363 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued
364 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued
365 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued
366 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued
367 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued
368 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued
369 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued
370 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued
371 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued
372 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued
374 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued
375 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued
376 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued
377 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued
378 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued
380 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued
386 system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued
387 system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued
388 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
389 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
390 system.cpu.iq.FU_type_0::total 8903 # Type of FU issued
391 system.cpu.iq.rate 0.242893 # Inst issue rate
392 system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
393 system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst)
394 system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads
395 system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes
396 system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses
397 system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
398 system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
399 system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
400 system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses
401 system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
402 system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
403 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
404 system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed
405 system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
406 system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
407 system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed
408 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
409 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
410 system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
411 system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
412 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
413 system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing
414 system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking
415 system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
416 system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ
417 system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch
418 system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions
419 system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
420 system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
421 system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
422 system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
423 system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
424 system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
425 system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
426 system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
427 system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions
428 system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed
429 system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
430 system.cpu.iew.exec_swp 0 # number of swp insts executed
431 system.cpu.iew.exec_nop 0 # number of nop insts executed
432 system.cpu.iew.exec_refs 3201 # number of memory reference insts executed
433 system.cpu.iew.exec_branches 1351 # Number of branches executed
434 system.cpu.iew.exec_stores 1523 # Number of stores executed
435 system.cpu.iew.exec_rate 0.231953 # Inst execution rate
436 system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit
437 system.cpu.iew.wb_count 8157 # cumulative count of insts written-back
438 system.cpu.iew.wb_producers 4222 # num instructions producing a value
439 system.cpu.iew.wb_consumers 6684 # num instructions consuming a value
440 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
441 system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle
442 system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back
443 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
444 system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit
445 system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
446 system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
447 system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle
448 system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle
449 system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle
450 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
451 system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle
452 system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle
453 system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle
454 system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle
455 system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle
456 system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle
457 system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle
458 system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle
459 system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
460 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
461 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
462 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle
464 system.cpu.commit.committedInsts 5792 # Number of instructions committed
465 system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
466 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
467 system.cpu.commit.refs 2007 # Number of memory references committed
468 system.cpu.commit.loads 961 # Number of loads committed
469 system.cpu.commit.membars 7 # Number of memory barriers committed
470 system.cpu.commit.branches 1037 # Number of branches committed
471 system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
472 system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
473 system.cpu.commit.function_calls 103 # Number of function calls committed.
474 system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
475 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
476 system.cpu.rob.rob_reads 21419 # The number of ROB reads
477 system.cpu.rob.rob_writes 21457 # The number of ROB writes
478 system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
479 system.cpu.idleCycles 24797 # Total number of cycles that the CPU has spent unscheduled due to idling
480 system.cpu.committedInsts 5792 # Number of Instructions Simulated
481 system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
482 system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
483 system.cpu.cpi 6.328384 # CPI: Cycles Per Instruction
484 system.cpu.cpi_total 6.328384 # CPI: Total CPI of All Threads
485 system.cpu.ipc 0.158018 # IPC: Instructions Per Cycle
486 system.cpu.ipc_total 0.158018 # IPC: Total IPC of All Threads
487 system.cpu.int_regfile_reads 13474 # number of integer regfile reads
488 system.cpu.int_regfile_writes 7049 # number of integer regfile writes
489 system.cpu.fp_regfile_reads 25 # number of floating regfile reads
490 system.cpu.fp_regfile_writes 2 # number of floating regfile writes
491 system.cpu.toL2Bus.throughput 1581971462 # Throughput (bytes/s)
492 system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
493 system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
494 system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
495 system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
496 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes)
497 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes)
498 system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes)
499 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes)
500 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes)
501 system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes)
502 system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes)
503 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
504 system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
505 system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
506 system.cpu.toL2Bus.respLayer0.occupancy 526500 # Layer occupancy (ticks)
507 system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
508 system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
509 system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
510 system.cpu.icache.replacements 0 # number of replacements
511 system.cpu.icache.tagsinuse 167.412828 # Cycle average of tags in use
512 system.cpu.icache.total_refs 1371 # Total number of references to valid blocks.
513 system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks.
514 system.cpu.icache.avg_refs 3.905983 # Average number of references to valid blocks.
515 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
516 system.cpu.icache.occ_blocks::cpu.inst 167.412828 # Average occupied blocks per requestor
517 system.cpu.icache.occ_percent::cpu.inst 0.081745 # Average percentage of cache occupancy
518 system.cpu.icache.occ_percent::total 0.081745 # Average percentage of cache occupancy
519 system.cpu.icache.ReadReq_hits::cpu.inst 1371 # number of ReadReq hits
520 system.cpu.icache.ReadReq_hits::total 1371 # number of ReadReq hits
521 system.cpu.icache.demand_hits::cpu.inst 1371 # number of demand (read+write) hits
522 system.cpu.icache.demand_hits::total 1371 # number of demand (read+write) hits
523 system.cpu.icache.overall_hits::cpu.inst 1371 # number of overall hits
524 system.cpu.icache.overall_hits::total 1371 # number of overall hits
525 system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses
526 system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses
527 system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses
528 system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses
529 system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses
530 system.cpu.icache.overall_misses::total 442 # number of overall misses
531 system.cpu.icache.ReadReq_miss_latency::cpu.inst 28629500 # number of ReadReq miss cycles
532 system.cpu.icache.ReadReq_miss_latency::total 28629500 # number of ReadReq miss cycles
533 system.cpu.icache.demand_miss_latency::cpu.inst 28629500 # number of demand (read+write) miss cycles
534 system.cpu.icache.demand_miss_latency::total 28629500 # number of demand (read+write) miss cycles
535 system.cpu.icache.overall_miss_latency::cpu.inst 28629500 # number of overall miss cycles
536 system.cpu.icache.overall_miss_latency::total 28629500 # number of overall miss cycles
537 system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses)
538 system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses)
539 system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses
540 system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses
541 system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses
542 system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses
543 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243795 # miss rate for ReadReq accesses
544 system.cpu.icache.ReadReq_miss_rate::total 0.243795 # miss rate for ReadReq accesses
545 system.cpu.icache.demand_miss_rate::cpu.inst 0.243795 # miss rate for demand accesses
546 system.cpu.icache.demand_miss_rate::total 0.243795 # miss rate for demand accesses
547 system.cpu.icache.overall_miss_rate::cpu.inst 0.243795 # miss rate for overall accesses
548 system.cpu.icache.overall_miss_rate::total 0.243795 # miss rate for overall accesses
549 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64772.624434 # average ReadReq miss latency
550 system.cpu.icache.ReadReq_avg_miss_latency::total 64772.624434 # average ReadReq miss latency
551 system.cpu.icache.demand_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency
552 system.cpu.icache.demand_avg_miss_latency::total 64772.624434 # average overall miss latency
553 system.cpu.icache.overall_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency
554 system.cpu.icache.overall_avg_miss_latency::total 64772.624434 # average overall miss latency
555 system.cpu.icache.blocked_cycles::no_mshrs 425 # number of cycles access was blocked
556 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
557 system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
558 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
559 system.cpu.icache.avg_blocked_cycles::no_mshrs 70.833333 # average number of cycles each access was blocked
560 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
561 system.cpu.icache.fast_writes 0 # number of fast writes performed
562 system.cpu.icache.cache_copies 0 # number of cache copies performed
563 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits
564 system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
565 system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits
566 system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
567 system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits
568 system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits
569 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
570 system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
571 system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
572 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
573 system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
574 system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
575 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23362000 # number of ReadReq MSHR miss cycles
576 system.cpu.icache.ReadReq_mshr_miss_latency::total 23362000 # number of ReadReq MSHR miss cycles
577 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23362000 # number of demand (read+write) MSHR miss cycles
578 system.cpu.icache.demand_mshr_miss_latency::total 23362000 # number of demand (read+write) MSHR miss cycles
579 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23362000 # number of overall MSHR miss cycles
580 system.cpu.icache.overall_mshr_miss_latency::total 23362000 # number of overall MSHR miss cycles
581 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses
582 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses
583 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses
584 system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses
585 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses
586 system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses
587 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66558.404558 # average ReadReq mshr miss latency
588 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66558.404558 # average ReadReq mshr miss latency
589 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency
590 system.cpu.icache.demand_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency
591 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency
592 system.cpu.icache.overall_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency
593 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
594 system.cpu.l2cache.replacements 0 # number of replacements
595 system.cpu.l2cache.tagsinuse 197.575721 # Cycle average of tags in use
596 system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks.
597 system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
598 system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks.
599 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
600 system.cpu.l2cache.occ_blocks::cpu.inst 166.296629 # Average occupied blocks per requestor
601 system.cpu.l2cache.occ_blocks::cpu.data 31.279092 # Average occupied blocks per requestor
602 system.cpu.l2cache.occ_percent::cpu.inst 0.005075 # Average percentage of cache occupancy
603 system.cpu.l2cache.occ_percent::cpu.data 0.000955 # Average percentage of cache occupancy
604 system.cpu.l2cache.occ_percent::total 0.006030 # Average percentage of cache occupancy
605 system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
606 system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
607 system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
608 system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits
609 system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
610 system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits
611 system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits
612 system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
613 system.cpu.l2cache.overall_hits::total 7 # number of overall hits
614 system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses
615 system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
616 system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses
617 system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
618 system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
619 system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses
620 system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
621 system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
622 system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
623 system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
624 system.cpu.l2cache.overall_misses::total 446 # number of overall misses
625 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22950500 # number of ReadReq miss cycles
626 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4123000 # number of ReadReq miss cycles
627 system.cpu.l2cache.ReadReq_miss_latency::total 27073500 # number of ReadReq miss cycles
628 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627500 # number of ReadExReq miss cycles
629 system.cpu.l2cache.ReadExReq_miss_latency::total 3627500 # number of ReadExReq miss cycles
630 system.cpu.l2cache.demand_miss_latency::cpu.inst 22950500 # number of demand (read+write) miss cycles
631 system.cpu.l2cache.demand_miss_latency::cpu.data 7750500 # number of demand (read+write) miss cycles
632 system.cpu.l2cache.demand_miss_latency::total 30701000 # number of demand (read+write) miss cycles
633 system.cpu.l2cache.overall_miss_latency::cpu.inst 22950500 # number of overall miss cycles
634 system.cpu.l2cache.overall_miss_latency::cpu.data 7750500 # number of overall miss cycles
635 system.cpu.l2cache.overall_miss_latency::total 30701000 # number of overall miss cycles
636 system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
637 system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
638 system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
639 system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
640 system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
641 system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses
642 system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
643 system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses
644 system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses
645 system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
646 system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses
647 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982906 # miss rate for ReadReq accesses
648 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses
649 system.cpu.l2cache.ReadReq_miss_rate::total 0.982759 # miss rate for ReadReq accesses
650 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
651 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
652 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses
653 system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses
654 system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses
655 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
656 system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
657 system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
658 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66523.188406 # average ReadReq miss latency
659 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76351.851852 # average ReadReq miss latency
660 system.cpu.l2cache.ReadReq_avg_miss_latency::total 67853.383459 # average ReadReq miss latency
661 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77180.851064 # average ReadExReq miss latency
662 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77180.851064 # average ReadExReq miss latency
663 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency
664 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency
665 system.cpu.l2cache.demand_avg_miss_latency::total 68836.322870 # average overall miss latency
666 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency
667 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency
668 system.cpu.l2cache.overall_avg_miss_latency::total 68836.322870 # average overall miss latency
669 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
670 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
671 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
672 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
673 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
674 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
675 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
676 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
677 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses
678 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
679 system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses
680 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
681 system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
682 system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses
683 system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
684 system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
685 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
686 system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
687 system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
688 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18670000 # number of ReadReq MSHR miss cycles
689 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463750 # number of ReadReq MSHR miss cycles
690 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22133750 # number of ReadReq MSHR miss cycles
691 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3054750 # number of ReadExReq MSHR miss cycles
692 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3054750 # number of ReadExReq MSHR miss cycles
693 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18670000 # number of demand (read+write) MSHR miss cycles
694 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6518500 # number of demand (read+write) MSHR miss cycles
695 system.cpu.l2cache.demand_mshr_miss_latency::total 25188500 # number of demand (read+write) MSHR miss cycles
696 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18670000 # number of overall MSHR miss cycles
697 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6518500 # number of overall MSHR miss cycles
698 system.cpu.l2cache.overall_mshr_miss_latency::total 25188500 # number of overall MSHR miss cycles
699 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
700 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
701 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
702 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
703 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
704 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses
705 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses
706 system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses
707 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
708 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
709 system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
710 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54115.942029 # average ReadReq mshr miss latency
711 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64143.518519 # average ReadReq mshr miss latency
712 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55473.057644 # average ReadReq mshr miss latency
713 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64994.680851 # average ReadExReq mshr miss latency
714 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64994.680851 # average ReadExReq mshr miss latency
715 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency
716 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency
717 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency
718 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency
719 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency
720 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency
721 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
722 system.cpu.dcache.replacements 0 # number of replacements
723 system.cpu.dcache.tagsinuse 63.158434 # Cycle average of tags in use
724 system.cpu.dcache.total_refs 2188 # Total number of references to valid blocks.
725 system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.
726 system.cpu.dcache.avg_refs 21.450980 # Average number of references to valid blocks.
727 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
728 system.cpu.dcache.occ_blocks::cpu.data 63.158434 # Average occupied blocks per requestor
729 system.cpu.dcache.occ_percent::cpu.data 0.015420 # Average percentage of cache occupancy
730 system.cpu.dcache.occ_percent::total 0.015420 # Average percentage of cache occupancy
731 system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
732 system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits
733 system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
734 system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
735 system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits
736 system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits
737 system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits
738 system.cpu.dcache.overall_hits::total 2188 # number of overall hits
739 system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
740 system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses
741 system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses
742 system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses
743 system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses
744 system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
745 system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
746 system.cpu.dcache.overall_misses::total 435 # number of overall misses
747 system.cpu.dcache.ReadReq_miss_latency::cpu.data 7358500 # number of ReadReq miss cycles
748 system.cpu.dcache.ReadReq_miss_latency::total 7358500 # number of ReadReq miss cycles
749 system.cpu.dcache.WriteReq_miss_latency::cpu.data 19767997 # number of WriteReq miss cycles
750 system.cpu.dcache.WriteReq_miss_latency::total 19767997 # number of WriteReq miss cycles
751 system.cpu.dcache.demand_miss_latency::cpu.data 27126497 # number of demand (read+write) miss cycles
752 system.cpu.dcache.demand_miss_latency::total 27126497 # number of demand (read+write) miss cycles
753 system.cpu.dcache.overall_miss_latency::cpu.data 27126497 # number of overall miss cycles
754 system.cpu.dcache.overall_miss_latency::total 27126497 # number of overall miss cycles
755 system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses)
756 system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses)
757 system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
758 system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
759 system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses
760 system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses
761 system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses
762 system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses
763 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses
764 system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses
765 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses
766 system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses
767 system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses
768 system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses
769 system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses
770 system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses
771 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.807692 # average ReadReq miss latency
772 system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.807692 # average ReadReq miss latency
773 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59722.045317 # average WriteReq miss latency
774 system.cpu.dcache.WriteReq_avg_miss_latency::total 59722.045317 # average WriteReq miss latency
775 system.cpu.dcache.demand_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency
776 system.cpu.dcache.demand_avg_miss_latency::total 62359.763218 # average overall miss latency
777 system.cpu.dcache.overall_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency
778 system.cpu.dcache.overall_avg_miss_latency::total 62359.763218 # average overall miss latency
779 system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked
780 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
781 system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
782 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
783 system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked
784 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
785 system.cpu.dcache.fast_writes 0 # number of fast writes performed
786 system.cpu.dcache.cache_copies 0 # number of cache copies performed
787 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
788 system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
789 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
790 system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
791 system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
792 system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
793 system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
794 system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
795 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
796 system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
797 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
798 system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
799 system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
800 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
801 system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
802 system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
803 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4188500 # number of ReadReq MSHR miss cycles
804 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4188500 # number of ReadReq MSHR miss cycles
805 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676999 # number of WriteReq MSHR miss cycles
806 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676999 # number of WriteReq MSHR miss cycles
807 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7865499 # number of demand (read+write) MSHR miss cycles
808 system.cpu.dcache.demand_mshr_miss_latency::total 7865499 # number of demand (read+write) MSHR miss cycles
809 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7865499 # number of overall MSHR miss cycles
810 system.cpu.dcache.overall_mshr_miss_latency::total 7865499 # number of overall MSHR miss cycles
811 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses
812 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses
813 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
814 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
815 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses
816 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses
817 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses
818 system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses
819 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency
820 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76154.545455 # average ReadReq mshr miss latency
821 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78234.021277 # average WriteReq mshr miss latency
822 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78234.021277 # average WriteReq mshr miss latency
823 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency
824 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency
825 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency
826 system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency
827 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
829 ---------- End Simulation Statistics ----------
projects / gem5.git / blob