2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000012 # Number of seconds simulated
4 sim_ticks 11763500 # Number of ticks simulated
5 final_tick 11763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 53396 # Simulator instruction rate (inst/s)
8 host_op_rate 53387 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 108411505 # Simulator tick rate (ticks/s)
10 host_mem_usage 219412 # Number of bytes of host memory used
11 host_seconds 0.11 # Real time elapsed on the host
12 sim_insts 5792 # Number of instructions simulated
13 sim_ops 5792 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 28928 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 452 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1909635738 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 549496323 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 2459132061 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1909635738 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1909635738 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1909635738 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 549496323 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 2459132061 # Total bandwidth to/from this memory (bytes/s)
30 system.cpu.dtb.read_hits 0 # DTB read hits
31 system.cpu.dtb.read_misses 0 # DTB read misses
32 system.cpu.dtb.read_accesses 0 # DTB read accesses
33 system.cpu.dtb.write_hits 0 # DTB write hits
34 system.cpu.dtb.write_misses 0 # DTB write misses
35 system.cpu.dtb.write_accesses 0 # DTB write accesses
36 system.cpu.dtb.hits 0 # DTB hits
37 system.cpu.dtb.misses 0 # DTB misses
38 system.cpu.dtb.accesses 0 # DTB accesses
39 system.cpu.itb.read_hits 0 # DTB read hits
40 system.cpu.itb.read_misses 0 # DTB read misses
41 system.cpu.itb.read_accesses 0 # DTB read accesses
42 system.cpu.itb.write_hits 0 # DTB write hits
43 system.cpu.itb.write_misses 0 # DTB write misses
44 system.cpu.itb.write_accesses 0 # DTB write accesses
45 system.cpu.itb.hits 0 # DTB hits
46 system.cpu.itb.misses 0 # DTB misses
47 system.cpu.itb.accesses 0 # DTB accesses
48 system.cpu.workload.num_syscalls 9 # Number of system calls
49 system.cpu.numCycles 23528 # number of cpu cycles simulated
50 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
51 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
52 system.cpu.BPredUnit.lookups 2457 # Number of BP lookups
53 system.cpu.BPredUnit.condPredicted 2014 # Number of conditional branches predicted
54 system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect
55 system.cpu.BPredUnit.BTBLookups 2037 # Number of BTB lookups
56 system.cpu.BPredUnit.BTBHits 618 # Number of BTB hits
57 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
58 system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
59 system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.
60 system.cpu.fetch.icacheStallCycles 7380 # Number of cycles fetch is stalled on an Icache miss
61 system.cpu.fetch.Insts 14306 # Number of instructions fetch has processed
62 system.cpu.fetch.Branches 2457 # Number of branches that fetch encountered
63 system.cpu.fetch.predictedBranches 778 # Number of branches that fetch has predicted taken
64 system.cpu.fetch.Cycles 2377 # Number of cycles fetch has run and was not squashing or blocked
65 system.cpu.fetch.SquashCycles 1402 # Number of cycles fetch has spent squashing
66 system.cpu.fetch.BlockedCycles 936 # Number of cycles fetch has spent blocked
67 system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
68 system.cpu.fetch.CacheLines 1859 # Number of cache lines fetched
69 system.cpu.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed
70 system.cpu.fetch.rateDist::samples 11638 # Number of instructions fetched each cycle (Total)
71 system.cpu.fetch.rateDist::mean 1.229249 # Number of instructions fetched each cycle (Total)
72 system.cpu.fetch.rateDist::stdev 2.662964 # Number of instructions fetched each cycle (Total)
73 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
74 system.cpu.fetch.rateDist::0 9261 79.58% 79.58% # Number of instructions fetched each cycle (Total)
75 system.cpu.fetch.rateDist::1 173 1.49% 81.06% # Number of instructions fetched each cycle (Total)
76 system.cpu.fetch.rateDist::2 162 1.39% 82.45% # Number of instructions fetched each cycle (Total)
77 system.cpu.fetch.rateDist::3 137 1.18% 83.63% # Number of instructions fetched each cycle (Total)
78 system.cpu.fetch.rateDist::4 198 1.70% 85.33% # Number of instructions fetched each cycle (Total)
79 system.cpu.fetch.rateDist::5 148 1.27% 86.60% # Number of instructions fetched each cycle (Total)
80 system.cpu.fetch.rateDist::6 250 2.15% 88.75% # Number of instructions fetched each cycle (Total)
81 system.cpu.fetch.rateDist::7 106 0.91% 89.66% # Number of instructions fetched each cycle (Total)
82 system.cpu.fetch.rateDist::8 1203 10.34% 100.00% # Number of instructions fetched each cycle (Total)
83 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
84 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
85 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::total 11638 # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.branchRate 0.104429 # Number of branch fetches per cycle
88 system.cpu.fetch.rate 0.608041 # Number of inst fetches per cycle
89 system.cpu.decode.IdleCycles 7505 # Number of cycles decode is idle
90 system.cpu.decode.BlockedCycles 1074 # Number of cycles decode is blocked
91 system.cpu.decode.RunCycles 2213 # Number of cycles decode is running
92 system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking
93 system.cpu.decode.SquashCycles 784 # Number of cycles decode is squashing
94 system.cpu.decode.BranchResolved 351 # Number of times decode resolved a branch
95 system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
96 system.cpu.decode.DecodedInsts 12646 # Number of instructions handled by decode
97 system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode
98 system.cpu.rename.SquashCycles 784 # Number of cycles rename is squashing
99 system.cpu.rename.IdleCycles 7717 # Number of cycles rename is idle
100 system.cpu.rename.BlockCycles 446 # Number of cycles rename is blocking
101 system.cpu.rename.serializeStallCycles 386 # count of cycles rename stalled for serializing inst
102 system.cpu.rename.RunCycles 2059 # Number of cycles rename is running
103 system.cpu.rename.UnblockCycles 246 # Number of cycles rename is unblocking
104 system.cpu.rename.RenamedInsts 11999 # Number of instructions processed by rename
105 system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
106 system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full
107 system.cpu.rename.RenamedOperands 10316 # Number of destination operands rename has renamed
108 system.cpu.rename.RenameLookups 19600 # Number of register rename lookups that rename has made
109 system.cpu.rename.int_rename_lookups 19545 # Number of integer rename lookups
110 system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
111 system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
112 system.cpu.rename.UndoneMaps 5318 # Number of HB maps that are undone due to squashing
113 system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
114 system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
115 system.cpu.rename.skidInsts 543 # count of insts added to the skid buffer
116 system.cpu.memDep0.insertedLoads 2051 # Number of loads inserted to the mem dependence unit.
117 system.cpu.memDep0.insertedStores 1909 # Number of stores inserted to the mem dependence unit.
118 system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads.
119 system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores.
120 system.cpu.iq.iqInstsAdded 10820 # Number of instructions added to the IQ (excludes non-spec)
121 system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
122 system.cpu.iq.iqInstsIssued 9196 # Number of instructions issued
123 system.cpu.iq.iqSquashedInstsIssued 160 # Number of squashed instructions issued
124 system.cpu.iq.iqSquashedInstsExamined 4794 # Number of squashed instructions iterated over during squash; mainly for profiling
125 system.cpu.iq.iqSquashedOperandsExamined 4145 # Number of squashed operands that are examined and possibly removed from graph
126 system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed
127 system.cpu.iq.issued_per_cycle::samples 11638 # Number of insts issued each cycle
128 system.cpu.iq.issued_per_cycle::mean 0.790170 # Number of insts issued each cycle
129 system.cpu.iq.issued_per_cycle::stdev 1.525459 # Number of insts issued each cycle
130 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
131 system.cpu.iq.issued_per_cycle::0 8215 70.59% 70.59% # Number of insts issued each cycle
132 system.cpu.iq.issued_per_cycle::1 1109 9.53% 80.12% # Number of insts issued each cycle
133 system.cpu.iq.issued_per_cycle::2 778 6.68% 86.80% # Number of insts issued each cycle
134 system.cpu.iq.issued_per_cycle::3 515 4.43% 91.23% # Number of insts issued each cycle
135 system.cpu.iq.issued_per_cycle::4 472 4.06% 95.28% # Number of insts issued each cycle
136 system.cpu.iq.issued_per_cycle::5 322 2.77% 98.05% # Number of insts issued each cycle
137 system.cpu.iq.issued_per_cycle::6 140 1.20% 99.25% # Number of insts issued each cycle
138 system.cpu.iq.issued_per_cycle::7 48 0.41% 99.66% # Number of insts issued each cycle
139 system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle
140 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
141 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
142 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::total 11638 # Number of insts issued each cycle
144 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
145 system.cpu.iq.fu_full::IntAlu 4 2.34% 2.34% # attempts to use FU when none available
146 system.cpu.iq.fu_full::IntMult 0 0.00% 2.34% # attempts to use FU when none available
147 system.cpu.iq.fu_full::IntDiv 0 0.00% 2.34% # attempts to use FU when none available
148 system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.34% # attempts to use FU when none available
149 system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.34% # attempts to use FU when none available
150 system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.34% # attempts to use FU when none available
151 system.cpu.iq.fu_full::FloatMult 0 0.00% 2.34% # attempts to use FU when none available
152 system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.34% # attempts to use FU when none available
153 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.34% # attempts to use FU when none available
154 system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.34% # attempts to use FU when none available
155 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.34% # attempts to use FU when none available
156 system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.34% # attempts to use FU when none available
157 system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.34% # attempts to use FU when none available
158 system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.34% # attempts to use FU when none available
159 system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.34% # attempts to use FU when none available
160 system.cpu.iq.fu_full::SimdMult 0 0.00% 2.34% # attempts to use FU when none available
161 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.34% # attempts to use FU when none available
162 system.cpu.iq.fu_full::SimdShift 0 0.00% 2.34% # attempts to use FU when none available
163 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.34% # attempts to use FU when none available
164 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.34% # attempts to use FU when none available
165 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.34% # attempts to use FU when none available
166 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.34% # attempts to use FU when none available
167 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.34% # attempts to use FU when none available
168 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.34% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.34% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.34% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.34% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.34% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.34% # attempts to use FU when none available
174 system.cpu.iq.fu_full::MemRead 75 43.86% 46.20% # attempts to use FU when none available
175 system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available
176 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
177 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
178 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
179 system.cpu.iq.FU_type_0::IntAlu 5661 61.56% 61.56% # Type of FU issued
180 system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.56% # Type of FU issued
181 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued
182 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.58% # Type of FU issued
183 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.58% # Type of FU issued
184 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.58% # Type of FU issued
185 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.58% # Type of FU issued
186 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.58% # Type of FU issued
187 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.58% # Type of FU issued
188 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.58% # Type of FU issued
189 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.58% # Type of FU issued
190 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.58% # Type of FU issued
191 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.58% # Type of FU issued
192 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.58% # Type of FU issued
193 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.58% # Type of FU issued
194 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.58% # Type of FU issued
195 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.58% # Type of FU issued
196 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.58% # Type of FU issued
197 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.58% # Type of FU issued
198 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.58% # Type of FU issued
199 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.58% # Type of FU issued
200 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.58% # Type of FU issued
201 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.58% # Type of FU issued
202 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.58% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.58% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.58% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.58% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.58% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.58% # Type of FU issued
208 system.cpu.iq.FU_type_0::MemRead 1833 19.93% 81.51% # Type of FU issued
209 system.cpu.iq.FU_type_0::MemWrite 1700 18.49% 100.00% # Type of FU issued
210 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
211 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
212 system.cpu.iq.FU_type_0::total 9196 # Type of FU issued
213 system.cpu.iq.rate 0.390853 # Inst issue rate
214 system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
215 system.cpu.iq.fu_busy_rate 0.018595 # FU busy rate (busy events/executed inst)
216 system.cpu.iq.int_inst_queue_reads 30299 # Number of integer instruction queue reads
217 system.cpu.iq.int_inst_queue_writes 15649 # Number of integer instruction queue writes
218 system.cpu.iq.int_inst_queue_wakeup_accesses 8318 # Number of integer instruction queue wakeup accesses
219 system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
220 system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
221 system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
222 system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses
223 system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
224 system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
225 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
226 system.cpu.iew.lsq.thread0.squashedLoads 1090 # Number of loads squashed
227 system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
228 system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
229 system.cpu.iew.lsq.thread0.squashedStores 863 # Number of stores squashed
230 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
231 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
232 system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
233 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
234 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
235 system.cpu.iew.iewSquashCycles 784 # Number of cycles IEW is squashing
236 system.cpu.iew.iewBlockCycles 229 # Number of cycles IEW is blocking
237 system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
238 system.cpu.iew.iewDispatchedInsts 10884 # Number of instructions dispatched to IQ
239 system.cpu.iew.iewDispSquashedInsts 101 # Number of squashed instructions skipped by dispatch
240 system.cpu.iew.iewDispLoadInsts 2051 # Number of dispatched load instructions
241 system.cpu.iew.iewDispStoreInsts 1909 # Number of dispatched store instructions
242 system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
243 system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall
244 system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
245 system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
246 system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly
247 system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly
248 system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute
249 system.cpu.iew.iewExecutedInsts 8699 # Number of executed instructions
250 system.cpu.iew.iewExecLoadInsts 1698 # Number of load instructions executed
251 system.cpu.iew.iewExecSquashedInsts 497 # Number of squashed instructions skipped in execute
252 system.cpu.iew.exec_swp 0 # number of swp insts executed
253 system.cpu.iew.exec_nop 0 # number of nop insts executed
254 system.cpu.iew.exec_refs 3253 # number of memory reference insts executed
255 system.cpu.iew.exec_branches 1376 # Number of branches executed
256 system.cpu.iew.exec_stores 1555 # Number of stores executed
257 system.cpu.iew.exec_rate 0.369730 # Inst execution rate
258 system.cpu.iew.wb_sent 8502 # cumulative count of insts sent to commit
259 system.cpu.iew.wb_count 8345 # cumulative count of insts written-back
260 system.cpu.iew.wb_producers 4327 # num instructions producing a value
261 system.cpu.iew.wb_consumers 6939 # num instructions consuming a value
262 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
263 system.cpu.iew.wb_rate 0.354684 # insts written-back per cycle
264 system.cpu.iew.wb_fanout 0.623577 # average fanout of values written-back
265 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
266 system.cpu.commit.commitSquashedInsts 5101 # The number of squashed insts skipped by commit
267 system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
268 system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted
269 system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle
270 system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle
271 system.cpu.commit.committed_per_cycle::stdev 1.316329 # Number of insts commited each cycle
272 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
273 system.cpu.commit.committed_per_cycle::0 8424 77.61% 77.61% # Number of insts commited each cycle
274 system.cpu.commit.committed_per_cycle::1 1042 9.60% 87.21% # Number of insts commited each cycle
275 system.cpu.commit.committed_per_cycle::2 639 5.89% 93.10% # Number of insts commited each cycle
276 system.cpu.commit.committed_per_cycle::3 261 2.40% 95.50% # Number of insts commited each cycle
277 system.cpu.commit.committed_per_cycle::4 182 1.68% 97.18% # Number of insts commited each cycle
278 system.cpu.commit.committed_per_cycle::5 104 0.96% 98.14% # Number of insts commited each cycle
279 system.cpu.commit.committed_per_cycle::6 67 0.62% 98.76% # Number of insts commited each cycle
280 system.cpu.commit.committed_per_cycle::7 41 0.38% 99.13% # Number of insts commited each cycle
281 system.cpu.commit.committed_per_cycle::8 94 0.87% 100.00% # Number of insts commited each cycle
282 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
283 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
284 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
285 system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle
286 system.cpu.commit.committedInsts 5792 # Number of instructions committed
287 system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
288 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
289 system.cpu.commit.refs 2007 # Number of memory references committed
290 system.cpu.commit.loads 961 # Number of loads committed
291 system.cpu.commit.membars 7 # Number of memory barriers committed
292 system.cpu.commit.branches 1037 # Number of branches committed
293 system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
294 system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
295 system.cpu.commit.function_calls 103 # Number of function calls committed.
296 system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached
297 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
298 system.cpu.rob.rob_reads 21653 # The number of ROB reads
299 system.cpu.rob.rob_writes 22571 # The number of ROB writes
300 system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself
301 system.cpu.idleCycles 11890 # Total number of cycles that the CPU has spent unscheduled due to idling
302 system.cpu.committedInsts 5792 # Number of Instructions Simulated
303 system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
304 system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
305 system.cpu.cpi 4.062155 # CPI: Cycles Per Instruction
306 system.cpu.cpi_total 4.062155 # CPI: Total CPI of All Threads
307 system.cpu.ipc 0.246175 # IPC: Instructions Per Cycle
308 system.cpu.ipc_total 0.246175 # IPC: Total IPC of All Threads
309 system.cpu.int_regfile_reads 13809 # number of integer regfile reads
310 system.cpu.int_regfile_writes 7224 # number of integer regfile writes
311 system.cpu.fp_regfile_reads 25 # number of floating regfile reads
312 system.cpu.fp_regfile_writes 2 # number of floating regfile writes
313 system.cpu.icache.replacements 0 # number of replacements
314 system.cpu.icache.tagsinuse 172.502715 # Cycle average of tags in use
315 system.cpu.icache.total_refs 1427 # Total number of references to valid blocks.
316 system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks.
317 system.cpu.icache.avg_refs 4.008427 # Average number of references to valid blocks.
318 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
319 system.cpu.icache.occ_blocks::cpu.inst 172.502715 # Average occupied blocks per requestor
320 system.cpu.icache.occ_percent::cpu.inst 0.084230 # Average percentage of cache occupancy
321 system.cpu.icache.occ_percent::total 0.084230 # Average percentage of cache occupancy
322 system.cpu.icache.ReadReq_hits::cpu.inst 1427 # number of ReadReq hits
323 system.cpu.icache.ReadReq_hits::total 1427 # number of ReadReq hits
324 system.cpu.icache.demand_hits::cpu.inst 1427 # number of demand (read+write) hits
325 system.cpu.icache.demand_hits::total 1427 # number of demand (read+write) hits
326 system.cpu.icache.overall_hits::cpu.inst 1427 # number of overall hits
327 system.cpu.icache.overall_hits::total 1427 # number of overall hits
328 system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses
329 system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses
330 system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses
331 system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
332 system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
333 system.cpu.icache.overall_misses::total 432 # number of overall misses
334 system.cpu.icache.ReadReq_miss_latency::cpu.inst 16299000 # number of ReadReq miss cycles
335 system.cpu.icache.ReadReq_miss_latency::total 16299000 # number of ReadReq miss cycles
336 system.cpu.icache.demand_miss_latency::cpu.inst 16299000 # number of demand (read+write) miss cycles
337 system.cpu.icache.demand_miss_latency::total 16299000 # number of demand (read+write) miss cycles
338 system.cpu.icache.overall_miss_latency::cpu.inst 16299000 # number of overall miss cycles
339 system.cpu.icache.overall_miss_latency::total 16299000 # number of overall miss cycles
340 system.cpu.icache.ReadReq_accesses::cpu.inst 1859 # number of ReadReq accesses(hits+misses)
341 system.cpu.icache.ReadReq_accesses::total 1859 # number of ReadReq accesses(hits+misses)
342 system.cpu.icache.demand_accesses::cpu.inst 1859 # number of demand (read+write) accesses
343 system.cpu.icache.demand_accesses::total 1859 # number of demand (read+write) accesses
344 system.cpu.icache.overall_accesses::cpu.inst 1859 # number of overall (read+write) accesses
345 system.cpu.icache.overall_accesses::total 1859 # number of overall (read+write) accesses
346 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232383 # miss rate for ReadReq accesses
347 system.cpu.icache.ReadReq_miss_rate::total 0.232383 # miss rate for ReadReq accesses
348 system.cpu.icache.demand_miss_rate::cpu.inst 0.232383 # miss rate for demand accesses
349 system.cpu.icache.demand_miss_rate::total 0.232383 # miss rate for demand accesses
350 system.cpu.icache.overall_miss_rate::cpu.inst 0.232383 # miss rate for overall accesses
351 system.cpu.icache.overall_miss_rate::total 0.232383 # miss rate for overall accesses
352 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37729.166667 # average ReadReq miss latency
353 system.cpu.icache.ReadReq_avg_miss_latency::total 37729.166667 # average ReadReq miss latency
354 system.cpu.icache.demand_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency
355 system.cpu.icache.demand_avg_miss_latency::total 37729.166667 # average overall miss latency
356 system.cpu.icache.overall_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency
357 system.cpu.icache.overall_avg_miss_latency::total 37729.166667 # average overall miss latency
358 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
359 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
360 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
361 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
362 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
363 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
364 system.cpu.icache.fast_writes 0 # number of fast writes performed
365 system.cpu.icache.cache_copies 0 # number of cache copies performed
366 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 76 # number of ReadReq MSHR hits
367 system.cpu.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
368 system.cpu.icache.demand_mshr_hits::cpu.inst 76 # number of demand (read+write) MSHR hits
369 system.cpu.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
370 system.cpu.icache.overall_mshr_hits::cpu.inst 76 # number of overall MSHR hits
371 system.cpu.icache.overall_mshr_hits::total 76 # number of overall MSHR hits
372 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses
373 system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses
374 system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses
375 system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses
376 system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses
377 system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses
378 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13111000 # number of ReadReq MSHR miss cycles
379 system.cpu.icache.ReadReq_mshr_miss_latency::total 13111000 # number of ReadReq MSHR miss cycles
380 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13111000 # number of demand (read+write) MSHR miss cycles
381 system.cpu.icache.demand_mshr_miss_latency::total 13111000 # number of demand (read+write) MSHR miss cycles
382 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13111000 # number of overall MSHR miss cycles
383 system.cpu.icache.overall_mshr_miss_latency::total 13111000 # number of overall MSHR miss cycles
384 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for ReadReq accesses
385 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191501 # mshr miss rate for ReadReq accesses
386 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for demand accesses
387 system.cpu.icache.demand_mshr_miss_rate::total 0.191501 # mshr miss rate for demand accesses
388 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for overall accesses
389 system.cpu.icache.overall_mshr_miss_rate::total 0.191501 # mshr miss rate for overall accesses
390 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36828.651685 # average ReadReq mshr miss latency
391 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36828.651685 # average ReadReq mshr miss latency
392 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency
393 system.cpu.icache.demand_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency
394 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency
395 system.cpu.icache.overall_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency
396 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
397 system.cpu.dcache.replacements 0 # number of replacements
398 system.cpu.dcache.tagsinuse 63.218136 # Cycle average of tags in use
399 system.cpu.dcache.total_refs 2196 # Total number of references to valid blocks.
400 system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks.
401 system.cpu.dcache.avg_refs 21.742574 # Average number of references to valid blocks.
402 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
403 system.cpu.dcache.occ_blocks::cpu.data 63.218136 # Average occupied blocks per requestor
404 system.cpu.dcache.occ_percent::cpu.data 0.015434 # Average percentage of cache occupancy
405 system.cpu.dcache.occ_percent::total 0.015434 # Average percentage of cache occupancy
406 system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits
407 system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits
408 system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits
409 system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits
410 system.cpu.dcache.demand_hits::cpu.data 2196 # number of demand (read+write) hits
411 system.cpu.dcache.demand_hits::total 2196 # number of demand (read+write) hits
412 system.cpu.dcache.overall_hits::cpu.data 2196 # number of overall hits
413 system.cpu.dcache.overall_hits::total 2196 # number of overall hits
414 system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
415 system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses
416 system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses
417 system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses
418 system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses
419 system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses
420 system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses
421 system.cpu.dcache.overall_misses::total 420 # number of overall misses
422 system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles
423 system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles
424 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12824500 # number of WriteReq miss cycles
425 system.cpu.dcache.WriteReq_miss_latency::total 12824500 # number of WriteReq miss cycles
426 system.cpu.dcache.demand_miss_latency::cpu.data 16557000 # number of demand (read+write) miss cycles
427 system.cpu.dcache.demand_miss_latency::total 16557000 # number of demand (read+write) miss cycles
428 system.cpu.dcache.overall_miss_latency::cpu.data 16557000 # number of overall miss cycles
429 system.cpu.dcache.overall_miss_latency::total 16557000 # number of overall miss cycles
430 system.cpu.dcache.ReadReq_accesses::cpu.data 1570 # number of ReadReq accesses(hits+misses)
431 system.cpu.dcache.ReadReq_accesses::total 1570 # number of ReadReq accesses(hits+misses)
432 system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
433 system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
434 system.cpu.dcache.demand_accesses::cpu.data 2616 # number of demand (read+write) accesses
435 system.cpu.dcache.demand_accesses::total 2616 # number of demand (read+write) accesses
436 system.cpu.dcache.overall_accesses::cpu.data 2616 # number of overall (read+write) accesses
437 system.cpu.dcache.overall_accesses::total 2616 # number of overall (read+write) accesses
438 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.057962 # miss rate for ReadReq accesses
439 system.cpu.dcache.ReadReq_miss_rate::total 0.057962 # miss rate for ReadReq accesses
440 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses
441 system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses
442 system.cpu.dcache.demand_miss_rate::cpu.data 0.160550 # miss rate for demand accesses
443 system.cpu.dcache.demand_miss_rate::total 0.160550 # miss rate for demand accesses
444 system.cpu.dcache.overall_miss_rate::cpu.data 0.160550 # miss rate for overall accesses
445 system.cpu.dcache.overall_miss_rate::total 0.160550 # miss rate for overall accesses
446 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41016.483516 # average ReadReq miss latency
447 system.cpu.dcache.ReadReq_avg_miss_latency::total 41016.483516 # average ReadReq miss latency
448 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38980.243161 # average WriteReq miss latency
449 system.cpu.dcache.WriteReq_avg_miss_latency::total 38980.243161 # average WriteReq miss latency
450 system.cpu.dcache.demand_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency
451 system.cpu.dcache.demand_avg_miss_latency::total 39421.428571 # average overall miss latency
452 system.cpu.dcache.overall_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency
453 system.cpu.dcache.overall_avg_miss_latency::total 39421.428571 # average overall miss latency
454 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
455 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
456 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
457 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
458 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
459 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
460 system.cpu.dcache.fast_writes 0 # number of fast writes performed
461 system.cpu.dcache.cache_copies 0 # number of cache copies performed
462 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits
463 system.cpu.dcache.ReadReq_mshr_hits::total 37 # number of ReadReq MSHR hits
464 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 282 # number of WriteReq MSHR hits
465 system.cpu.dcache.WriteReq_mshr_hits::total 282 # number of WriteReq MSHR hits
466 system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits
467 system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits
468 system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits
469 system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits
470 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
471 system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
472 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
473 system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
474 system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
475 system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses
476 system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
477 system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses
478 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2168500 # number of ReadReq MSHR miss cycles
479 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2168500 # number of ReadReq MSHR miss cycles
480 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2086000 # number of WriteReq MSHR miss cycles
481 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086000 # number of WriteReq MSHR miss cycles
482 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4254500 # number of demand (read+write) MSHR miss cycles
483 system.cpu.dcache.demand_mshr_miss_latency::total 4254500 # number of demand (read+write) MSHR miss cycles
484 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4254500 # number of overall MSHR miss cycles
485 system.cpu.dcache.overall_mshr_miss_latency::total 4254500 # number of overall MSHR miss cycles
486 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034395 # mshr miss rate for ReadReq accesses
487 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034395 # mshr miss rate for ReadReq accesses
488 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
489 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
490 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for demand accesses
491 system.cpu.dcache.demand_mshr_miss_rate::total 0.038609 # mshr miss rate for demand accesses
492 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for overall accesses
493 system.cpu.dcache.overall_mshr_miss_rate::total 0.038609 # mshr miss rate for overall accesses
494 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40157.407407 # average ReadReq mshr miss latency
495 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40157.407407 # average ReadReq mshr miss latency
496 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44382.978723 # average WriteReq mshr miss latency
497 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44382.978723 # average WriteReq mshr miss latency
498 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency
499 system.cpu.dcache.demand_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency
500 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency
501 system.cpu.dcache.overall_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency
502 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
503 system.cpu.l2cache.replacements 0 # number of replacements
504 system.cpu.l2cache.tagsinuse 203.045072 # Cycle average of tags in use
505 system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.
506 system.cpu.l2cache.sampled_refs 405 # Sample count of references to valid blocks.
507 system.cpu.l2cache.avg_refs 0.012346 # Average number of references to valid blocks.
508 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
509 system.cpu.l2cache.occ_blocks::cpu.inst 171.614713 # Average occupied blocks per requestor
510 system.cpu.l2cache.occ_blocks::cpu.data 31.430359 # Average occupied blocks per requestor
511 system.cpu.l2cache.occ_percent::cpu.inst 0.005237 # Average percentage of cache occupancy
512 system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy
513 system.cpu.l2cache.occ_percent::total 0.006196 # Average percentage of cache occupancy
514 system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
515 system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits
516 system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
517 system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits
518 system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
519 system.cpu.l2cache.overall_hits::total 5 # number of overall hits
520 system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses
521 system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
522 system.cpu.l2cache.ReadReq_misses::total 405 # number of ReadReq misses
523 system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
524 system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
525 system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses
526 system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
527 system.cpu.l2cache.demand_misses::total 452 # number of demand (read+write) misses
528 system.cpu.l2cache.overall_misses::cpu.inst 351 # number of overall misses
529 system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
530 system.cpu.l2cache.overall_misses::total 452 # number of overall misses
531 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12737500 # number of ReadReq miss cycles
532 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2108500 # number of ReadReq miss cycles
533 system.cpu.l2cache.ReadReq_miss_latency::total 14846000 # number of ReadReq miss cycles
534 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2028500 # number of ReadExReq miss cycles
535 system.cpu.l2cache.ReadExReq_miss_latency::total 2028500 # number of ReadExReq miss cycles
536 system.cpu.l2cache.demand_miss_latency::cpu.inst 12737500 # number of demand (read+write) miss cycles
537 system.cpu.l2cache.demand_miss_latency::cpu.data 4137000 # number of demand (read+write) miss cycles
538 system.cpu.l2cache.demand_miss_latency::total 16874500 # number of demand (read+write) miss cycles
539 system.cpu.l2cache.overall_miss_latency::cpu.inst 12737500 # number of overall miss cycles
540 system.cpu.l2cache.overall_miss_latency::cpu.data 4137000 # number of overall miss cycles
541 system.cpu.l2cache.overall_miss_latency::total 16874500 # number of overall miss cycles
542 system.cpu.l2cache.ReadReq_accesses::cpu.inst 356 # number of ReadReq accesses(hits+misses)
543 system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
544 system.cpu.l2cache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses)
545 system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
546 system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
547 system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses
548 system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses
549 system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
550 system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses
551 system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses
552 system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
553 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses
554 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
555 system.cpu.l2cache.ReadReq_miss_rate::total 0.987805 # miss rate for ReadReq accesses
556 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
557 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
558 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses
559 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
560 system.cpu.l2cache.demand_miss_rate::total 0.989059 # miss rate for demand accesses
561 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses
562 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
563 system.cpu.l2cache.overall_miss_rate::total 0.989059 # miss rate for overall accesses
564 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36289.173789 # average ReadReq miss latency
565 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39046.296296 # average ReadReq miss latency
566 system.cpu.l2cache.ReadReq_avg_miss_latency::total 36656.790123 # average ReadReq miss latency
567 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43159.574468 # average ReadExReq miss latency
568 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43159.574468 # average ReadExReq miss latency
569 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency
570 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency
571 system.cpu.l2cache.demand_avg_miss_latency::total 37332.964602 # average overall miss latency
572 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency
573 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency
574 system.cpu.l2cache.overall_avg_miss_latency::total 37332.964602 # average overall miss latency
575 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
576 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
577 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
578 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
579 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
580 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
581 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
582 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
583 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
584 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
585 system.cpu.l2cache.ReadReq_mshr_misses::total 405 # number of ReadReq MSHR misses
586 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
587 system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
588 system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
589 system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
590 system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses
591 system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
592 system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
593 system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses
594 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11613500 # number of ReadReq MSHR miss cycles
595 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1942500 # number of ReadReq MSHR miss cycles
596 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13556000 # number of ReadReq MSHR miss cycles
597 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1882000 # number of ReadExReq MSHR miss cycles
598 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1882000 # number of ReadExReq MSHR miss cycles
599 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11613500 # number of demand (read+write) MSHR miss cycles
600 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3824500 # number of demand (read+write) MSHR miss cycles
601 system.cpu.l2cache.demand_mshr_miss_latency::total 15438000 # number of demand (read+write) MSHR miss cycles
602 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11613500 # number of overall MSHR miss cycles
603 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3824500 # number of overall MSHR miss cycles
604 system.cpu.l2cache.overall_mshr_miss_latency::total 15438000 # number of overall MSHR miss cycles
605 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses
606 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
607 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses
608 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
609 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
610 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses
611 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
612 system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses
613 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses
614 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
615 system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses
616 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33086.894587 # average ReadReq mshr miss latency
617 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35972.222222 # average ReadReq mshr miss latency
618 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33471.604938 # average ReadReq mshr miss latency
619 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40042.553191 # average ReadExReq mshr miss latency
620 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40042.553191 # average ReadExReq mshr miss latency
621 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency
622 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency
623 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency
624 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency
625 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency
626 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency
627 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
629 ---------- End Simulation Statistics ----------
projects / gem5.git / blob