2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000003 # Number of seconds simulated
4 sim_ticks 2900000 # Number of ticks simulated
5 final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 305071 # Simulator instruction rate (inst/s)
8 host_tick_rate 152367478 # Simulator tick rate (ticks/s)
9 host_mem_usage 196296 # Number of bytes of host memory used
10 host_seconds 0.02 # Real time elapsed on the host
11 sim_insts 5801 # Number of instructions simulated
12 system.physmem.bytes_read 26925 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 4209 # Number of bytes written to this memory
15 system.physmem.num_reads 6763 # Number of read requests responded to by this memory
16 system.physmem.num_writes 1046 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 9284482759 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 8001379310 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 1451379310 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 10735862069 # Total bandwidth to/from this memory (bytes/s)
22 system.cpu.dtb.read_hits 0 # DTB read hits
23 system.cpu.dtb.read_misses 0 # DTB read misses
24 system.cpu.dtb.read_accesses 0 # DTB read accesses
25 system.cpu.dtb.write_hits 0 # DTB write hits
26 system.cpu.dtb.write_misses 0 # DTB write misses
27 system.cpu.dtb.write_accesses 0 # DTB write accesses
28 system.cpu.dtb.hits 0 # DTB hits
29 system.cpu.dtb.misses 0 # DTB misses
30 system.cpu.dtb.accesses 0 # DTB accesses
31 system.cpu.itb.read_hits 0 # DTB read hits
32 system.cpu.itb.read_misses 0 # DTB read misses
33 system.cpu.itb.read_accesses 0 # DTB read accesses
34 system.cpu.itb.write_hits 0 # DTB write hits
35 system.cpu.itb.write_misses 0 # DTB write misses
36 system.cpu.itb.write_accesses 0 # DTB write accesses
37 system.cpu.itb.hits 0 # DTB hits
38 system.cpu.itb.misses 0 # DTB misses
39 system.cpu.itb.accesses 0 # DTB accesses
40 system.cpu.workload.num_syscalls 9 # Number of system calls
41 system.cpu.numCycles 5801 # number of cpu cycles simulated
42 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
43 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
44 system.cpu.num_insts 5801 # Number of instructions executed
45 system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses
46 system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses
47 system.cpu.num_func_calls 200 # number of times a function call or return occured
48 system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls
49 system.cpu.num_int_insts 5706 # number of integer instructions
50 system.cpu.num_fp_insts 22 # number of float instructions
51 system.cpu.num_int_register_reads 9541 # number of times the integer registers were read
52 system.cpu.num_int_register_writes 5005 # number of times the integer registers were written
53 system.cpu.num_fp_register_reads 20 # number of times the floating registers were read
54 system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
55 system.cpu.num_mem_refs 2008 # number of memory refs
56 system.cpu.num_load_insts 962 # Number of load instructions
57 system.cpu.num_store_insts 1046 # Number of store instructions
58 system.cpu.num_idle_cycles 0 # Number of idle cycles
59 system.cpu.num_busy_cycles 5801 # Number of busy cycles
60 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
61 system.cpu.idle_fraction 0 # Percentage of idle cycles
63 ---------- End Simulation Statistics ----------
projects / gem5.git / blob