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[gem5.git] / tests / quick / se / 00.hello / ref / riscv / linux / minor-timing / config.json
1 {
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "membus": {
9 "point_of_coherency": true,
10 "system": "system",
11 "response_latency": 2,
12 "cxx_class": "CoherentXBar",
13 "forward_latency": 4,
14 "clk_domain": "system.clk_domain",
15 "width": 16,
16 "eventq_index": 0,
17 "default_p_state": "UNDEFINED",
18 "p_state_clk_gate_max": 1000000000000,
19 "master": {
20 "peer": [
21 "system.physmem.port"
22 ],
23 "role": "MASTER"
24 },
25 "type": "CoherentXBar",
26 "frontend_latency": 3,
27 "slave": {
28 "peer": [
29 "system.system_port",
30 "system.cpu.l2cache.mem_side"
31 ],
32 "role": "SLAVE"
33 },
34 "p_state_clk_gate_min": 1000,
35 "snoop_filter": {
36 "name": "snoop_filter",
37 "system": "system",
38 "max_capacity": 8388608,
39 "eventq_index": 0,
40 "cxx_class": "SnoopFilter",
41 "path": "system.membus.snoop_filter",
42 "type": "SnoopFilter",
43 "lookup_latency": 1
44 },
45 "power_model": null,
46 "path": "system.membus",
47 "snoop_response_latency": 4,
48 "name": "membus",
49 "p_state_clk_gate_bins": 20,
50 "use_default_range": false
51 },
52 "symbolfile": "",
53 "readfile": "",
54 "thermal_model": null,
55 "cxx_class": "System",
56 "work_begin_cpu_id_exit": -1,
57 "load_offset": 0,
58 "work_begin_exit_count": 0,
59 "p_state_clk_gate_min": 1000,
60 "memories": [
61 "system.physmem"
62 ],
63 "work_begin_ckpt_count": 0,
64 "clk_domain": {
65 "name": "clk_domain",
66 "clock": [
67 1000
68 ],
69 "init_perf_level": 0,
70 "voltage_domain": "system.voltage_domain",
71 "eventq_index": 0,
72 "cxx_class": "SrcClockDomain",
73 "path": "system.clk_domain",
74 "type": "SrcClockDomain",
75 "domain_id": -1
76 },
77 "mem_ranges": [],
78 "eventq_index": 0,
79 "default_p_state": "UNDEFINED",
80 "p_state_clk_gate_max": 1000000000000,
81 "dvfs_handler": {
82 "enable": false,
83 "name": "dvfs_handler",
84 "sys_clk_domain": "system.clk_domain",
85 "transition_latency": 100000000,
86 "eventq_index": 0,
87 "cxx_class": "DVFSHandler",
88 "domains": [],
89 "path": "system.dvfs_handler",
90 "type": "DVFSHandler"
91 },
92 "work_end_exit_count": 0,
93 "type": "System",
94 "voltage_domain": {
95 "name": "voltage_domain",
96 "eventq_index": 0,
97 "voltage": [
98 "1.0"
99 ],
100 "cxx_class": "VoltageDomain",
101 "path": "system.voltage_domain",
102 "type": "VoltageDomain"
103 },
104 "cache_line_size": 64,
105 "boot_osflags": "a",
106 "system_port": {
107 "peer": "system.membus.slave[0]",
108 "role": "MASTER"
109 },
110 "physmem": {
111 "static_frontend_latency": 10000,
112 "tRFC": 260000,
113 "activation_limit": 4,
114 "in_addr_map": true,
115 "IDD3N2": "0.0",
116 "tWTR": 7500,
117 "IDD52": "0.0",
118 "clk_domain": "system.clk_domain",
119 "channels": 1,
120 "write_buffer_size": 64,
121 "device_bus_width": 8,
122 "VDD": "1.5",
123 "write_high_thresh_perc": 85,
124 "cxx_class": "DRAMCtrl",
125 "bank_groups_per_rank": 0,
126 "IDD2N2": "0.0",
127 "port": {
128 "peer": "system.membus.master[0]",
129 "role": "SLAVE"
130 },
131 "tCCD_L": 0,
132 "IDD2N": "0.032",
133 "p_state_clk_gate_min": 1000,
134 "null": false,
135 "IDD2P1": "0.032",
136 "eventq_index": 0,
137 "tRRD": 6000,
138 "tRTW": 2500,
139 "IDD4R": "0.157",
140 "burst_length": 8,
141 "tRTP": 7500,
142 "IDD4W": "0.125",
143 "tWR": 15000,
144 "banks_per_rank": 8,
145 "devices_per_rank": 8,
146 "IDD2P02": "0.0",
147 "default_p_state": "UNDEFINED",
148 "p_state_clk_gate_max": 1000000000000,
149 "IDD6": "0.02",
150 "IDD5": "0.235",
151 "tRCD": 13750,
152 "type": "DRAMCtrl",
153 "IDD3P02": "0.0",
154 "tRRD_L": 0,
155 "IDD0": "0.055",
156 "IDD62": "0.0",
157 "min_writes_per_switch": 16,
158 "mem_sched_policy": "frfcfs",
159 "IDD02": "0.0",
160 "IDD2P0": "0.0",
161 "ranks_per_channel": 2,
162 "page_policy": "open_adaptive",
163 "IDD4W2": "0.0",
164 "tCS": 2500,
165 "power_model": null,
166 "tCL": 13750,
167 "read_buffer_size": 32,
168 "conf_table_reported": true,
169 "tCK": 1250,
170 "tRAS": 35000,
171 "tRP": 13750,
172 "tBURST": 5000,
173 "path": "system.physmem",
174 "tXP": 6000,
175 "tXS": 270000,
176 "addr_mapping": "RoRaBaCoCh",
177 "IDD3P0": "0.0",
178 "IDD3P1": "0.038",
179 "IDD3N": "0.038",
180 "name": "physmem",
181 "tXSDLL": 0,
182 "device_size": 536870912,
183 "kvm_map": true,
184 "dll": true,
185 "tXAW": 30000,
186 "write_low_thresh_perc": 50,
187 "range": "0:134217727:0:0:0:0",
188 "VDD2": "0.0",
189 "IDD2P12": "0.0",
190 "p_state_clk_gate_bins": 20,
191 "tXPDLL": 0,
192 "IDD4R2": "0.0",
193 "device_rowbuffer_size": 1024,
194 "static_backend_latency": 10000,
195 "max_accesses_per_row": 16,
196 "IDD3P12": "0.0",
197 "tREFI": 7800000
198 },
199 "power_model": null,
200 "work_cpus_ckpt_count": 0,
201 "thermal_components": [],
202 "path": "system",
203 "cpu_clk_domain": {
204 "name": "cpu_clk_domain",
205 "clock": [
206 500
207 ],
208 "init_perf_level": 0,
209 "voltage_domain": "system.voltage_domain",
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211 "cxx_class": "SrcClockDomain",
212 "path": "system.cpu_clk_domain",
213 "type": "SrcClockDomain",
214 "domain_id": -1
215 },
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217 "mem_mode": "timing",
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221 "load_addr_mask": 1099511627775,
222 "cpu": [
223 {
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225 "do_statistics_insts": true,
226 "numThreads": 1,
227 "fetch1LineSnapWidth": 0,
228 "fetch1ToFetch2BackwardDelay": 1,
229 "fetch1FetchLimit": 1,
230 "executeIssueLimit": 2,
231 "system": "system",
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233 "icache": {
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237 },
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249 "default_p_state": "UNDEFINED",
250 "p_state_clk_gate_max": 1000000000000,
251 "mem_side": {
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253 "role": "MASTER"
254 },
255 "mshrs": 4,
256 "writeback_clean": true,
257 "p_state_clk_gate_min": 1000,
258 "tags": {
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261 "name": "tags",
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263 "eventq_index": 0,
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265 "default_p_state": "UNDEFINED",
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267 "power_model": null,
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272 "path": "system.cpu.icache.tags",
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274 "type": "LRU",
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276 },
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279 "power_model": null,
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282 ],
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284 "prefetch_on_access": false,
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288 "name": "icache",
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290 "sequential_access": false,
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292 },
293 "function_trace": false,
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295 "decodeInputWidth": 2,
296 "cxx_class": "MinorCPU",
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298 "executeMemoryIssueLimit": 1,
299 "decodeCycleInput": true,
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311 "executeMemoryCommitLimit": 1,
312 "l2cache": {
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333 },
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380 },
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382 "socket_id": 0,
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385 "toL2Bus": {
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428 },
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453 }
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