tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=DerivO3CPU
  58 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  59 LFSTSize=1024
  60 LQEntries=32
  61 LSQCheckLoads=true
  62 LSQDepCheckShift=4
  63 SQEntries=32
  64 SSITSize=1024
  65 activity=0
  66 backComSize=5
  67 branchPred=system.cpu.branchPred
  68 cachePorts=200
  69 checker=Null
  70 clk_domain=system.cpu_clk_domain
  71 commitToDecodeDelay=1
  72 commitToFetchDelay=1
  73 commitToIEWDelay=1
  74 commitToRenameDelay=1
  75 commitWidth=8
  76 cpu_id=0
  77 decodeToFetchDelay=1
  78 decodeToRenameDelay=1
  79 decodeWidth=8
  80 default_p_state=UNDEFINED
  81 dispatchWidth=8
  82 do_checkpoint_insts=true
  83 do_quiesce=true
  84 do_statistics_insts=true
  85 dtb=system.cpu.dtb
  86 eventq_index=0
  87 fetchBufferSize=64
  88 fetchQueueSize=32
  89 fetchToDecodeDelay=1
  90 fetchTrapLatency=1
  91 fetchWidth=8
  92 forwardComSize=5
  93 fuPool=system.cpu.fuPool
  94 function_trace=false
  95 function_trace_start=0
  96 iewToCommitDelay=1
  97 iewToDecodeDelay=1
  98 iewToFetchDelay=1
  99 iewToRenameDelay=1
 100 interrupts=system.cpu.interrupts
 101 isa=system.cpu.isa
 102 issueToExecuteDelay=1
 103 issueWidth=8
 104 itb=system.cpu.itb
 105 max_insts_all_threads=0
 106 max_insts_any_thread=0
 107 max_loads_all_threads=0
 108 max_loads_any_thread=0
 109 needsTSO=false
 110 numIQEntries=64
 111 numPhysCCRegs=0
 112 numPhysFloatRegs=256
 113 numPhysIntRegs=256
 114 numROBEntries=192
 115 numRobs=1
 116 numThreads=1
 117 p_state_clk_gate_bins=20
 118 p_state_clk_gate_max=1000000000000
 119 p_state_clk_gate_min=1000
 120 power_model=Null
 121 profile=0
 122 progress_interval=0
 123 renameToDecodeDelay=1
 124 renameToFetchDelay=1
 125 renameToIEWDelay=2
 126 renameToROBDelay=1
 127 renameWidth=8
 128 simpoint_start_insts=
 129 smtCommitPolicy=RoundRobin
 130 smtFetchPolicy=SingleThread
 131 smtIQPolicy=Partitioned
 132 smtIQThreshold=100
 133 smtLSQPolicy=Partitioned
 134 smtLSQThreshold=100
 135 smtNumFetchingThreads=1
 136 smtROBPolicy=Partitioned
 137 smtROBThreshold=100
 138 socket_id=0
 139 squashWidth=8
 140 store_set_clear_period=250000
 141 switched_out=false
 142 system=system
 143 tracer=system.cpu.tracer
 144 trapLatency=13
 145 wbWidth=8
 146 workload=system.cpu.workload
 147 dcache_port=system.cpu.dcache.cpu_side
 148 icache_port=system.cpu.icache.cpu_side
 149
 150 [system.cpu.branchPred]
 151 type=TournamentBP
 152 BTBEntries=4096
 153 BTBTagSize=16
 154 RASSize=16
 155 choiceCtrBits=2
 156 choicePredictorSize=8192
 157 eventq_index=0
 158 globalCtrBits=2
 159 globalPredictorSize=8192
 160 indirectHashGHR=true
 161 indirectHashTargets=true
 162 indirectPathLength=3
 163 indirectSets=256
 164 indirectTagSize=16
 165 indirectWays=2
 166 instShiftAmt=2
 167 localCtrBits=2
 168 localHistoryTableSize=2048
 169 localPredictorSize=2048
 170 numThreads=1
 171 useIndirect=true
 172
 173 [system.cpu.dcache]
 174 type=Cache
 175 children=tags
 176 addr_ranges=0:18446744073709551615:0:0:0:0
 177 assoc=2
 178 clk_domain=system.cpu_clk_domain
 179 clusivity=mostly_incl
 180 data_latency=2
 181 default_p_state=UNDEFINED
 182 demand_mshr_reserve=1
 183 eventq_index=0
 184 is_read_only=false
 185 max_miss_count=0
 186 mshrs=4
 187 p_state_clk_gate_bins=20
 188 p_state_clk_gate_max=1000000000000
 189 p_state_clk_gate_min=1000
 190 power_model=Null
 191 prefetch_on_access=false
 192 prefetcher=Null
 193 response_latency=2
 194 sequential_access=false
 195 size=262144
 196 system=system
 197 tag_latency=2
 198 tags=system.cpu.dcache.tags
 199 tgts_per_mshr=20
 200 write_buffers=8
 201 writeback_clean=false
 202 cpu_side=system.cpu.dcache_port
 203 mem_side=system.cpu.toL2Bus.slave[1]
 204
 205 [system.cpu.dcache.tags]
 206 type=LRU
 207 assoc=2
 208 block_size=64
 209 clk_domain=system.cpu_clk_domain
 210 data_latency=2
 211 default_p_state=UNDEFINED
 212 eventq_index=0
 213 p_state_clk_gate_bins=20
 214 p_state_clk_gate_max=1000000000000
 215 p_state_clk_gate_min=1000
 216 power_model=Null
 217 sequential_access=false
 218 size=262144
 219 tag_latency=2
 220
 221 [system.cpu.dtb]
 222 type=RiscvTLB
 223 eventq_index=0
 224 size=64
 225
 226 [system.cpu.fuPool]
 227 type=FUPool
 228 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 229 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 230 eventq_index=0
 231
 232 [system.cpu.fuPool.FUList0]
 233 type=FUDesc
 234 children=opList
 235 count=6
 236 eventq_index=0
 237 opList=system.cpu.fuPool.FUList0.opList
 238
 239 [system.cpu.fuPool.FUList0.opList]
 240 type=OpDesc
 241 eventq_index=0
 242 opClass=IntAlu
 243 opLat=1
 244 pipelined=true
 245
 246 [system.cpu.fuPool.FUList1]
 247 type=FUDesc
 248 children=opList0 opList1
 249 count=2
 250 eventq_index=0
 251 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 252
 253 [system.cpu.fuPool.FUList1.opList0]
 254 type=OpDesc
 255 eventq_index=0
 256 opClass=IntMult
 257 opLat=3
 258 pipelined=true
 259
 260 [system.cpu.fuPool.FUList1.opList1]
 261 type=OpDesc
 262 eventq_index=0
 263 opClass=IntDiv
 264 opLat=20
 265 pipelined=false
 266
 267 [system.cpu.fuPool.FUList2]
 268 type=FUDesc
 269 children=opList0 opList1 opList2
 270 count=4
 271 eventq_index=0
 272 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 273
 274 [system.cpu.fuPool.FUList2.opList0]
 275 type=OpDesc
 276 eventq_index=0
 277 opClass=FloatAdd
 278 opLat=2
 279 pipelined=true
 280
 281 [system.cpu.fuPool.FUList2.opList1]
 282 type=OpDesc
 283 eventq_index=0
 284 opClass=FloatCmp
 285 opLat=2
 286 pipelined=true
 287
 288 [system.cpu.fuPool.FUList2.opList2]
 289 type=OpDesc
 290 eventq_index=0
 291 opClass=FloatCvt
 292 opLat=2
 293 pipelined=true
 294
 295 [system.cpu.fuPool.FUList3]
 296 type=FUDesc
 297 children=opList0 opList1 opList2 opList3 opList4
 298 count=2
 299 eventq_index=0
 300 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
 301
 302 [system.cpu.fuPool.FUList3.opList0]
 303 type=OpDesc
 304 eventq_index=0
 305 opClass=FloatMult
 306 opLat=4
 307 pipelined=true
 308
 309 [system.cpu.fuPool.FUList3.opList1]
 310 type=OpDesc
 311 eventq_index=0
 312 opClass=FloatMultAcc
 313 opLat=5
 314 pipelined=true
 315
 316 [system.cpu.fuPool.FUList3.opList2]
 317 type=OpDesc
 318 eventq_index=0
 319 opClass=FloatMisc
 320 opLat=3
 321 pipelined=true
 322
 323 [system.cpu.fuPool.FUList3.opList3]
 324 type=OpDesc
 325 eventq_index=0
 326 opClass=FloatDiv
 327 opLat=12
 328 pipelined=false
 329
 330 [system.cpu.fuPool.FUList3.opList4]
 331 type=OpDesc
 332 eventq_index=0
 333 opClass=FloatSqrt
 334 opLat=24
 335 pipelined=false
 336
 337 [system.cpu.fuPool.FUList4]
 338 type=FUDesc
 339 children=opList0 opList1
 340 count=0
 341 eventq_index=0
 342 opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
 343
 344 [system.cpu.fuPool.FUList4.opList0]
 345 type=OpDesc
 346 eventq_index=0
 347 opClass=MemRead
 348 opLat=1
 349 pipelined=true
 350
 351 [system.cpu.fuPool.FUList4.opList1]
 352 type=OpDesc
 353 eventq_index=0
 354 opClass=FloatMemRead
 355 opLat=1
 356 pipelined=true
 357
 358 [system.cpu.fuPool.FUList5]
 359 type=FUDesc
 360 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 361 count=4
 362 eventq_index=0
 363 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 364
 365 [system.cpu.fuPool.FUList5.opList00]
 366 type=OpDesc
 367 eventq_index=0
 368 opClass=SimdAdd
 369 opLat=1
 370 pipelined=true
 371
 372 [system.cpu.fuPool.FUList5.opList01]
 373 type=OpDesc
 374 eventq_index=0
 375 opClass=SimdAddAcc
 376 opLat=1
 377 pipelined=true
 378
 379 [system.cpu.fuPool.FUList5.opList02]
 380 type=OpDesc
 381 eventq_index=0
 382 opClass=SimdAlu
 383 opLat=1
 384 pipelined=true
 385
 386 [system.cpu.fuPool.FUList5.opList03]
 387 type=OpDesc
 388 eventq_index=0
 389 opClass=SimdCmp
 390 opLat=1
 391 pipelined=true
 392
 393 [system.cpu.fuPool.FUList5.opList04]
 394 type=OpDesc
 395 eventq_index=0
 396 opClass=SimdCvt
 397 opLat=1
 398 pipelined=true
 399
 400 [system.cpu.fuPool.FUList5.opList05]
 401 type=OpDesc
 402 eventq_index=0
 403 opClass=SimdMisc
 404 opLat=1
 405 pipelined=true
 406
 407 [system.cpu.fuPool.FUList5.opList06]
 408 type=OpDesc
 409 eventq_index=0
 410 opClass=SimdMult
 411 opLat=1
 412 pipelined=true
 413
 414 [system.cpu.fuPool.FUList5.opList07]
 415 type=OpDesc
 416 eventq_index=0
 417 opClass=SimdMultAcc
 418 opLat=1
 419 pipelined=true
 420
 421 [system.cpu.fuPool.FUList5.opList08]
 422 type=OpDesc
 423 eventq_index=0
 424 opClass=SimdShift
 425 opLat=1
 426 pipelined=true
 427
 428 [system.cpu.fuPool.FUList5.opList09]
 429 type=OpDesc
 430 eventq_index=0
 431 opClass=SimdShiftAcc
 432 opLat=1
 433 pipelined=true
 434
 435 [system.cpu.fuPool.FUList5.opList10]
 436 type=OpDesc
 437 eventq_index=0
 438 opClass=SimdSqrt
 439 opLat=1
 440 pipelined=true
 441
 442 [system.cpu.fuPool.FUList5.opList11]
 443 type=OpDesc
 444 eventq_index=0
 445 opClass=SimdFloatAdd
 446 opLat=1
 447 pipelined=true
 448
 449 [system.cpu.fuPool.FUList5.opList12]
 450 type=OpDesc
 451 eventq_index=0
 452 opClass=SimdFloatAlu
 453 opLat=1
 454 pipelined=true
 455
 456 [system.cpu.fuPool.FUList5.opList13]
 457 type=OpDesc
 458 eventq_index=0
 459 opClass=SimdFloatCmp
 460 opLat=1
 461 pipelined=true
 462
 463 [system.cpu.fuPool.FUList5.opList14]
 464 type=OpDesc
 465 eventq_index=0
 466 opClass=SimdFloatCvt
 467 opLat=1
 468 pipelined=true
 469
 470 [system.cpu.fuPool.FUList5.opList15]
 471 type=OpDesc
 472 eventq_index=0
 473 opClass=SimdFloatDiv
 474 opLat=1
 475 pipelined=true
 476
 477 [system.cpu.fuPool.FUList5.opList16]
 478 type=OpDesc
 479 eventq_index=0
 480 opClass=SimdFloatMisc
 481 opLat=1
 482 pipelined=true
 483
 484 [system.cpu.fuPool.FUList5.opList17]
 485 type=OpDesc
 486 eventq_index=0
 487 opClass=SimdFloatMult
 488 opLat=1
 489 pipelined=true
 490
 491 [system.cpu.fuPool.FUList5.opList18]
 492 type=OpDesc
 493 eventq_index=0
 494 opClass=SimdFloatMultAcc
 495 opLat=1
 496 pipelined=true
 497
 498 [system.cpu.fuPool.FUList5.opList19]
 499 type=OpDesc
 500 eventq_index=0
 501 opClass=SimdFloatSqrt
 502 opLat=1
 503 pipelined=true
 504
 505 [system.cpu.fuPool.FUList6]
 506 type=FUDesc
 507 children=opList0 opList1
 508 count=0
 509 eventq_index=0
 510 opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 511
 512 [system.cpu.fuPool.FUList6.opList0]
 513 type=OpDesc
 514 eventq_index=0
 515 opClass=MemWrite
 516 opLat=1
 517 pipelined=true
 518
 519 [system.cpu.fuPool.FUList6.opList1]
 520 type=OpDesc
 521 eventq_index=0
 522 opClass=FloatMemWrite
 523 opLat=1
 524 pipelined=true
 525
 526 [system.cpu.fuPool.FUList7]
 527 type=FUDesc
 528 children=opList0 opList1 opList2 opList3
 529 count=4
 530 eventq_index=0
 531 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
 532
 533 [system.cpu.fuPool.FUList7.opList0]
 534 type=OpDesc
 535 eventq_index=0
 536 opClass=MemRead
 537 opLat=1
 538 pipelined=true
 539
 540 [system.cpu.fuPool.FUList7.opList1]
 541 type=OpDesc
 542 eventq_index=0
 543 opClass=MemWrite
 544 opLat=1
 545 pipelined=true
 546
 547 [system.cpu.fuPool.FUList7.opList2]
 548 type=OpDesc
 549 eventq_index=0
 550 opClass=FloatMemRead
 551 opLat=1
 552 pipelined=true
 553
 554 [system.cpu.fuPool.FUList7.opList3]
 555 type=OpDesc
 556 eventq_index=0
 557 opClass=FloatMemWrite
 558 opLat=1
 559 pipelined=true
 560
 561 [system.cpu.fuPool.FUList8]
 562 type=FUDesc
 563 children=opList
 564 count=1
 565 eventq_index=0
 566 opList=system.cpu.fuPool.FUList8.opList
 567
 568 [system.cpu.fuPool.FUList8.opList]
 569 type=OpDesc
 570 eventq_index=0
 571 opClass=IprAccess
 572 opLat=3
 573 pipelined=false
 574
 575 [system.cpu.icache]
 576 type=Cache
 577 children=tags
 578 addr_ranges=0:18446744073709551615:0:0:0:0
 579 assoc=2
 580 clk_domain=system.cpu_clk_domain
 581 clusivity=mostly_incl
 582 data_latency=2
 583 default_p_state=UNDEFINED
 584 demand_mshr_reserve=1
 585 eventq_index=0
 586 is_read_only=true
 587 max_miss_count=0
 588 mshrs=4
 589 p_state_clk_gate_bins=20
 590 p_state_clk_gate_max=1000000000000
 591 p_state_clk_gate_min=1000
 592 power_model=Null
 593 prefetch_on_access=false
 594 prefetcher=Null
 595 response_latency=2
 596 sequential_access=false
 597 size=131072
 598 system=system
 599 tag_latency=2
 600 tags=system.cpu.icache.tags
 601 tgts_per_mshr=20
 602 write_buffers=8
 603 writeback_clean=true
 604 cpu_side=system.cpu.icache_port
 605 mem_side=system.cpu.toL2Bus.slave[0]
 606
 607 [system.cpu.icache.tags]
 608 type=LRU
 609 assoc=2
 610 block_size=64
 611 clk_domain=system.cpu_clk_domain
 612 data_latency=2
 613 default_p_state=UNDEFINED
 614 eventq_index=0
 615 p_state_clk_gate_bins=20
 616 p_state_clk_gate_max=1000000000000
 617 p_state_clk_gate_min=1000
 618 power_model=Null
 619 sequential_access=false
 620 size=131072
 621 tag_latency=2
 622
 623 [system.cpu.interrupts]
 624 type=RiscvInterrupts
 625 eventq_index=0
 626
 627 [system.cpu.isa]
 628 type=RiscvISA
 629 eventq_index=0
 630
 631 [system.cpu.itb]
 632 type=RiscvTLB
 633 eventq_index=0
 634 size=64
 635
 636 [system.cpu.l2cache]
 637 type=Cache
 638 children=tags
 639 addr_ranges=0:18446744073709551615:0:0:0:0
 640 assoc=8
 641 clk_domain=system.cpu_clk_domain
 642 clusivity=mostly_incl
 643 data_latency=20
 644 default_p_state=UNDEFINED
 645 demand_mshr_reserve=1
 646 eventq_index=0
 647 is_read_only=false
 648 max_miss_count=0
 649 mshrs=20
 650 p_state_clk_gate_bins=20
 651 p_state_clk_gate_max=1000000000000
 652 p_state_clk_gate_min=1000
 653 power_model=Null
 654 prefetch_on_access=false
 655 prefetcher=Null
 656 response_latency=20
 657 sequential_access=false
 658 size=2097152
 659 system=system
 660 tag_latency=20
 661 tags=system.cpu.l2cache.tags
 662 tgts_per_mshr=12
 663 write_buffers=8
 664 writeback_clean=false
 665 cpu_side=system.cpu.toL2Bus.master[0]
 666 mem_side=system.membus.slave[1]
 667
 668 [system.cpu.l2cache.tags]
 669 type=LRU
 670 assoc=8
 671 block_size=64
 672 clk_domain=system.cpu_clk_domain
 673 data_latency=20
 674 default_p_state=UNDEFINED
 675 eventq_index=0
 676 p_state_clk_gate_bins=20
 677 p_state_clk_gate_max=1000000000000
 678 p_state_clk_gate_min=1000
 679 power_model=Null
 680 sequential_access=false
 681 size=2097152
 682 tag_latency=20
 683
 684 [system.cpu.toL2Bus]
 685 type=CoherentXBar
 686 children=snoop_filter
 687 clk_domain=system.cpu_clk_domain
 688 default_p_state=UNDEFINED
 689 eventq_index=0
 690 forward_latency=0
 691 frontend_latency=1
 692 p_state_clk_gate_bins=20
 693 p_state_clk_gate_max=1000000000000
 694 p_state_clk_gate_min=1000
 695 point_of_coherency=false
 696 power_model=Null
 697 response_latency=1
 698 snoop_filter=system.cpu.toL2Bus.snoop_filter
 699 snoop_response_latency=1
 700 system=system
 701 use_default_range=false
 702 width=32
 703 master=system.cpu.l2cache.cpu_side
 704 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 705
 706 [system.cpu.toL2Bus.snoop_filter]
 707 type=SnoopFilter
 708 eventq_index=0
 709 lookup_latency=0
 710 max_capacity=8388608
 711 system=system
 712
 713 [system.cpu.tracer]
 714 type=ExeTracer
 715 eventq_index=0
 716
 717 [system.cpu.workload]
 718 type=LiveProcess
 719 cmd=hello
 720 cwd=
 721 drivers=
 722 egid=100
 723 env=
 724 errout=cerr
 725 euid=100
 726 eventq_index=0
 727 executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello
 728 gid=100
 729 input=cin
 730 kvmInSE=false
 731 max_stack_size=67108864
 732 output=cout
 733 pid=100
 734 ppid=99
 735 simpoint=0
 736 system=system
 737 uid=100
 738 useArchPT=false
 739
 740 [system.cpu_clk_domain]
 741 type=SrcClockDomain
 742 clock=500
 743 domain_id=-1
 744 eventq_index=0
 745 init_perf_level=0
 746 voltage_domain=system.voltage_domain
 747
 748 [system.dvfs_handler]
 749 type=DVFSHandler
 750 domains=
 751 enable=false
 752 eventq_index=0
 753 sys_clk_domain=system.clk_domain
 754 transition_latency=100000000
 755
 756 [system.membus]
 757 type=CoherentXBar
 758 children=snoop_filter
 759 clk_domain=system.clk_domain
 760 default_p_state=UNDEFINED
 761 eventq_index=0
 762 forward_latency=4
 763 frontend_latency=3
 764 p_state_clk_gate_bins=20
 765 p_state_clk_gate_max=1000000000000
 766 p_state_clk_gate_min=1000
 767 point_of_coherency=true
 768 power_model=Null
 769 response_latency=2
 770 snoop_filter=system.membus.snoop_filter
 771 snoop_response_latency=4
 772 system=system
 773 use_default_range=false
 774 width=16
 775 master=system.physmem.port
 776 slave=system.system_port system.cpu.l2cache.mem_side
 777
 778 [system.membus.snoop_filter]
 779 type=SnoopFilter
 780 eventq_index=0
 781 lookup_latency=1
 782 max_capacity=8388608
 783 system=system
 784
 785 [system.physmem]
 786 type=DRAMCtrl
 787 IDD0=0.055000
 788 IDD02=0.000000
 789 IDD2N=0.032000
 790 IDD2N2=0.000000
 791 IDD2P0=0.000000
 792 IDD2P02=0.000000
 793 IDD2P1=0.032000
 794 IDD2P12=0.000000
 795 IDD3N=0.038000
 796 IDD3N2=0.000000
 797 IDD3P0=0.000000
 798 IDD3P02=0.000000
 799 IDD3P1=0.038000
 800 IDD3P12=0.000000
 801 IDD4R=0.157000
 802 IDD4R2=0.000000
 803 IDD4W=0.125000
 804 IDD4W2=0.000000
 805 IDD5=0.235000
 806 IDD52=0.000000
 807 IDD6=0.020000
 808 IDD62=0.000000
 809 VDD=1.500000
 810 VDD2=0.000000
 811 activation_limit=4
 812 addr_mapping=RoRaBaCoCh
 813 bank_groups_per_rank=0
 814 banks_per_rank=8
 815 burst_length=8
 816 channels=1
 817 clk_domain=system.clk_domain
 818 conf_table_reported=true
 819 default_p_state=UNDEFINED
 820 device_bus_width=8
 821 device_rowbuffer_size=1024
 822 device_size=536870912
 823 devices_per_rank=8
 824 dll=true
 825 eventq_index=0
 826 in_addr_map=true
 827 kvm_map=true
 828 max_accesses_per_row=16
 829 mem_sched_policy=frfcfs
 830 min_writes_per_switch=16
 831 null=false
 832 p_state_clk_gate_bins=20
 833 p_state_clk_gate_max=1000000000000
 834 p_state_clk_gate_min=1000
 835 page_policy=open_adaptive
 836 power_model=Null
 837 range=0:134217727:0:0:0:0
 838 ranks_per_channel=2
 839 read_buffer_size=32
 840 static_backend_latency=10000
 841 static_frontend_latency=10000
 842 tBURST=5000
 843 tCCD_L=0
 844 tCK=1250
 845 tCL=13750
 846 tCS=2500
 847 tRAS=35000
 848 tRCD=13750
 849 tREFI=7800000
 850 tRFC=260000
 851 tRP=13750
 852 tRRD=6000
 853 tRRD_L=0
 854 tRTP=7500
 855 tRTW=2500
 856 tWR=15000
 857 tWTR=7500
 858 tXAW=30000
 859 tXP=6000
 860 tXPDLL=0
 861 tXS=270000
 862 tXSDLL=0
 863 write_buffer_size=64
 864 write_high_thresh_perc=85
 865 write_low_thresh_perc=50
 866 port=system.membus.master[0]
 867
 868 [system.voltage_domain]
 869 type=VoltageDomain
 870 eventq_index=0
 871 voltage=1.000000
 872