2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000008 # Number of seconds simulated
4 sim_ticks 7939500 # Number of ticks simulated
5 final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 81718 # Simulator instruction rate (inst/s)
8 host_op_rate 81674 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 408398393 # Simulator tick rate (ticks/s)
10 host_mem_usage 251348 # Number of bytes of host memory used
11 host_seconds 0.02 # Real time elapsed on the host
12 sim_insts 1587 # Number of instructions simulated
13 sim_ops 1587 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 11648 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 9600 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 9600 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 150 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 182 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 1209144153 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 257950753 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 1467094905 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 1209144153 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 1209144153 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 1209144153 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 257950753 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 1467094905 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.readReqs 184 # Number of read requests accepted
34 system.physmem.writeReqs 0 # Number of write requests accepted
35 system.physmem.readBursts 184 # Number of DRAM read bursts, including those serviced by the write queue
36 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37 system.physmem.bytesReadDRAM 11648 # Total number of bytes read from DRAM
38 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40 system.physmem.bytesReadSys 11776 # Total read bytes from the system interface side
41 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45 system.physmem.perBankRdBursts::0 93 # Per bank write bursts
46 system.physmem.perBankRdBursts::1 62 # Per bank write bursts
47 system.physmem.perBankRdBursts::2 18 # Per bank write bursts
48 system.physmem.perBankRdBursts::3 9 # Per bank write bursts
49 system.physmem.perBankRdBursts::4 0 # Per bank write bursts
50 system.physmem.perBankRdBursts::5 0 # Per bank write bursts
51 system.physmem.perBankRdBursts::6 0 # Per bank write bursts
52 system.physmem.perBankRdBursts::7 0 # Per bank write bursts
53 system.physmem.perBankRdBursts::8 0 # Per bank write bursts
54 system.physmem.perBankRdBursts::9 0 # Per bank write bursts
55 system.physmem.perBankRdBursts::10 0 # Per bank write bursts
56 system.physmem.perBankRdBursts::11 0 # Per bank write bursts
57 system.physmem.perBankRdBursts::12 0 # Per bank write bursts
58 system.physmem.perBankRdBursts::13 0 # Per bank write bursts
59 system.physmem.perBankRdBursts::14 0 # Per bank write bursts
60 system.physmem.perBankRdBursts::15 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79 system.physmem.totGap 7854500 # Total gap between requests
80 system.physmem.readPktSize::0 0 # Read request sizes (log2)
81 system.physmem.readPktSize::1 0 # Read request sizes (log2)
82 system.physmem.readPktSize::2 0 # Read request sizes (log2)
83 system.physmem.readPktSize::3 0 # Read request sizes (log2)
84 system.physmem.readPktSize::4 0 # Read request sizes (log2)
85 system.physmem.readPktSize::5 0 # Read request sizes (log2)
86 system.physmem.readPktSize::6 184 # Read request sizes (log2)
87 system.physmem.writePktSize::0 0 # Write request sizes (log2)
88 system.physmem.writePktSize::1 0 # Write request sizes (log2)
89 system.physmem.writePktSize::2 0 # Write request sizes (log2)
90 system.physmem.writePktSize::3 0 # Write request sizes (log2)
91 system.physmem.writePktSize::4 0 # Write request sizes (log2)
92 system.physmem.writePktSize::5 0 # Write request sizes (log2)
93 system.physmem.writePktSize::6 0 # Write request sizes (log2)
94 system.physmem.rdQLenPdf::0 94 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190 system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::mean 896 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::gmean 813.228460 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::stdev 265.169128 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 1 7.69% 7.69% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::512-639 1 7.69% 15.38% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::768-895 1 7.69% 23.08% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::896-1023 1 7.69% 30.77% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation
200 system.physmem.totQLat 1405000 # Total ticks spent queuing
201 system.physmem.totMemAccLat 4817500 # Total ticks spent from burst creation until serviced by the DRAM
202 system.physmem.totBusLat 910000 # Total ticks spent in databus transfers
203 system.physmem.avgQLat 7635.87 # Average queueing delay per DRAM burst
204 system.physmem.avgBusLat 4945.65 # Average bus latency per DRAM burst
205 system.physmem.avgMemAccLat 26182.07 # Average memory access latency per DRAM burst
206 system.physmem.avgRdBW 1467.09 # Average DRAM read bandwidth in MiByte/s
207 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
208 system.physmem.avgRdBWSys 1483.22 # Average system read bandwidth in MiByte/s
209 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
210 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
211 system.physmem.busUtil 11.46 # Data bus utilization in percentage
212 system.physmem.busUtilRead 11.46 # Data bus utilization in percentage for reads
213 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
214 system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing
215 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
216 system.physmem.readRowHits 169 # Number of row buffer hits during reads
217 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
218 system.physmem.readRowHitRate 91.85 # Row buffer hit rate for reads
219 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
220 system.physmem.avgGap 42687.50 # Average gap between requests
221 system.physmem.pageHitRate 91.85 # Row buffer hit rate, read and write combined
222 system.physmem_0.actEnergy 92820 # Energy for activate commands per rank (pJ)
223 system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ)
224 system.physmem_0.readEnergy 1299480 # Energy for read commands per rank (pJ)
225 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
226 system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
227 system.physmem_0.actBackEnergy 1581180 # Energy for active background per rank (pJ)
228 system.physmem_0.preBackEnergy 10080 # Energy for precharge background per rank (pJ)
229 system.physmem_0.actPowerDownEnergy 2075940 # Energy for active power-down per rank (pJ)
230 system.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ)
231 system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
232 system.physmem_0.totalEnergy 5723475 # Total energy per rank (pJ)
233 system.physmem_0.averagePower 711.322044 # Core power per rank (mW)
234 system.physmem_0.totalIdleTime 4551000 # Total Idle time Per DRAM Rank
235 system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
236 system.physmem_0.memoryStateTime::REF 139500 # Time in different power states
237 system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
238 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
239 system.physmem_0.memoryStateTime::ACT 3237500 # Time in different power states
240 system.physmem_0.memoryStateTime::ACT_PDN 4551000 # Time in different power states
241 system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ)
242 system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
243 system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ)
244 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
245 system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
246 system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ)
247 system.physmem_1.preBackEnergy 2989920 # Energy for precharge background per rank (pJ)
248 system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
249 system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ)
250 system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
251 system.physmem_1.totalEnergy 3716850 # Total energy per rank (pJ)
252 system.physmem_1.averagePower 462.726424 # Core power per rank (mW)
253 system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank
254 system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states
255 system.physmem_1.memoryStateTime::REF 153250 # Time in different power states
256 system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
257 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
258 system.physmem_1.memoryStateTime::ACT 0 # Time in different power states
259 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
260 system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
261 system.cpu.branchPred.lookups 1255 # Number of BP lookups
262 system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted
263 system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect
264 system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups
265 system.cpu.branchPred.BTBHits 302 # Number of BTB hits
266 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
267 system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage
268 system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
269 system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
270 system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups.
271 system.cpu.branchPred.indirectHits 24 # Number of indirect target hits.
272 system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
273 system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches.
274 system.cpu_clk_domain.clock 500 # Clock period in ticks
275 system.cpu.dtb.read_hits 0 # DTB read hits
276 system.cpu.dtb.read_misses 0 # DTB read misses
277 system.cpu.dtb.read_accesses 0 # DTB read accesses
278 system.cpu.dtb.write_hits 0 # DTB write hits
279 system.cpu.dtb.write_misses 0 # DTB write misses
280 system.cpu.dtb.write_accesses 0 # DTB write accesses
281 system.cpu.dtb.hits 0 # DTB hits
282 system.cpu.dtb.misses 0 # DTB misses
283 system.cpu.dtb.accesses 0 # DTB accesses
284 system.cpu.itb.read_hits 0 # DTB read hits
285 system.cpu.itb.read_misses 0 # DTB read misses
286 system.cpu.itb.read_accesses 0 # DTB read accesses
287 system.cpu.itb.write_hits 0 # DTB write hits
288 system.cpu.itb.write_misses 0 # DTB write misses
289 system.cpu.itb.write_accesses 0 # DTB write accesses
290 system.cpu.itb.hits 0 # DTB hits
291 system.cpu.itb.misses 0 # DTB misses
292 system.cpu.itb.accesses 0 # DTB accesses
293 system.cpu.workload.numSyscalls 9 # Number of system calls
294 system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states
295 system.cpu.numCycles 15880 # number of cpu cycles simulated
296 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
297 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
298 system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss
299 system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed
300 system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered
301 system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken
302 system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked
303 system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing
304 system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
305 system.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps
306 system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR
307 system.cpu.fetch.CacheLines 803 # Number of cache lines fetched
308 system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed
309 system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total)
310 system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total)
311 system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total)
312 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
313 system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total)
314 system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total)
315 system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total)
316 system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total)
317 system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total)
318 system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total)
319 system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total)
320 system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total)
321 system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle
327 system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle
328 system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle
329 system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked
330 system.cpu.decode.RunCycles 756 # Number of cycles decode is running
331 system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
332 system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing
333 system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch
334 system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction
335 system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode
336 system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode
337 system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing
338 system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle
339 system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking
340 system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst
341 system.cpu.rename.RunCycles 673 # Number of cycles rename is running
342 system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking
343 system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename
344 system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full
345 system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed
346 system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made
347 system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups
348 system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed
349 system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing
350 system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
351 system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed
352 system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer
353 system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit.
354 system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit.
355 system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
356 system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
357 system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec)
358 system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ
359 system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued
360 system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
361 system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling
362 system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph
363 system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
364 system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle
365 system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle
366 system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle
367 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
368 system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle
369 system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle
370 system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle
371 system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle
372 system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle
373 system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle
374 system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle
375 system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle
376 system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle
377 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
378 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle
381 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
382 system.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available
383 system.cpu.iq.fu_full::IntMult 0 0.00% 5.71% # attempts to use FU when none available
384 system.cpu.iq.fu_full::IntDiv 0 0.00% 5.71% # attempts to use FU when none available
385 system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.71% # attempts to use FU when none available
386 system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.71% # attempts to use FU when none available
387 system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.71% # attempts to use FU when none available
388 system.cpu.iq.fu_full::FloatMult 0 0.00% 5.71% # attempts to use FU when none available
389 system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available
390 system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.71% # attempts to use FU when none available
391 system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.71% # attempts to use FU when none available
392 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.71% # attempts to use FU when none available
393 system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.71% # attempts to use FU when none available
394 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.71% # attempts to use FU when none available
395 system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.71% # attempts to use FU when none available
396 system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.71% # attempts to use FU when none available
397 system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.71% # attempts to use FU when none available
398 system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.71% # attempts to use FU when none available
399 system.cpu.iq.fu_full::SimdMult 0 0.00% 5.71% # attempts to use FU when none available
400 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.71% # attempts to use FU when none available
401 system.cpu.iq.fu_full::SimdShift 0 0.00% 5.71% # attempts to use FU when none available
402 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.71% # attempts to use FU when none available
403 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.71% # attempts to use FU when none available
404 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.71% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.71% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.71% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.71% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.71% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.71% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.71% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available
413 system.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available
414 system.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available
415 system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
416 system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
417 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
418 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
419 system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued
420 system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued
421 system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued
422 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued
423 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued
424 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued
425 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued
426 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued
427 system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued
428 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued
429 system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued
430 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued
431 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued
432 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued
433 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued
434 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued
435 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued
436 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued
437 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued
438 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued
451 system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued
452 system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
454 system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
455 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
456 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
457 system.cpu.iq.FU_type_0::total 2703 # Type of FU issued
458 system.cpu.iq.rate 0.170214 # Inst issue rate
459 system.cpu.iq.fu_busy_cnt 70 # FU busy when requested
460 system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst)
461 system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads
462 system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes
463 system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses
464 system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
465 system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
466 system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
467 system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses
468 system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
469 system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores
470 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
471 system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed
472 system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
473 system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations
474 system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed
475 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
476 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
477 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
478 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
479 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
480 system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing
481 system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking
482 system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
483 system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ
484 system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch
485 system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions
486 system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions
487 system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions
488 system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
489 system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
490 system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations
491 system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly
492 system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly
493 system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute
494 system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions
495 system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed
496 system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute
497 system.cpu.iew.exec_swp 0 # number of swp insts executed
498 system.cpu.iew.exec_nop 0 # number of nop insts executed
499 system.cpu.iew.exec_refs 846 # number of memory reference insts executed
500 system.cpu.iew.exec_branches 566 # Number of branches executed
501 system.cpu.iew.exec_stores 375 # Number of stores executed
502 system.cpu.iew.exec_rate 0.154849 # Inst execution rate
503 system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit
504 system.cpu.iew.wb_count 2318 # cumulative count of insts written-back
505 system.cpu.iew.wb_producers 798 # num instructions producing a value
506 system.cpu.iew.wb_consumers 1140 # num instructions consuming a value
507 system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle
508 system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back
509 system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit
510 system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
511 system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted
512 system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle
513 system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle
514 system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle
515 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
516 system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle
517 system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle
518 system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle
519 system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle
520 system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle
529 system.cpu.commit.committedInsts 1587 # Number of instructions committed
530 system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed
531 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
532 system.cpu.commit.refs 568 # Number of memory references committed
533 system.cpu.commit.loads 289 # Number of loads committed
534 system.cpu.commit.membars 0 # Number of memory barriers committed
535 system.cpu.commit.branches 373 # Number of branches committed
536 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
537 system.cpu.commit.int_insts 1587 # Number of committed integer instructions.
538 system.cpu.commit.function_calls 142 # Number of function calls committed.
539 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
540 system.cpu.commit.op_class_0::IntAlu 1019 64.21% 64.21% # Class of committed instruction
541 system.cpu.commit.op_class_0::IntMult 0 0.00% 64.21% # Class of committed instruction
542 system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.21% # Class of committed instruction
543 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.21% # Class of committed instruction
544 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.21% # Class of committed instruction
545 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.21% # Class of committed instruction
546 system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.21% # Class of committed instruction
547 system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 64.21% # Class of committed instruction
548 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.21% # Class of committed instruction
549 system.cpu.commit.op_class_0::FloatMisc 0 0.00% 64.21% # Class of committed instruction
550 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.21% # Class of committed instruction
551 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.21% # Class of committed instruction
552 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.21% # Class of committed instruction
553 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.21% # Class of committed instruction
554 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.21% # Class of committed instruction
555 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.21% # Class of committed instruction
556 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.21% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.21% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.21% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.21% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.21% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.21% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.21% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.21% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.21% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.21% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.21% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.21% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.21% # Class of committed instruction
569 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.21% # Class of committed instruction
570 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.21% # Class of committed instruction
571 system.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction
572 system.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction
573 system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
574 system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
575 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
576 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
577 system.cpu.commit.op_class_0::total 1587 # Class of committed instruction
578 system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached
579 system.cpu.rob.rob_reads 7050 # The number of ROB reads
580 system.cpu.rob.rob_writes 6361 # The number of ROB writes
581 system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself
582 system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling
583 system.cpu.committedInsts 1587 # Number of Instructions Simulated
584 system.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated
585 system.cpu.cpi 10.006301 # CPI: Cycles Per Instruction
586 system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads
587 system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle
588 system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads
589 system.cpu.int_regfile_reads 3116 # number of integer regfile reads
590 system.cpu.int_regfile_writes 1668 # number of integer regfile writes
591 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
592 system.cpu.dcache.tags.replacements 0 # number of replacements
593 system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use
594 system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks.
595 system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks.
596 system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks.
597 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
598 system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor
599 system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy
600 system.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy
601 system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id
602 system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
603 system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id
604 system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses
605 system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses
606 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
607 system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits
608 system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits
609 system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits
610 system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits
611 system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits
612 system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits
613 system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits
614 system.cpu.dcache.overall_hits::total 625 # number of overall hits
615 system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses
616 system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses
617 system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
618 system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
619 system.cpu.dcache.demand_misses::cpu.data 106 # number of demand (read+write) misses
620 system.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses
621 system.cpu.dcache.overall_misses::cpu.data 106 # number of overall misses
622 system.cpu.dcache.overall_misses::total 106 # number of overall misses
623 system.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles
624 system.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles
625 system.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles
626 system.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles
627 system.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles
628 system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles
629 system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles
630 system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles
631 system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses)
632 system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses)
633 system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses)
634 system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
635 system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses
636 system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses
637 system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses
638 system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses
639 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses
640 system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses
641 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses
642 system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses
643 system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses
644 system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses
645 system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses
646 system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses
647 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency
648 system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency
649 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency
650 system.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency
651 system.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency
652 system.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency
653 system.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency
654 system.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency
655 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
656 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
657 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
658 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
659 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
660 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
661 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
662 system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
663 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits
664 system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits
665 system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits
666 system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
667 system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits
668 system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits
669 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses
670 system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses
671 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses
672 system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses
673 system.cpu.dcache.demand_mshr_misses::cpu.data 34 # number of demand (read+write) MSHR misses
674 system.cpu.dcache.demand_mshr_misses::total 34 # number of demand (read+write) MSHR misses
675 system.cpu.dcache.overall_mshr_misses::cpu.data 34 # number of overall MSHR misses
676 system.cpu.dcache.overall_mshr_misses::total 34 # number of overall MSHR misses
677 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles
678 system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles
679 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles
680 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles
681 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles
682 system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles
683 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles
684 system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles
685 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses
686 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
687 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses
688 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses
689 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses
690 system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses
691 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses
692 system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses
693 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency
694 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency
695 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency
696 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79527.777778 # average WriteReq mshr miss latency
697 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency
698 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency
699 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency
700 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency
701 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
702 system.cpu.icache.tags.replacements 0 # number of replacements
703 system.cpu.icache.tags.tagsinuse 76.387250 # Cycle average of tags in use
704 system.cpu.icache.tags.total_refs 579 # Total number of references to valid blocks.
705 system.cpu.icache.tags.sampled_refs 151 # Sample count of references to valid blocks.
706 system.cpu.icache.tags.avg_refs 3.834437 # Average number of references to valid blocks.
707 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
708 system.cpu.icache.tags.occ_blocks::cpu.inst 76.387250 # Average occupied blocks per requestor
709 system.cpu.icache.tags.occ_percent::cpu.inst 0.037298 # Average percentage of cache occupancy
710 system.cpu.icache.tags.occ_percent::total 0.037298 # Average percentage of cache occupancy
711 system.cpu.icache.tags.occ_task_id_blocks::1024 151 # Occupied blocks per task id
712 system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
713 system.cpu.icache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id
714 system.cpu.icache.tags.tag_accesses 1753 # Number of tag accesses
715 system.cpu.icache.tags.data_accesses 1753 # Number of data accesses
716 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
717 system.cpu.icache.ReadReq_hits::cpu.inst 579 # number of ReadReq hits
718 system.cpu.icache.ReadReq_hits::total 579 # number of ReadReq hits
719 system.cpu.icache.demand_hits::cpu.inst 579 # number of demand (read+write) hits
720 system.cpu.icache.demand_hits::total 579 # number of demand (read+write) hits
721 system.cpu.icache.overall_hits::cpu.inst 579 # number of overall hits
722 system.cpu.icache.overall_hits::total 579 # number of overall hits
723 system.cpu.icache.ReadReq_misses::cpu.inst 222 # number of ReadReq misses
724 system.cpu.icache.ReadReq_misses::total 222 # number of ReadReq misses
725 system.cpu.icache.demand_misses::cpu.inst 222 # number of demand (read+write) misses
726 system.cpu.icache.demand_misses::total 222 # number of demand (read+write) misses
727 system.cpu.icache.overall_misses::cpu.inst 222 # number of overall misses
728 system.cpu.icache.overall_misses::total 222 # number of overall misses
729 system.cpu.icache.ReadReq_miss_latency::cpu.inst 16076000 # number of ReadReq miss cycles
730 system.cpu.icache.ReadReq_miss_latency::total 16076000 # number of ReadReq miss cycles
731 system.cpu.icache.demand_miss_latency::cpu.inst 16076000 # number of demand (read+write) miss cycles
732 system.cpu.icache.demand_miss_latency::total 16076000 # number of demand (read+write) miss cycles
733 system.cpu.icache.overall_miss_latency::cpu.inst 16076000 # number of overall miss cycles
734 system.cpu.icache.overall_miss_latency::total 16076000 # number of overall miss cycles
735 system.cpu.icache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses)
736 system.cpu.icache.ReadReq_accesses::total 801 # number of ReadReq accesses(hits+misses)
737 system.cpu.icache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
738 system.cpu.icache.demand_accesses::total 801 # number of demand (read+write) accesses
739 system.cpu.icache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
740 system.cpu.icache.overall_accesses::total 801 # number of overall (read+write) accesses
741 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.277154 # miss rate for ReadReq accesses
742 system.cpu.icache.ReadReq_miss_rate::total 0.277154 # miss rate for ReadReq accesses
743 system.cpu.icache.demand_miss_rate::cpu.inst 0.277154 # miss rate for demand accesses
744 system.cpu.icache.demand_miss_rate::total 0.277154 # miss rate for demand accesses
745 system.cpu.icache.overall_miss_rate::cpu.inst 0.277154 # miss rate for overall accesses
746 system.cpu.icache.overall_miss_rate::total 0.277154 # miss rate for overall accesses
747 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72414.414414 # average ReadReq miss latency
748 system.cpu.icache.ReadReq_avg_miss_latency::total 72414.414414 # average ReadReq miss latency
749 system.cpu.icache.demand_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency
750 system.cpu.icache.demand_avg_miss_latency::total 72414.414414 # average overall miss latency
751 system.cpu.icache.overall_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency
752 system.cpu.icache.overall_avg_miss_latency::total 72414.414414 # average overall miss latency
753 system.cpu.icache.blocked_cycles::no_mshrs 447 # number of cycles access was blocked
754 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
755 system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
756 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
757 system.cpu.icache.avg_blocked_cycles::no_mshrs 89.400000 # average number of cycles each access was blocked
758 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
759 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
760 system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
761 system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
762 system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
763 system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
764 system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
765 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 153 # number of ReadReq MSHR misses
766 system.cpu.icache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses
767 system.cpu.icache.demand_mshr_misses::cpu.inst 153 # number of demand (read+write) MSHR misses
768 system.cpu.icache.demand_mshr_misses::total 153 # number of demand (read+write) MSHR misses
769 system.cpu.icache.overall_mshr_misses::cpu.inst 153 # number of overall MSHR misses
770 system.cpu.icache.overall_mshr_misses::total 153 # number of overall MSHR misses
771 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11858500 # number of ReadReq MSHR miss cycles
772 system.cpu.icache.ReadReq_mshr_miss_latency::total 11858500 # number of ReadReq MSHR miss cycles
773 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11858500 # number of demand (read+write) MSHR miss cycles
774 system.cpu.icache.demand_mshr_miss_latency::total 11858500 # number of demand (read+write) MSHR miss cycles
775 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11858500 # number of overall MSHR miss cycles
776 system.cpu.icache.overall_mshr_miss_latency::total 11858500 # number of overall MSHR miss cycles
777 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for ReadReq accesses
778 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191011 # mshr miss rate for ReadReq accesses
779 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for demand accesses
780 system.cpu.icache.demand_mshr_miss_rate::total 0.191011 # mshr miss rate for demand accesses
781 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for overall accesses
782 system.cpu.icache.overall_mshr_miss_rate::total 0.191011 # mshr miss rate for overall accesses
783 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77506.535948 # average ReadReq mshr miss latency
784 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77506.535948 # average ReadReq mshr miss latency
785 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency
786 system.cpu.icache.demand_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency
787 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency
788 system.cpu.icache.overall_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency
789 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
790 system.cpu.l2cache.tags.replacements 0 # number of replacements
791 system.cpu.l2cache.tags.tagsinuse 99.069725 # Cycle average of tags in use
792 system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
793 system.cpu.l2cache.tags.sampled_refs 182 # Sample count of references to valid blocks.
794 system.cpu.l2cache.tags.avg_refs 0.010989 # Average number of references to valid blocks.
795 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
796 system.cpu.l2cache.tags.occ_blocks::cpu.inst 75.716364 # Average occupied blocks per requestor
797 system.cpu.l2cache.tags.occ_blocks::cpu.data 23.353361 # Average occupied blocks per requestor
798 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002311 # Average percentage of cache occupancy
799 system.cpu.l2cache.tags.occ_percent::cpu.data 0.000713 # Average percentage of cache occupancy
800 system.cpu.l2cache.tags.occ_percent::total 0.003023 # Average percentage of cache occupancy
801 system.cpu.l2cache.tags.occ_task_id_blocks::1024 182 # Occupied blocks per task id
802 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
803 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005554 # Percentage of cache occupancy per task id
804 system.cpu.l2cache.tags.tag_accesses 1678 # Number of tag accesses
805 system.cpu.l2cache.tags.data_accesses 1678 # Number of data accesses
806 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
807 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
808 system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
809 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
810 system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
811 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
812 system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
813 system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
814 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
815 system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
816 system.cpu.l2cache.overall_hits::total 2 # number of overall hits
817 system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses
818 system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses
819 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 152 # number of ReadCleanReq misses
820 system.cpu.l2cache.ReadCleanReq_misses::total 152 # number of ReadCleanReq misses
821 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses
822 system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses
823 system.cpu.l2cache.demand_misses::cpu.inst 152 # number of demand (read+write) misses
824 system.cpu.l2cache.demand_misses::cpu.data 33 # number of demand (read+write) misses
825 system.cpu.l2cache.demand_misses::total 185 # number of demand (read+write) misses
826 system.cpu.l2cache.overall_misses::cpu.inst 152 # number of overall misses
827 system.cpu.l2cache.overall_misses::cpu.data 33 # number of overall misses
828 system.cpu.l2cache.overall_misses::total 185 # number of overall misses
829 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404500 # number of ReadExReq miss cycles
830 system.cpu.l2cache.ReadExReq_miss_latency::total 1404500 # number of ReadExReq miss cycles
831 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11620000 # number of ReadCleanReq miss cycles
832 system.cpu.l2cache.ReadCleanReq_miss_latency::total 11620000 # number of ReadCleanReq miss cycles
833 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1106000 # number of ReadSharedReq miss cycles
834 system.cpu.l2cache.ReadSharedReq_miss_latency::total 1106000 # number of ReadSharedReq miss cycles
835 system.cpu.l2cache.demand_miss_latency::cpu.inst 11620000 # number of demand (read+write) miss cycles
836 system.cpu.l2cache.demand_miss_latency::cpu.data 2510500 # number of demand (read+write) miss cycles
837 system.cpu.l2cache.demand_miss_latency::total 14130500 # number of demand (read+write) miss cycles
838 system.cpu.l2cache.overall_miss_latency::cpu.inst 11620000 # number of overall miss cycles
839 system.cpu.l2cache.overall_miss_latency::cpu.data 2510500 # number of overall miss cycles
840 system.cpu.l2cache.overall_miss_latency::total 14130500 # number of overall miss cycles
841 system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses)
842 system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses)
843 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 153 # number of ReadCleanReq accesses(hits+misses)
844 system.cpu.l2cache.ReadCleanReq_accesses::total 153 # number of ReadCleanReq accesses(hits+misses)
845 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses)
846 system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses)
847 system.cpu.l2cache.demand_accesses::cpu.inst 153 # number of demand (read+write) accesses
848 system.cpu.l2cache.demand_accesses::cpu.data 34 # number of demand (read+write) accesses
849 system.cpu.l2cache.demand_accesses::total 187 # number of demand (read+write) accesses
850 system.cpu.l2cache.overall_accesses::cpu.inst 153 # number of overall (read+write) accesses
851 system.cpu.l2cache.overall_accesses::cpu.data 34 # number of overall (read+write) accesses
852 system.cpu.l2cache.overall_accesses::total 187 # number of overall (read+write) accesses
853 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
854 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
855 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993464 # miss rate for ReadCleanReq accesses
856 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993464 # miss rate for ReadCleanReq accesses
857 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses
858 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses
859 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993464 # miss rate for demand accesses
860 system.cpu.l2cache.demand_miss_rate::cpu.data 0.970588 # miss rate for demand accesses
861 system.cpu.l2cache.demand_miss_rate::total 0.989305 # miss rate for demand accesses
862 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993464 # miss rate for overall accesses
863 system.cpu.l2cache.overall_miss_rate::cpu.data 0.970588 # miss rate for overall accesses
864 system.cpu.l2cache.overall_miss_rate::total 0.989305 # miss rate for overall accesses
865 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78027.777778 # average ReadExReq miss latency
866 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78027.777778 # average ReadExReq miss latency
867 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76447.368421 # average ReadCleanReq miss latency
868 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76447.368421 # average ReadCleanReq miss latency
869 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73733.333333 # average ReadSharedReq miss latency
870 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73733.333333 # average ReadSharedReq miss latency
871 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency
872 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency
873 system.cpu.l2cache.demand_avg_miss_latency::total 76381.081081 # average overall miss latency
874 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency
875 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency
876 system.cpu.l2cache.overall_avg_miss_latency::total 76381.081081 # average overall miss latency
877 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
878 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
879 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
880 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
881 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
882 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
883 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses
884 system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses
885 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 152 # number of ReadCleanReq MSHR misses
886 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 152 # number of ReadCleanReq MSHR misses
887 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses
888 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses
889 system.cpu.l2cache.demand_mshr_misses::cpu.inst 152 # number of demand (read+write) MSHR misses
890 system.cpu.l2cache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses
891 system.cpu.l2cache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses
892 system.cpu.l2cache.overall_mshr_misses::cpu.inst 152 # number of overall MSHR misses
893 system.cpu.l2cache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses
894 system.cpu.l2cache.overall_mshr_misses::total 185 # number of overall MSHR misses
895 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1224500 # number of ReadExReq MSHR miss cycles
896 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1224500 # number of ReadExReq MSHR miss cycles
897 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10120000 # number of ReadCleanReq MSHR miss cycles
898 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10120000 # number of ReadCleanReq MSHR miss cycles
899 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 966000 # number of ReadSharedReq MSHR miss cycles
900 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 966000 # number of ReadSharedReq MSHR miss cycles
901 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10120000 # number of demand (read+write) MSHR miss cycles
902 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2190500 # number of demand (read+write) MSHR miss cycles
903 system.cpu.l2cache.demand_mshr_miss_latency::total 12310500 # number of demand (read+write) MSHR miss cycles
904 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10120000 # number of overall MSHR miss cycles
905 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2190500 # number of overall MSHR miss cycles
906 system.cpu.l2cache.overall_mshr_miss_latency::total 12310500 # number of overall MSHR miss cycles
907 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
908 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
909 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for ReadCleanReq accesses
910 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993464 # mshr miss rate for ReadCleanReq accesses
911 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses
912 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses
913 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for demand accesses
914 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for demand accesses
915 system.cpu.l2cache.demand_mshr_miss_rate::total 0.989305 # mshr miss rate for demand accesses
916 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for overall accesses
917 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for overall accesses
918 system.cpu.l2cache.overall_mshr_miss_rate::total 0.989305 # mshr miss rate for overall accesses
919 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68027.777778 # average ReadExReq mshr miss latency
920 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68027.777778 # average ReadExReq mshr miss latency
921 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66578.947368 # average ReadCleanReq mshr miss latency
922 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66578.947368 # average ReadCleanReq mshr miss latency
923 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64400 # average ReadSharedReq mshr miss latency
924 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64400 # average ReadSharedReq mshr miss latency
925 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency
926 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency
927 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency
928 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency
929 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency
930 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency
931 system.cpu.toL2Bus.snoop_filter.tot_requests 187 # Total number of requests made to the snoop filter.
932 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
933 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
934 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
935 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
936 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
937 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
938 system.cpu.toL2Bus.trans_dist::ReadResp 166 # Transaction distribution
939 system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution
940 system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution
941 system.cpu.toL2Bus.trans_dist::ReadCleanReq 153 # Transaction distribution
942 system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution
943 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 304 # Packet count per connected master and slave (bytes)
944 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 67 # Packet count per connected master and slave (bytes)
945 system.cpu.toL2Bus.pkt_count::total 371 # Packet count per connected master and slave (bytes)
946 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9664 # Cumulative packet size per connected master and slave (bytes)
947 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes)
948 system.cpu.toL2Bus.pkt_size::total 11776 # Cumulative packet size per connected master and slave (bytes)
949 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
950 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
951 system.cpu.toL2Bus.snoop_fanout::samples 187 # Request fanout histogram
952 system.cpu.toL2Bus.snoop_fanout::mean 0.010695 # Request fanout histogram
953 system.cpu.toL2Bus.snoop_fanout::stdev 0.103139 # Request fanout histogram
954 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
955 system.cpu.toL2Bus.snoop_fanout::0 185 98.93% 98.93% # Request fanout histogram
956 system.cpu.toL2Bus.snoop_fanout::1 2 1.07% 100.00% # Request fanout histogram
957 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
958 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
959 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
960 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
961 system.cpu.toL2Bus.snoop_fanout::total 187 # Request fanout histogram
962 system.cpu.toL2Bus.reqLayer0.occupancy 93500 # Layer occupancy (ticks)
963 system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
964 system.cpu.toL2Bus.respLayer0.occupancy 226500 # Layer occupancy (ticks)
965 system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
966 system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks)
967 system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
968 system.membus.snoop_filter.tot_requests 184 # Total number of requests made to the snoop filter.
969 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
970 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
971 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
972 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
973 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
974 system.membus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
975 system.membus.trans_dist::ReadResp 164 # Transaction distribution
976 system.membus.trans_dist::ReadExReq 18 # Transaction distribution
977 system.membus.trans_dist::ReadExResp 18 # Transaction distribution
978 system.membus.trans_dist::ReadSharedReq 166 # Transaction distribution
979 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 366 # Packet count per connected master and slave (bytes)
980 system.membus.pkt_count::total 366 # Packet count per connected master and slave (bytes)
981 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 11648 # Cumulative packet size per connected master and slave (bytes)
982 system.membus.pkt_size::total 11648 # Cumulative packet size per connected master and slave (bytes)
983 system.membus.snoops 0 # Total snoops (count)
984 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
985 system.membus.snoop_fanout::samples 184 # Request fanout histogram
986 system.membus.snoop_fanout::mean 0 # Request fanout histogram
987 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
988 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
989 system.membus.snoop_fanout::0 184 100.00% 100.00% # Request fanout histogram
990 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
991 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
992 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
993 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
994 system.membus.snoop_fanout::total 184 # Request fanout histogram
995 system.membus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
996 system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
997 system.membus.respLayer1.occupancy 948750 # Layer occupancy (ticks)
998 system.membus.respLayer1.utilization 11.9 # Layer utilization (%)
1000 ---------- End Simulation Statistics ----------
projects / gem5.git / blob