6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
11 children=cpu membus physmem
15 load_addr_mask=1099511627775
17 memories=system.physmem
19 physmem=system.physmem
22 work_begin_ckpt_count=0
23 work_begin_cpu_id_exit=-1
24 work_begin_exit_count=0
25 work_cpus_ckpt_count=0
29 system_port=system.membus.port[0]
33 children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
41 choicePredictorSize=8192
44 dataMemPort=dcache_port
45 defer_registration=false
54 do_checkpoint_insts=true
56 do_statistics_insts=true
59 fetchMemPort=icache_port
63 function_trace_start=0
66 globalPredictorSize=8192
68 interrupts=system.cpu.interrupts
72 localHistoryTableSize=2048
73 localPredictorSize=2048
74 max_insts_all_threads=0
75 max_insts_any_thread=0
76 max_loads_all_threads=0
77 max_loads_any_thread=0
90 tracer=system.cpu.tracer
91 workload=system.cpu.workload
92 dcache_port=system.cpu.dcache.cpu_side
93 icache_port=system.cpu.icache.cpu_side
97 addr_range=0:18446744073709551615
106 prefetch_on_access=false
108 prioritizeRequests=false
117 cpu_side=system.cpu.dcache_port
118 mem_side=system.cpu.toL2Bus.port[1]
126 addr_range=0:18446744073709551615
135 prefetch_on_access=false
137 prioritizeRequests=false
146 cpu_side=system.cpu.icache_port
147 mem_side=system.cpu.toL2Bus.port[0]
149 [system.cpu.interrupts]
158 addr_range=0:18446744073709551615
167 prefetch_on_access=false
169 prioritizeRequests=false
178 cpu_side=system.cpu.toL2Bus.port[2]
179 mem_side=system.membus.port[2]
187 use_default_range=false
189 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
194 [system.cpu.workload]
202 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
205 max_stack_size=67108864
219 use_default_range=false
221 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
231 port=system.membus.port[1]