2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000021 # Number of seconds simulated
4 sim_ticks 20970500 # Number of ticks simulated
5 final_tick 20970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 71497 # Simulator instruction rate (inst/s)
8 host_op_rate 71482 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 281347268 # Simulator tick rate (ticks/s)
10 host_mem_usage 269780 # Number of bytes of host memory used
11 host_seconds 0.07 # Real time elapsed on the host
12 sim_insts 5327 # Number of instructions simulated
13 sim_ops 5327 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 27072 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 882000906 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 408955437 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 1290956343 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 882000906 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 882000906 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 882000906 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 408955437 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 1290956343 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 423 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 24 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 7 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 1 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 8 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 0 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 78 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 80 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 62 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 35 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 18 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 10 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 52 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 12 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 21 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 7 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 8 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 20901000 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 423 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 48 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 337.333333 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 221.579222 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 300.401245 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 13 27.08% 27.08% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 9 18.75% 45.83% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 6 12.50% 58.33% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 7 14.58% 72.92% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 6 12.50% 85.42% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 2 4.17% 89.58% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::1024-1151 5 10.42% 100.00% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::total 48 # Bytes accessed per row activation
201 system.physmem.totQLat 3113750 # Total ticks spent queuing
202 system.physmem.totMemAccLat 11732500 # Total ticks spent from burst creation until serviced by the DRAM
203 system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers
204 system.physmem.totBankLat 6503750 # Total ticks spent accessing banks
205 system.physmem.avgQLat 7361.11 # Average queueing delay per DRAM burst
206 system.physmem.avgBankLat 15375.30 # Average bank access latency per DRAM burst
207 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208 system.physmem.avgMemAccLat 27736.41 # Average memory access latency per DRAM burst
209 system.physmem.avgRdBW 1290.96 # Average DRAM read bandwidth in MiByte/s
210 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211 system.physmem.avgRdBWSys 1290.96 # Average system read bandwidth in MiByte/s
212 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214 system.physmem.busUtil 10.09 # Data bus utilization in percentage
215 system.physmem.busUtilRead 10.09 # Data bus utilization in percentage for reads
216 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217 system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
218 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219 system.physmem.readRowHits 339 # Number of row buffer hits during reads
220 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221 system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads
222 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223 system.physmem.avgGap 49411.35 # Average gap between requests
224 system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
225 system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
226 system.membus.throughput 1290956343 # Throughput (bytes/s)
227 system.membus.trans_dist::ReadReq 342 # Transaction distribution
228 system.membus.trans_dist::ReadResp 342 # Transaction distribution
229 system.membus.trans_dist::ReadExReq 81 # Transaction distribution
230 system.membus.trans_dist::ReadExResp 81 # Transaction distribution
231 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes)
232 system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
233 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
234 system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
235 system.membus.data_through_bus 27072 # Total data (bytes)
236 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
237 system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks)
238 system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
239 system.membus.respLayer1.occupancy 3929500 # Layer occupancy (ticks)
240 system.membus.respLayer1.utilization 18.7 # Layer utilization (%)
241 system.cpu_clk_domain.clock 500 # Clock period in ticks
242 system.cpu.branchPred.lookups 1636 # Number of BP lookups
243 system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
244 system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
245 system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups
246 system.cpu.branchPred.BTBHits 584 # Number of BTB hits
247 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
248 system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
249 system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
250 system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
251 system.cpu.workload.num_syscalls 11 # Number of system calls
252 system.cpu.numCycles 41942 # number of cpu cycles simulated
253 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
254 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
255 system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
256 system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
257 system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File
258 system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
259 system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File
260 system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
261 system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
262 system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
263 system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic
264 system.cpu.agen_unit.agens 1472 # Number of Address Generations
265 system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken.
266 system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken).
267 system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted
268 system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted
269 system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts
270 system.cpu.execution_unit.executions 3957 # Number of Instructions Executed.
271 system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
272 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
273 system.cpu.contextSwitches 1 # Number of context switches
274 system.cpu.threadCycles 9659 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
275 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
276 system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself
277 system.cpu.idleCycles 35694 # Number of cycles cpu's stages were not processed
278 system.cpu.runCycles 6248 # Number of cycles cpu stages are processed.
279 system.cpu.activity 14.896762 # Percentage of cycles cpu is active
280 system.cpu.comLoads 715 # Number of Load instructions committed
281 system.cpu.comStores 673 # Number of Store instructions committed
282 system.cpu.comBranches 1115 # Number of Branches instructions committed
283 system.cpu.comNops 173 # Number of Nop instructions committed
284 system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
285 system.cpu.comInts 2526 # Number of Integer instructions committed
286 system.cpu.comFloats 0 # Number of Floating Point instructions committed
287 system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread)
288 system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
289 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
290 system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
291 system.cpu.cpi 7.873475 # CPI: Cycles Per Instruction (Per-Thread)
292 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
293 system.cpu.cpi_total 7.873475 # CPI: Total CPI of All Threads
294 system.cpu.ipc 0.127009 # IPC: Instructions Per Cycle (Per-Thread)
295 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
296 system.cpu.ipc_total 0.127009 # IPC: Total IPC of All Threads
297 system.cpu.stage0.idleCycles 37302 # Number of cycles 0 instructions are processed.
298 system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
299 system.cpu.stage0.utilization 11.062896 # Percentage of cycles stage was utilized (processing insts).
300 system.cpu.stage1.idleCycles 38748 # Number of cycles 0 instructions are processed.
301 system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed.
302 system.cpu.stage1.utilization 7.615278 # Percentage of cycles stage was utilized (processing insts).
303 system.cpu.stage2.idleCycles 38908 # Number of cycles 0 instructions are processed.
304 system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed.
305 system.cpu.stage2.utilization 7.233799 # Percentage of cycles stage was utilized (processing insts).
306 system.cpu.stage3.idleCycles 40966 # Number of cycles 0 instructions are processed.
307 system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed.
308 system.cpu.stage3.utilization 2.327023 # Percentage of cycles stage was utilized (processing insts).
309 system.cpu.stage4.idleCycles 38785 # Number of cycles 0 instructions are processed.
310 system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
311 system.cpu.stage4.utilization 7.527061 # Percentage of cycles stage was utilized (processing insts).
312 system.cpu.icache.tags.replacements 0 # number of replacements
313 system.cpu.icache.tags.tagsinuse 142.644710 # Cycle average of tags in use
314 system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
315 system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
316 system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
317 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
318 system.cpu.icache.tags.occ_blocks::cpu.inst 142.644710 # Average occupied blocks per requestor
319 system.cpu.icache.tags.occ_percent::cpu.inst 0.069651 # Average percentage of cache occupancy
320 system.cpu.icache.tags.occ_percent::total 0.069651 # Average percentage of cache occupancy
321 system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id
322 system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
323 system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
324 system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id
325 system.cpu.icache.tags.tag_accesses 2807 # Number of tag accesses
326 system.cpu.icache.tags.data_accesses 2807 # Number of data accesses
327 system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits
328 system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits
329 system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits
330 system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits
331 system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits
332 system.cpu.icache.overall_hits::total 892 # number of overall hits
333 system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
334 system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
335 system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
336 system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
337 system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
338 system.cpu.icache.overall_misses::total 366 # number of overall misses
339 system.cpu.icache.ReadReq_miss_latency::cpu.inst 25482750 # number of ReadReq miss cycles
340 system.cpu.icache.ReadReq_miss_latency::total 25482750 # number of ReadReq miss cycles
341 system.cpu.icache.demand_miss_latency::cpu.inst 25482750 # number of demand (read+write) miss cycles
342 system.cpu.icache.demand_miss_latency::total 25482750 # number of demand (read+write) miss cycles
343 system.cpu.icache.overall_miss_latency::cpu.inst 25482750 # number of overall miss cycles
344 system.cpu.icache.overall_miss_latency::total 25482750 # number of overall miss cycles
345 system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
346 system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
347 system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
348 system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses
349 system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses
350 system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses
351 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.290938 # miss rate for ReadReq accesses
352 system.cpu.icache.ReadReq_miss_rate::total 0.290938 # miss rate for ReadReq accesses
353 system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 # miss rate for demand accesses
354 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses
355 system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses
356 system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses
357 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69625 # average ReadReq miss latency
358 system.cpu.icache.ReadReq_avg_miss_latency::total 69625 # average ReadReq miss latency
359 system.cpu.icache.demand_avg_miss_latency::cpu.inst 69625 # average overall miss latency
360 system.cpu.icache.demand_avg_miss_latency::total 69625 # average overall miss latency
361 system.cpu.icache.overall_avg_miss_latency::cpu.inst 69625 # average overall miss latency
362 system.cpu.icache.overall_avg_miss_latency::total 69625 # average overall miss latency
363 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
364 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
365 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
366 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
367 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
368 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
369 system.cpu.icache.fast_writes 0 # number of fast writes performed
370 system.cpu.icache.cache_copies 0 # number of cache copies performed
371 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits
372 system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
373 system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits
374 system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
375 system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits
376 system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
377 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
378 system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
379 system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
380 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
381 system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
382 system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
383 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20711750 # number of ReadReq MSHR miss cycles
384 system.cpu.icache.ReadReq_mshr_miss_latency::total 20711750 # number of ReadReq MSHR miss cycles
385 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20711750 # number of demand (read+write) MSHR miss cycles
386 system.cpu.icache.demand_mshr_miss_latency::total 20711750 # number of demand (read+write) MSHR miss cycles
387 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20711750 # number of overall MSHR miss cycles
388 system.cpu.icache.overall_mshr_miss_latency::total 20711750 # number of overall MSHR miss cycles
389 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
390 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
391 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
392 system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
393 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
394 system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
395 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625 # average ReadReq mshr miss latency
396 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625 # average ReadReq mshr miss latency
397 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency
398 system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency
399 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency
400 system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency
401 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
402 system.cpu.toL2Bus.throughput 1300112062 # Throughput (bytes/s)
403 system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
404 system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
405 system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
406 system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
407 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
408 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
409 system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes)
410 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
411 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
412 system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes)
413 system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes)
414 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
415 system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
416 system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
417 system.cpu.toL2Bus.respLayer0.occupancy 485750 # Layer occupancy (ticks)
418 system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
419 system.cpu.toL2Bus.respLayer1.occupancy 216250 # Layer occupancy (ticks)
420 system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
421 system.cpu.l2cache.tags.replacements 0 # number of replacements
422 system.cpu.l2cache.tags.tagsinuse 169.087834 # Cycle average of tags in use
423 system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
424 system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks.
425 system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks.
426 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
427 system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.075458 # Average occupied blocks per requestor
428 system.cpu.l2cache.tags.occ_blocks::cpu.data 27.012376 # Average occupied blocks per requestor
429 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004336 # Average percentage of cache occupancy
430 system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
431 system.cpu.l2cache.tags.occ_percent::total 0.005160 # Average percentage of cache occupancy
432 system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id
433 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
434 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
435 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id
436 system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses
437 system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses
438 system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
439 system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
440 system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
441 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
442 system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
443 system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
444 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
445 system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
446 system.cpu.l2cache.overall_hits::total 3 # number of overall hits
447 system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses
448 system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
449 system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses
450 system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
451 system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
452 system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses
453 system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
454 system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses
455 system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
456 system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
457 system.cpu.l2cache.overall_misses::total 423 # number of overall misses
458 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20393250 # number of ReadReq miss cycles
459 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4031000 # number of ReadReq miss cycles
460 system.cpu.l2cache.ReadReq_miss_latency::total 24424250 # number of ReadReq miss cycles
461 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6031750 # number of ReadExReq miss cycles
462 system.cpu.l2cache.ReadExReq_miss_latency::total 6031750 # number of ReadExReq miss cycles
463 system.cpu.l2cache.demand_miss_latency::cpu.inst 20393250 # number of demand (read+write) miss cycles
464 system.cpu.l2cache.demand_miss_latency::cpu.data 10062750 # number of demand (read+write) miss cycles
465 system.cpu.l2cache.demand_miss_latency::total 30456000 # number of demand (read+write) miss cycles
466 system.cpu.l2cache.overall_miss_latency::cpu.inst 20393250 # number of overall miss cycles
467 system.cpu.l2cache.overall_miss_latency::cpu.data 10062750 # number of overall miss cycles
468 system.cpu.l2cache.overall_miss_latency::total 30456000 # number of overall miss cycles
469 system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
470 system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
471 system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
472 system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
473 system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
474 system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
475 system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
476 system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses
477 system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
478 system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
479 system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses
480 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses
481 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
482 system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses
483 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
484 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
485 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses
486 system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
487 system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses
488 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
489 system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
490 system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
491 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893 # average ReadReq miss latency
492 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774 # average ReadReq miss latency
493 system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673 # average ReadReq miss latency
494 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383 # average ReadExReq miss latency
495 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383 # average ReadExReq miss latency
496 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency
497 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency
498 system.cpu.l2cache.demand_avg_miss_latency::total 72000 # average overall miss latency
499 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency
500 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency
501 system.cpu.l2cache.overall_avg_miss_latency::total 72000 # average overall miss latency
502 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
503 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
504 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
505 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
506 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
507 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
508 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
509 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
510 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses
511 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
512 system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
513 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
514 system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
515 system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
516 system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
517 system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses
518 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
519 system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
520 system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
521 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16781250 # number of ReadReq MSHR miss cycles
522 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3376000 # number of ReadReq MSHR miss cycles
523 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20157250 # number of ReadReq MSHR miss cycles
524 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5037250 # number of ReadExReq MSHR miss cycles
525 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5037250 # number of ReadExReq MSHR miss cycles
526 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16781250 # number of demand (read+write) MSHR miss cycles
527 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413250 # number of demand (read+write) MSHR miss cycles
528 system.cpu.l2cache.demand_mshr_miss_latency::total 25194500 # number of demand (read+write) MSHR miss cycles
529 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16781250 # number of overall MSHR miss cycles
530 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413250 # number of overall MSHR miss cycles
531 system.cpu.l2cache.overall_mshr_miss_latency::total 25194500 # number of overall MSHR miss cycles
532 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
533 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
534 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
535 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
536 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
537 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses
538 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
539 system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses
540 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
541 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
542 system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
543 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997 # average ReadReq mshr miss latency
544 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208 # average ReadReq mshr miss latency
545 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485 # average ReadReq mshr miss latency
546 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605 # average ReadExReq mshr miss latency
547 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605 # average ReadExReq mshr miss latency
548 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency
549 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency
550 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency
551 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency
552 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency
553 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency
554 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
555 system.cpu.dcache.tags.replacements 0 # number of replacements
556 system.cpu.dcache.tags.tagsinuse 85.369033 # Cycle average of tags in use
557 system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
558 system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
559 system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
560 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
561 system.cpu.dcache.tags.occ_blocks::cpu.data 85.369033 # Average occupied blocks per requestor
562 system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy
563 system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy
564 system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
565 system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
566 system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
567 system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
568 system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
569 system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
570 system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
571 system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
572 system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
573 system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
574 system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
575 system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
576 system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
577 system.cpu.dcache.overall_hits::total 914 # number of overall hits
578 system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
579 system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
580 system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
581 system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
582 system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
583 system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
584 system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
585 system.cpu.dcache.overall_misses::total 474 # number of overall misses
586 system.cpu.dcache.ReadReq_miss_latency::cpu.data 4594750 # number of ReadReq miss cycles
587 system.cpu.dcache.ReadReq_miss_latency::total 4594750 # number of ReadReq miss cycles
588 system.cpu.dcache.WriteReq_miss_latency::cpu.data 29091500 # number of WriteReq miss cycles
589 system.cpu.dcache.WriteReq_miss_latency::total 29091500 # number of WriteReq miss cycles
590 system.cpu.dcache.demand_miss_latency::cpu.data 33686250 # number of demand (read+write) miss cycles
591 system.cpu.dcache.demand_miss_latency::total 33686250 # number of demand (read+write) miss cycles
592 system.cpu.dcache.overall_miss_latency::cpu.data 33686250 # number of overall miss cycles
593 system.cpu.dcache.overall_miss_latency::total 33686250 # number of overall miss cycles
594 system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
595 system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
596 system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
597 system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
598 system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
599 system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
600 system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
601 system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
602 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
603 system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
604 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
605 system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
606 system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
607 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
608 system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
609 system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
610 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492 # average ReadReq miss latency
611 system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492 # average ReadReq miss latency
612 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312 # average WriteReq miss latency
613 system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312 # average WriteReq miss latency
614 system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency
615 system.cpu.dcache.demand_avg_miss_latency::total 71068.037975 # average overall miss latency
616 system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency
617 system.cpu.dcache.overall_avg_miss_latency::total 71068.037975 # average overall miss latency
618 system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked
619 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
620 system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
621 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
622 system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked
623 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
624 system.cpu.dcache.fast_writes 0 # number of fast writes performed
625 system.cpu.dcache.cache_copies 0 # number of cache copies performed
626 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
627 system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
628 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
629 system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
630 system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
631 system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
632 system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
633 system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
634 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
635 system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
636 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
637 system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
638 system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
639 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
640 system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
641 system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
642 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4097500 # number of ReadReq MSHR miss cycles
643 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4097500 # number of ReadReq MSHR miss cycles
644 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6115250 # number of WriteReq MSHR miss cycles
645 system.cpu.dcache.WriteReq_mshr_miss_latency::total 6115250 # number of WriteReq MSHR miss cycles
646 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10212750 # number of demand (read+write) MSHR miss cycles
647 system.cpu.dcache.demand_mshr_miss_latency::total 10212750 # number of demand (read+write) MSHR miss cycles
648 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10212750 # number of overall MSHR miss cycles
649 system.cpu.dcache.overall_mshr_miss_latency::total 10212750 # number of overall MSHR miss cycles
650 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
651 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
652 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
653 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
654 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
655 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
656 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
657 system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
658 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630 # average ReadReq mshr miss latency
659 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630 # average ReadReq mshr miss latency
660 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580 # average WriteReq mshr miss latency
661 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580 # average WriteReq mshr miss latency
662 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency
663 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency
664 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency
665 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency
666 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
668 ---------- End Simulation Statistics ----------
projects / gem5.git / blob