2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000028 # Number of seconds simulated
4 sim_ticks 27800500 # Number of ticks simulated
5 final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 428112 # Simulator instruction rate (inst/s)
8 host_op_rate 427631 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2229390537 # Simulator tick rate (ticks/s)
10 host_mem_usage 290104 # Number of bytes of host memory used
11 host_seconds 0.01 # Real time elapsed on the host
12 sim_insts 5327 # Number of instructions simulated
13 sim_ops 5327 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
32 system.cpu_clk_domain.clock 500 # Clock period in ticks
33 system.cpu.workload.num_syscalls 11 # Number of system calls
34 system.cpu.numCycles 55601 # number of cpu cycles simulated
35 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37 system.cpu.committedInsts 5327 # Number of instructions committed
38 system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
39 system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
40 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
41 system.cpu.num_func_calls 146 # number of times a function call or return occured
42 system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
43 system.cpu.num_int_insts 4505 # number of integer instructions
44 system.cpu.num_fp_insts 0 # number of float instructions
45 system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
46 system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
47 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
48 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
49 system.cpu.num_mem_refs 1401 # number of memory refs
50 system.cpu.num_load_insts 723 # Number of load instructions
51 system.cpu.num_store_insts 678 # Number of store instructions
52 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
53 system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
54 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56 system.cpu.Branches 1121 # Number of branches fetched
57 system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
58 system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
59 system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction
60 system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction
61 system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction
62 system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction
63 system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction
64 system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction
65 system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction
66 system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction
67 system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction
68 system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction
69 system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction
70 system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction
71 system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction
72 system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction
73 system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction
74 system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction
75 system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction
76 system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction
77 system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction
78 system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction
79 system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction
80 system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction
81 system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction
82 system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction
83 system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction
84 system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction
85 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction
86 system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction
87 system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction
88 system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction
89 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91 system.cpu.op_class::total 5370 # Class of executed instruction
92 system.cpu.dcache.tags.replacements 0 # number of replacements
93 system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use
94 system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
95 system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
96 system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
97 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
98 system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor
99 system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
100 system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
101 system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
102 system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
103 system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
104 system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
105 system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
106 system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
107 system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
108 system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
109 system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
110 system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
111 system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
112 system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
113 system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
114 system.cpu.dcache.overall_hits::total 1253 # number of overall hits
115 system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
116 system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
117 system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
118 system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
119 system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
120 system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
121 system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
122 system.cpu.dcache.overall_misses::total 135 # number of overall misses
123 system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
124 system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
125 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
126 system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
127 system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
128 system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
129 system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
130 system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
131 system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
132 system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
133 system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
134 system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
135 system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
136 system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
137 system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
138 system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
139 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
140 system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
141 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
142 system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
143 system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
144 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
145 system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
146 system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
147 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
148 system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
149 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
150 system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
151 system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
152 system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
153 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
154 system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
155 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
156 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
157 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
158 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
159 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
160 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
161 system.cpu.dcache.fast_writes 0 # number of fast writes performed
162 system.cpu.dcache.cache_copies 0 # number of cache copies performed
163 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
164 system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
165 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
166 system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
167 system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
168 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
169 system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
170 system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
171 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles
172 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles
173 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles
174 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles
175 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles
176 system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles
177 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles
178 system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles
179 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
180 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
181 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
182 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
183 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
184 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
185 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
186 system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
187 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency
188 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency
189 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
190 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
191 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
192 system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
193 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
194 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
195 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
196 system.cpu.icache.tags.replacements 0 # number of replacements
197 system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use
198 system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
199 system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
200 system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
201 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
202 system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor
203 system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy
204 system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy
205 system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
206 system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
207 system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
208 system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id
209 system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses
210 system.cpu.icache.tags.data_accesses 10999 # Number of data accesses
211 system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
212 system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
213 system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
214 system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits
215 system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits
216 system.cpu.icache.overall_hits::total 5114 # number of overall hits
217 system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
218 system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
219 system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
220 system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
221 system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
222 system.cpu.icache.overall_misses::total 257 # number of overall misses
223 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
224 system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
225 system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
226 system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
227 system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
228 system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
229 system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
230 system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
231 system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
232 system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses
233 system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses
234 system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses
235 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses
236 system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses
237 system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses
238 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
239 system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
240 system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
241 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
242 system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
243 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
244 system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
245 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
246 system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
247 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
248 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
249 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
250 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
251 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
252 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
253 system.cpu.icache.fast_writes 0 # number of fast writes performed
254 system.cpu.icache.cache_copies 0 # number of cache copies performed
255 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
256 system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
257 system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
258 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
259 system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
260 system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
261 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles
262 system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles
263 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles
264 system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles
265 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles
266 system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles
267 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
268 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
269 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
270 system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
271 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
272 system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
273 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency
274 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency
275 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
276 system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
277 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
278 system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
279 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
280 system.cpu.l2cache.tags.replacements 0 # number of replacements
281 system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use
282 system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
283 system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
284 system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
285 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
286 system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor
287 system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor
288 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy
289 system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
290 system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy
291 system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
292 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
293 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
294 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
295 system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses
296 system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses
297 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
298 system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
299 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
300 system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
301 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
302 system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
303 system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
304 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
305 system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
306 system.cpu.l2cache.overall_hits::total 3 # number of overall hits
307 system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
308 system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
309 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 255 # number of ReadCleanReq misses
310 system.cpu.l2cache.ReadCleanReq_misses::total 255 # number of ReadCleanReq misses
311 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses
312 system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses
313 system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses
314 system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
315 system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses
316 system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
317 system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
318 system.cpu.l2cache.overall_misses::total 389 # number of overall misses
319 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles
320 system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles
321 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles
322 system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles
323 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles
324 system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles
325 system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles
326 system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
327 system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles
328 system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles
329 system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
330 system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles
331 system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
332 system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
333 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses)
334 system.cpu.l2cache.ReadCleanReq_accesses::total 257 # number of ReadCleanReq accesses(hits+misses)
335 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 54 # number of ReadSharedReq accesses(hits+misses)
336 system.cpu.l2cache.ReadSharedReq_accesses::total 54 # number of ReadSharedReq accesses(hits+misses)
337 system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses
338 system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
339 system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses
340 system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses
341 system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
342 system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses
343 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
344 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
345 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadCleanReq accesses
346 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992218 # miss rate for ReadCleanReq accesses
347 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses
348 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses
349 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses
350 system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
351 system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses
352 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
353 system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
354 system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
355 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
356 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
357 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency
358 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency
359 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
360 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
361 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
362 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
363 system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency
364 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
365 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
366 system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency
367 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
368 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
369 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
370 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
371 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
372 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
373 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
374 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
375 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
376 system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
377 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses
378 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses
379 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses
380 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses
381 system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses
382 system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
383 system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
384 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
385 system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
386 system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
387 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles
388 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles
389 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles
390 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles
391 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles
392 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles
393 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles
394 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles
395 system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles
396 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles
397 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles
398 system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles
399 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
400 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
401 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses
402 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses
403 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses
404 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses
405 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
406 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
407 system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses
408 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
409 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
410 system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
411 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
412 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
413 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency
414 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency
415 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
416 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
417 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency
418 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
419 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency
420 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency
421 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
422 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency
423 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
424 system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
425 system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
426 system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
427 system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution
428 system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution
429 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
430 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
431 system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
432 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
433 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
434 system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
435 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
436 system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram
437 system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
438 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
439 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
440 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
441 system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram
442 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
443 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
444 system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
445 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
446 system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
447 system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
448 system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
449 system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
450 system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
451 system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
452 system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
453 system.membus.trans_dist::ReadResp 308 # Transaction distribution
454 system.membus.trans_dist::ReadExReq 81 # Transaction distribution
455 system.membus.trans_dist::ReadExResp 81 # Transaction distribution
456 system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution
457 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
458 system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
459 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
460 system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
461 system.membus.snoops 0 # Total snoops (count)
462 system.membus.snoop_fanout::samples 389 # Request fanout histogram
463 system.membus.snoop_fanout::mean 0 # Request fanout histogram
464 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
465 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
466 system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
467 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
468 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
469 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
470 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
471 system.membus.snoop_fanout::total 389 # Request fanout histogram
472 system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
473 system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
474 system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks)
475 system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
477 ---------- End Simulation Statistics ----------
projects / gem5.git / blob