tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=DerivO3CPU
  48 children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  49 LFSTSize=1024
  50 LQEntries=32
  51 LSQCheckLoads=true
  52 LSQDepCheckShift=4
  53 SQEntries=32
  54 SSITSize=1024
  55 activity=0
  56 backComSize=5
  57 branchPred=system.cpu.branchPred
  58 cachePorts=200
  59 checker=Null
  60 clk_domain=system.cpu_clk_domain
  61 commitToDecodeDelay=1
  62 commitToFetchDelay=1
  63 commitToIEWDelay=1
  64 commitToRenameDelay=1
  65 commitWidth=8
  66 cpu_id=0
  67 decodeToFetchDelay=1
  68 decodeToRenameDelay=1
  69 decodeWidth=8
  70 dispatchWidth=8
  71 do_checkpoint_insts=true
  72 do_quiesce=true
  73 do_statistics_insts=true
  74 dtb=system.cpu.dtb
  75 eventq_index=0
  76 fetchBufferSize=64
  77 fetchToDecodeDelay=1
  78 fetchTrapLatency=1
  79 fetchWidth=8
  80 forwardComSize=5
  81 fuPool=system.cpu.fuPool
  82 function_trace=false
  83 function_trace_start=0
  84 iewToCommitDelay=1
  85 iewToDecodeDelay=1
  86 iewToFetchDelay=1
  87 iewToRenameDelay=1
  88 interrupts=system.cpu.interrupts
  89 isa=system.cpu.isa
  90 issueToExecuteDelay=1
  91 issueWidth=8
  92 itb=system.cpu.itb
  93 max_insts_all_threads=0
  94 max_insts_any_thread=0
  95 max_loads_all_threads=0
  96 max_loads_any_thread=0
  97 needsTSO=true
  98 numIQEntries=64
  99 numPhysCCRegs=1280
 100 numPhysFloatRegs=256
 101 numPhysIntRegs=256
 102 numROBEntries=192
 103 numRobs=1
 104 numThreads=1
 105 profile=0
 106 progress_interval=0
 107 renameToDecodeDelay=1
 108 renameToFetchDelay=1
 109 renameToIEWDelay=2
 110 renameToROBDelay=1
 111 renameWidth=8
 112 simpoint_start_insts=
 113 smtCommitPolicy=RoundRobin
 114 smtFetchPolicy=SingleThread
 115 smtIQPolicy=Partitioned
 116 smtIQThreshold=100
 117 smtLSQPolicy=Partitioned
 118 smtLSQThreshold=100
 119 smtNumFetchingThreads=1
 120 smtROBPolicy=Partitioned
 121 smtROBThreshold=100
 122 socket_id=0
 123 squashWidth=8
 124 store_set_clear_period=250000
 125 switched_out=false
 126 system=system
 127 tracer=system.cpu.tracer
 128 trapLatency=13
 129 wbDepth=1
 130 wbWidth=8
 131 workload=system.cpu.workload
 132 dcache_port=system.cpu.dcache.cpu_side
 133 icache_port=system.cpu.icache.cpu_side
 134
 135 [system.cpu.apic_clk_domain]
 136 type=DerivedClockDomain
 137 clk_divider=16
 138 clk_domain=system.cpu_clk_domain
 139 eventq_index=0
 140
 141 [system.cpu.branchPred]
 142 type=BranchPredictor
 143 BTBEntries=4096
 144 BTBTagSize=16
 145 RASSize=16
 146 choiceCtrBits=2
 147 choicePredictorSize=8192
 148 eventq_index=0
 149 globalCtrBits=2
 150 globalPredictorSize=8192
 151 instShiftAmt=2
 152 localCtrBits=2
 153 localHistoryTableSize=2048
 154 localPredictorSize=2048
 155 numThreads=1
 156 predType=tournament
 157
 158 [system.cpu.dcache]
 159 type=BaseCache
 160 children=tags
 161 addr_ranges=0:18446744073709551615
 162 assoc=2
 163 clk_domain=system.cpu_clk_domain
 164 eventq_index=0
 165 forward_snoops=true
 166 hit_latency=2
 167 is_top_level=true
 168 max_miss_count=0
 169 mshrs=4
 170 prefetch_on_access=false
 171 prefetcher=Null
 172 response_latency=2
 173 sequential_access=false
 174 size=262144
 175 system=system
 176 tags=system.cpu.dcache.tags
 177 tgts_per_mshr=20
 178 two_queue=false
 179 write_buffers=8
 180 cpu_side=system.cpu.dcache_port
 181 mem_side=system.cpu.toL2Bus.slave[1]
 182
 183 [system.cpu.dcache.tags]
 184 type=LRU
 185 assoc=2
 186 block_size=64
 187 clk_domain=system.cpu_clk_domain
 188 eventq_index=0
 189 hit_latency=2
 190 sequential_access=false
 191 size=262144
 192
 193 [system.cpu.dtb]
 194 type=X86TLB
 195 children=walker
 196 eventq_index=0
 197 size=64
 198 walker=system.cpu.dtb.walker
 199
 200 [system.cpu.dtb.walker]
 201 type=X86PagetableWalker
 202 clk_domain=system.cpu_clk_domain
 203 eventq_index=0
 204 num_squash_per_cycle=4
 205 system=system
 206 port=system.cpu.toL2Bus.slave[3]
 207
 208 [system.cpu.fuPool]
 209 type=FUPool
 210 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 211 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 212 eventq_index=0
 213
 214 [system.cpu.fuPool.FUList0]
 215 type=FUDesc
 216 children=opList
 217 count=6
 218 eventq_index=0
 219 opList=system.cpu.fuPool.FUList0.opList
 220
 221 [system.cpu.fuPool.FUList0.opList]
 222 type=OpDesc
 223 eventq_index=0
 224 issueLat=1
 225 opClass=IntAlu
 226 opLat=1
 227
 228 [system.cpu.fuPool.FUList1]
 229 type=FUDesc
 230 children=opList0 opList1
 231 count=2
 232 eventq_index=0
 233 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 234
 235 [system.cpu.fuPool.FUList1.opList0]
 236 type=OpDesc
 237 eventq_index=0
 238 issueLat=1
 239 opClass=IntMult
 240 opLat=3
 241
 242 [system.cpu.fuPool.FUList1.opList1]
 243 type=OpDesc
 244 eventq_index=0
 245 issueLat=19
 246 opClass=IntDiv
 247 opLat=20
 248
 249 [system.cpu.fuPool.FUList2]
 250 type=FUDesc
 251 children=opList0 opList1 opList2
 252 count=4
 253 eventq_index=0
 254 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 255
 256 [system.cpu.fuPool.FUList2.opList0]
 257 type=OpDesc
 258 eventq_index=0
 259 issueLat=1
 260 opClass=FloatAdd
 261 opLat=2
 262
 263 [system.cpu.fuPool.FUList2.opList1]
 264 type=OpDesc
 265 eventq_index=0
 266 issueLat=1
 267 opClass=FloatCmp
 268 opLat=2
 269
 270 [system.cpu.fuPool.FUList2.opList2]
 271 type=OpDesc
 272 eventq_index=0
 273 issueLat=1
 274 opClass=FloatCvt
 275 opLat=2
 276
 277 [system.cpu.fuPool.FUList3]
 278 type=FUDesc
 279 children=opList0 opList1 opList2
 280 count=2
 281 eventq_index=0
 282 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 283
 284 [system.cpu.fuPool.FUList3.opList0]
 285 type=OpDesc
 286 eventq_index=0
 287 issueLat=1
 288 opClass=FloatMult
 289 opLat=4
 290
 291 [system.cpu.fuPool.FUList3.opList1]
 292 type=OpDesc
 293 eventq_index=0
 294 issueLat=12
 295 opClass=FloatDiv
 296 opLat=12
 297
 298 [system.cpu.fuPool.FUList3.opList2]
 299 type=OpDesc
 300 eventq_index=0
 301 issueLat=24
 302 opClass=FloatSqrt
 303 opLat=24
 304
 305 [system.cpu.fuPool.FUList4]
 306 type=FUDesc
 307 children=opList
 308 count=0
 309 eventq_index=0
 310 opList=system.cpu.fuPool.FUList4.opList
 311
 312 [system.cpu.fuPool.FUList4.opList]
 313 type=OpDesc
 314 eventq_index=0
 315 issueLat=1
 316 opClass=MemRead
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5]
 320 type=FUDesc
 321 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 322 count=4
 323 eventq_index=0
 324 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 325
 326 [system.cpu.fuPool.FUList5.opList00]
 327 type=OpDesc
 328 eventq_index=0
 329 issueLat=1
 330 opClass=SimdAdd
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList01]
 334 type=OpDesc
 335 eventq_index=0
 336 issueLat=1
 337 opClass=SimdAddAcc
 338 opLat=1
 339
 340 [system.cpu.fuPool.FUList5.opList02]
 341 type=OpDesc
 342 eventq_index=0
 343 issueLat=1
 344 opClass=SimdAlu
 345 opLat=1
 346
 347 [system.cpu.fuPool.FUList5.opList03]
 348 type=OpDesc
 349 eventq_index=0
 350 issueLat=1
 351 opClass=SimdCmp
 352 opLat=1
 353
 354 [system.cpu.fuPool.FUList5.opList04]
 355 type=OpDesc
 356 eventq_index=0
 357 issueLat=1
 358 opClass=SimdCvt
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList05]
 362 type=OpDesc
 363 eventq_index=0
 364 issueLat=1
 365 opClass=SimdMisc
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList06]
 369 type=OpDesc
 370 eventq_index=0
 371 issueLat=1
 372 opClass=SimdMult
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList07]
 376 type=OpDesc
 377 eventq_index=0
 378 issueLat=1
 379 opClass=SimdMultAcc
 380 opLat=1
 381
 382 [system.cpu.fuPool.FUList5.opList08]
 383 type=OpDesc
 384 eventq_index=0
 385 issueLat=1
 386 opClass=SimdShift
 387 opLat=1
 388
 389 [system.cpu.fuPool.FUList5.opList09]
 390 type=OpDesc
 391 eventq_index=0
 392 issueLat=1
 393 opClass=SimdShiftAcc
 394 opLat=1
 395
 396 [system.cpu.fuPool.FUList5.opList10]
 397 type=OpDesc
 398 eventq_index=0
 399 issueLat=1
 400 opClass=SimdSqrt
 401 opLat=1
 402
 403 [system.cpu.fuPool.FUList5.opList11]
 404 type=OpDesc
 405 eventq_index=0
 406 issueLat=1
 407 opClass=SimdFloatAdd
 408 opLat=1
 409
 410 [system.cpu.fuPool.FUList5.opList12]
 411 type=OpDesc
 412 eventq_index=0
 413 issueLat=1
 414 opClass=SimdFloatAlu
 415 opLat=1
 416
 417 [system.cpu.fuPool.FUList5.opList13]
 418 type=OpDesc
 419 eventq_index=0
 420 issueLat=1
 421 opClass=SimdFloatCmp
 422 opLat=1
 423
 424 [system.cpu.fuPool.FUList5.opList14]
 425 type=OpDesc
 426 eventq_index=0
 427 issueLat=1
 428 opClass=SimdFloatCvt
 429 opLat=1
 430
 431 [system.cpu.fuPool.FUList5.opList15]
 432 type=OpDesc
 433 eventq_index=0
 434 issueLat=1
 435 opClass=SimdFloatDiv
 436 opLat=1
 437
 438 [system.cpu.fuPool.FUList5.opList16]
 439 type=OpDesc
 440 eventq_index=0
 441 issueLat=1
 442 opClass=SimdFloatMisc
 443 opLat=1
 444
 445 [system.cpu.fuPool.FUList5.opList17]
 446 type=OpDesc
 447 eventq_index=0
 448 issueLat=1
 449 opClass=SimdFloatMult
 450 opLat=1
 451
 452 [system.cpu.fuPool.FUList5.opList18]
 453 type=OpDesc
 454 eventq_index=0
 455 issueLat=1
 456 opClass=SimdFloatMultAcc
 457 opLat=1
 458
 459 [system.cpu.fuPool.FUList5.opList19]
 460 type=OpDesc
 461 eventq_index=0
 462 issueLat=1
 463 opClass=SimdFloatSqrt
 464 opLat=1
 465
 466 [system.cpu.fuPool.FUList6]
 467 type=FUDesc
 468 children=opList
 469 count=0
 470 eventq_index=0
 471 opList=system.cpu.fuPool.FUList6.opList
 472
 473 [system.cpu.fuPool.FUList6.opList]
 474 type=OpDesc
 475 eventq_index=0
 476 issueLat=1
 477 opClass=MemWrite
 478 opLat=1
 479
 480 [system.cpu.fuPool.FUList7]
 481 type=FUDesc
 482 children=opList0 opList1
 483 count=4
 484 eventq_index=0
 485 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 486
 487 [system.cpu.fuPool.FUList7.opList0]
 488 type=OpDesc
 489 eventq_index=0
 490 issueLat=1
 491 opClass=MemRead
 492 opLat=1
 493
 494 [system.cpu.fuPool.FUList7.opList1]
 495 type=OpDesc
 496 eventq_index=0
 497 issueLat=1
 498 opClass=MemWrite
 499 opLat=1
 500
 501 [system.cpu.fuPool.FUList8]
 502 type=FUDesc
 503 children=opList
 504 count=1
 505 eventq_index=0
 506 opList=system.cpu.fuPool.FUList8.opList
 507
 508 [system.cpu.fuPool.FUList8.opList]
 509 type=OpDesc
 510 eventq_index=0
 511 issueLat=3
 512 opClass=IprAccess
 513 opLat=3
 514
 515 [system.cpu.icache]
 516 type=BaseCache
 517 children=tags
 518 addr_ranges=0:18446744073709551615
 519 assoc=2
 520 clk_domain=system.cpu_clk_domain
 521 eventq_index=0
 522 forward_snoops=true
 523 hit_latency=2
 524 is_top_level=true
 525 max_miss_count=0
 526 mshrs=4
 527 prefetch_on_access=false
 528 prefetcher=Null
 529 response_latency=2
 530 sequential_access=false
 531 size=131072
 532 system=system
 533 tags=system.cpu.icache.tags
 534 tgts_per_mshr=20
 535 two_queue=false
 536 write_buffers=8
 537 cpu_side=system.cpu.icache_port
 538 mem_side=system.cpu.toL2Bus.slave[0]
 539
 540 [system.cpu.icache.tags]
 541 type=LRU
 542 assoc=2
 543 block_size=64
 544 clk_domain=system.cpu_clk_domain
 545 eventq_index=0
 546 hit_latency=2
 547 sequential_access=false
 548 size=131072
 549
 550 [system.cpu.interrupts]
 551 type=X86LocalApic
 552 clk_domain=system.cpu.apic_clk_domain
 553 eventq_index=0
 554 int_latency=1000
 555 pio_addr=2305843009213693952
 556 pio_latency=100000
 557 system=system
 558 int_master=system.membus.slave[2]
 559 int_slave=system.membus.master[2]
 560 pio=system.membus.master[1]
 561
 562 [system.cpu.isa]
 563 type=X86ISA
 564 eventq_index=0
 565
 566 [system.cpu.itb]
 567 type=X86TLB
 568 children=walker
 569 eventq_index=0
 570 size=64
 571 walker=system.cpu.itb.walker
 572
 573 [system.cpu.itb.walker]
 574 type=X86PagetableWalker
 575 clk_domain=system.cpu_clk_domain
 576 eventq_index=0
 577 num_squash_per_cycle=4
 578 system=system
 579 port=system.cpu.toL2Bus.slave[2]
 580
 581 [system.cpu.l2cache]
 582 type=BaseCache
 583 children=tags
 584 addr_ranges=0:18446744073709551615
 585 assoc=8
 586 clk_domain=system.cpu_clk_domain
 587 eventq_index=0
 588 forward_snoops=true
 589 hit_latency=20
 590 is_top_level=false
 591 max_miss_count=0
 592 mshrs=20
 593 prefetch_on_access=false
 594 prefetcher=Null
 595 response_latency=20
 596 sequential_access=false
 597 size=2097152
 598 system=system
 599 tags=system.cpu.l2cache.tags
 600 tgts_per_mshr=12
 601 two_queue=false
 602 write_buffers=8
 603 cpu_side=system.cpu.toL2Bus.master[0]
 604 mem_side=system.membus.slave[1]
 605
 606 [system.cpu.l2cache.tags]
 607 type=LRU
 608 assoc=8
 609 block_size=64
 610 clk_domain=system.cpu_clk_domain
 611 eventq_index=0
 612 hit_latency=20
 613 sequential_access=false
 614 size=2097152
 615
 616 [system.cpu.toL2Bus]
 617 type=CoherentBus
 618 clk_domain=system.cpu_clk_domain
 619 eventq_index=0
 620 header_cycles=1
 621 system=system
 622 use_default_range=false
 623 width=32
 624 master=system.cpu.l2cache.cpu_side
 625 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 626
 627 [system.cpu.tracer]
 628 type=ExeTracer
 629 eventq_index=0
 630
 631 [system.cpu.workload]
 632 type=LiveProcess
 633 cmd=hello
 634 cwd=
 635 egid=100
 636 env=
 637 errout=cerr
 638 euid=100
 639 eventq_index=0
 640 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
 641 gid=100
 642 input=cin
 643 max_stack_size=67108864
 644 output=cout
 645 pid=100
 646 ppid=99
 647 simpoint=0
 648 system=system
 649 uid=100
 650
 651 [system.cpu_clk_domain]
 652 type=SrcClockDomain
 653 clock=500
 654 domain_id=-1
 655 eventq_index=0
 656 init_perf_level=0
 657 voltage_domain=system.voltage_domain
 658
 659 [system.dvfs_handler]
 660 type=DVFSHandler
 661 domains=
 662 enable=false
 663 eventq_index=0
 664 sys_clk_domain=system.clk_domain
 665 transition_latency=100000000
 666
 667 [system.membus]
 668 type=CoherentBus
 669 clk_domain=system.clk_domain
 670 eventq_index=0
 671 header_cycles=1
 672 system=system
 673 use_default_range=false
 674 width=8
 675 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 676 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 677
 678 [system.physmem]
 679 type=DRAMCtrl
 680 activation_limit=4
 681 addr_mapping=RoRaBaChCo
 682 banks_per_rank=8
 683 burst_length=8
 684 channels=1
 685 clk_domain=system.clk_domain
 686 conf_table_reported=true
 687 device_bus_width=8
 688 device_rowbuffer_size=1024
 689 devices_per_rank=8
 690 eventq_index=0
 691 in_addr_map=true
 692 max_accesses_per_row=16
 693 mem_sched_policy=frfcfs
 694 min_writes_per_switch=16
 695 null=false
 696 page_policy=open_adaptive
 697 range=0:134217727
 698 ranks_per_channel=2
 699 read_buffer_size=32
 700 static_backend_latency=10000
 701 static_frontend_latency=10000
 702 tBURST=5000
 703 tCK=1250
 704 tCL=13750
 705 tRAS=35000
 706 tRCD=13750
 707 tREFI=7800000
 708 tRFC=260000
 709 tRP=13750
 710 tRRD=6000
 711 tRTP=7500
 712 tRTW=2500
 713 tWR=15000
 714 tWTR=7500
 715 tXAW=30000
 716 write_buffer_size=64
 717 write_high_thresh_perc=85
 718 write_low_thresh_perc=50
 719 port=system.membus.master[0]
 720
 721 [system.voltage_domain]
 722 type=VoltageDomain
 723 eventq_index=0
 724 voltage=1.000000
 725