2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000015 # Number of seconds simulated
4 sim_ticks 15014000 # Number of ticks simulated
5 final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 32657 # Simulator instruction rate (inst/s)
8 host_op_rate 59148 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 91121721 # Simulator tick rate (ticks/s)
10 host_mem_usage 223384 # Number of bytes of host memory used
11 host_seconds 0.16 # Real time elapsed on the host
12 sim_insts 5380 # Number of instructions simulated
13 sim_ops 9745 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 450 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 28736 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 14992500 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 450 # Categorize read packet sizes
81 system.physmem.readPktSize::7 0 # Categorize read packet sizes
82 system.physmem.readPktSize::8 0 # Categorize read packet sizes
83 system.physmem.writePktSize::0 0 # categorize write packet sizes
84 system.physmem.writePktSize::1 0 # categorize write packet sizes
85 system.physmem.writePktSize::2 0 # categorize write packet sizes
86 system.physmem.writePktSize::3 0 # categorize write packet sizes
87 system.physmem.writePktSize::4 0 # categorize write packet sizes
88 system.physmem.writePktSize::5 0 # categorize write packet sizes
89 system.physmem.writePktSize::6 0 # categorize write packet sizes
90 system.physmem.writePktSize::7 0 # categorize write packet sizes
91 system.physmem.writePktSize::8 0 # categorize write packet sizes
92 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
93 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98 system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101 system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
134 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167 system.physmem.totQLat 1656450 # Total cycles spent in queuing delays
168 system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests
169 system.physmem.totBusLat 1800000 # Total cycles spent in databus access
170 system.physmem.totBankLat 8568000 # Total cycles spent in bank access
171 system.physmem.avgQLat 3681.00 # Average queueing delay per request
172 system.physmem.avgBankLat 19040.00 # Average bank access latency per request
173 system.physmem.avgBusLat 4000.00 # Average bus latency per request
174 system.physmem.avgMemAccLat 26721.00 # Average memory access latency
175 system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s
176 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177 system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s
178 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179 system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180 system.physmem.busUtil 11.96 # Data bus utilization in percentage
181 system.physmem.avgRdQLen 0.80 # Average read queue length over time
182 system.physmem.avgWrQLen 0.00 # Average write queue length over time
183 system.physmem.readRowHits 352 # Number of row buffer hits during reads
184 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185 system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads
186 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187 system.physmem.avgGap 33316.67 # Average gap between requests
188 system.cpu.workload.num_syscalls 11 # Number of system calls
189 system.cpu.numCycles 30029 # number of cpu cycles simulated
190 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
191 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
192 system.cpu.BPredUnit.lookups 3018 # Number of BP lookups
193 system.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted
194 system.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect
195 system.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups
196 system.cpu.BPredUnit.BTBHits 796 # Number of BTB hits
197 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
198 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
199 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
200 system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss
201 system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed
202 system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered
203 system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken
204 system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked
205 system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing
206 system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked
207 system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
208 system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps
209 system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
210 system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched
211 system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
212 system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total)
213 system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total)
214 system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total)
215 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
216 system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total)
217 system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total)
218 system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total)
219 system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total)
220 system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total)
221 system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total)
222 system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total)
223 system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total)
224 system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total)
225 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
226 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
227 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
228 system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total)
229 system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle
230 system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle
231 system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle
232 system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked
233 system.cpu.decode.RunCycles 3547 # Number of cycles decode is running
234 system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
235 system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing
236 system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode
237 system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing
238 system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle
239 system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking
240 system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst
241 system.cpu.rename.RunCycles 3325 # Number of cycles rename is running
242 system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking
243 system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename
244 system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
245 system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
246 system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full
247 system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed
248 system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made
249 system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups
250 system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
251 system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
252 system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing
253 system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
254 system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
255 system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer
256 system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit.
257 system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit.
258 system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
259 system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
260 system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec)
261 system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
262 system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued
263 system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued
264 system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling
265 system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph
266 system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
267 system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle
268 system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle
269 system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle
270 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
271 system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle
272 system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle
273 system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle
274 system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle
275 system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle
276 system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle
277 system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle
278 system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle
279 system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle
280 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
281 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
282 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
283 system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle
284 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
285 system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available
286 system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available
287 system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available
288 system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available
289 system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available
290 system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available
291 system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available
292 system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available
293 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available
294 system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available
295 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available
296 system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available
297 system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available
298 system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available
299 system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available
300 system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available
301 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available
302 system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available
303 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available
304 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available
305 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available
306 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available
307 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available
308 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available
309 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available
310 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available
311 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available
312 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available
313 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available
314 system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available
315 system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available
316 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
317 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
318 system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
319 system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued
320 system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued
321 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued
322 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued
323 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued
324 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued
325 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued
326 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued
327 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued
328 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued
329 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued
330 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued
331 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued
332 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued
333 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued
334 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued
335 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued
336 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued
337 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued
338 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued
339 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued
340 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued
341 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued
342 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued
343 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued
344 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued
345 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued
346 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued
347 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued
348 system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued
349 system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued
350 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
351 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
352 system.cpu.iq.FU_type_0::total 17349 # Type of FU issued
353 system.cpu.iq.rate 0.577742 # Inst issue rate
354 system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
355 system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst)
356 system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads
357 system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes
358 system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses
359 system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
360 system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
361 system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
362 system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses
363 system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
364 system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores
365 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
366 system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed
367 system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
368 system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
369 system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed
370 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
371 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
372 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
373 system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
374 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
375 system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing
376 system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking
377 system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
378 system.cpu.iew.iewDispatchedInsts 20491 # Number of instructions dispatched to IQ
379 system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
380 system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions
381 system.cpu.iew.iewDispStoreInsts 1755 # Number of dispatched store instructions
382 system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
383 system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
384 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
385 system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
386 system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
387 system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly
388 system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute
389 system.cpu.iew.iewExecutedInsts 16425 # Number of executed instructions
390 system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed
391 system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute
392 system.cpu.iew.exec_swp 0 # number of swp insts executed
393 system.cpu.iew.exec_nop 0 # number of nop insts executed
394 system.cpu.iew.exec_refs 3140 # number of memory reference insts executed
395 system.cpu.iew.exec_branches 1630 # Number of branches executed
396 system.cpu.iew.exec_stores 1363 # Number of stores executed
397 system.cpu.iew.exec_rate 0.546971 # Inst execution rate
398 system.cpu.iew.wb_sent 16197 # cumulative count of insts sent to commit
399 system.cpu.iew.wb_count 16007 # cumulative count of insts written-back
400 system.cpu.iew.wb_producers 10178 # num instructions producing a value
401 system.cpu.iew.wb_consumers 15727 # num instructions consuming a value
402 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
403 system.cpu.iew.wb_rate 0.533051 # insts written-back per cycle
404 system.cpu.iew.wb_fanout 0.647167 # average fanout of values written-back
405 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
406 system.cpu.commit.commitSquashedInsts 10745 # The number of squashed insts skipped by commit
407 system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
408 system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted
409 system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle
410 system.cpu.commit.committed_per_cycle::mean 0.581687 # Number of insts commited each cycle
411 system.cpu.commit.committed_per_cycle::stdev 1.458321 # Number of insts commited each cycle
412 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
413 system.cpu.commit.committed_per_cycle::0 13226 78.95% 78.95% # Number of insts commited each cycle
414 system.cpu.commit.committed_per_cycle::1 1316 7.86% 86.80% # Number of insts commited each cycle
415 system.cpu.commit.committed_per_cycle::2 596 3.56% 90.36% # Number of insts commited each cycle
416 system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle
417 system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle
418 system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle
419 system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle
420 system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle
421 system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle
422 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
423 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
424 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
425 system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle
426 system.cpu.commit.committedInsts 5380 # Number of instructions committed
427 system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
428 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
429 system.cpu.commit.refs 1986 # Number of memory references committed
430 system.cpu.commit.loads 1052 # Number of loads committed
431 system.cpu.commit.membars 0 # Number of memory barriers committed
432 system.cpu.commit.branches 1208 # Number of branches committed
433 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
434 system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
435 system.cpu.commit.function_calls 0 # Number of function calls committed.
436 system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
437 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
438 system.cpu.rob.rob_reads 37022 # The number of ROB reads
439 system.cpu.rob.rob_writes 42839 # The number of ROB writes
440 system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
441 system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling
442 system.cpu.committedInsts 5380 # Number of Instructions Simulated
443 system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
444 system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
445 system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction
446 system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads
447 system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle
448 system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads
449 system.cpu.int_regfile_reads 28874 # number of integer regfile reads
450 system.cpu.int_regfile_writes 17232 # number of integer regfile writes
451 system.cpu.fp_regfile_reads 4 # number of floating regfile reads
452 system.cpu.misc_regfile_reads 7155 # number of misc regfile reads
453 system.cpu.icache.replacements 0 # number of replacements
454 system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use
455 system.cpu.icache.total_refs 1482 # Total number of references to valid blocks.
456 system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
457 system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks.
458 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
459 system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor
460 system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy
461 system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy
462 system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits
463 system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits
464 system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits
465 system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits
466 system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits
467 system.cpu.icache.overall_hits::total 1482 # number of overall hits
468 system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses
469 system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses
470 system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses
471 system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses
472 system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses
473 system.cpu.icache.overall_misses::total 398 # number of overall misses
474 system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles
475 system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles
476 system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles
477 system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles
478 system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles
479 system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles
480 system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses)
481 system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses)
482 system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses
483 system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses
484 system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses
485 system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses
486 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses
487 system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses
488 system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses
489 system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses
490 system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses
491 system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses
492 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency
493 system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency
494 system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
495 system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency
496 system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
497 system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency
498 system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
499 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
500 system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
501 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
502 system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
503 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
504 system.cpu.icache.fast_writes 0 # number of fast writes performed
505 system.cpu.icache.cache_copies 0 # number of cache copies performed
506 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
507 system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
508 system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
509 system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
510 system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
511 system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
512 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
513 system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
514 system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
515 system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
516 system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
517 system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
518 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles
519 system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles
520 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles
521 system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles
522 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles
523 system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles
524 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for ReadReq accesses
525 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses
526 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses
527 system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses
528 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses
529 system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses
530 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency
531 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency
532 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
533 system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
534 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
535 system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
536 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
537 system.cpu.l2cache.replacements 0 # number of replacements
538 system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use
539 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
540 system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
541 system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
542 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
543 system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor
544 system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor
545 system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy
546 system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
547 system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy
548 system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
549 system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
550 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
551 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
552 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
553 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
554 system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
555 system.cpu.l2cache.ReadReq_misses::cpu.data 71 # number of ReadReq misses
556 system.cpu.l2cache.ReadReq_misses::total 374 # number of ReadReq misses
557 system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
558 system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
559 system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
560 system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
561 system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses
562 system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses
563 system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
564 system.cpu.l2cache.overall_misses::total 450 # number of overall misses
565 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles
566 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811000 # number of ReadReq miss cycles
567 system.cpu.l2cache.ReadReq_miss_latency::total 18957500 # number of ReadReq miss cycles
568 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles
569 system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles
570 system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles
571 system.cpu.l2cache.demand_miss_latency::cpu.data 7803500 # number of demand (read+write) miss cycles
572 system.cpu.l2cache.demand_miss_latency::total 22950000 # number of demand (read+write) miss cycles
573 system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles
574 system.cpu.l2cache.overall_miss_latency::cpu.data 7803500 # number of overall miss cycles
575 system.cpu.l2cache.overall_miss_latency::total 22950000 # number of overall miss cycles
576 system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
577 system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses)
578 system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses)
579 system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
580 system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
581 system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
582 system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
583 system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses
584 system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
585 system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
586 system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses
587 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses
588 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
589 system.cpu.l2cache.ReadReq_miss_rate::total 0.997333 # miss rate for ReadReq accesses
590 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
591 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
592 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses
593 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
594 system.cpu.l2cache.demand_miss_rate::total 0.997783 # miss rate for demand accesses
595 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses
596 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
597 system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses
598 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency
599 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53676.056338 # average ReadReq miss latency
600 system.cpu.l2cache.ReadReq_avg_miss_latency::total 50688.502674 # average ReadReq miss latency
601 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency
602 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency
603 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
604 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
605 system.cpu.l2cache.demand_avg_miss_latency::total 51000 # average overall miss latency
606 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
607 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
608 system.cpu.l2cache.overall_avg_miss_latency::total 51000 # average overall miss latency
609 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
610 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
611 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
612 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
613 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
614 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
615 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
616 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
617 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
618 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
619 system.cpu.l2cache.ReadReq_mshr_misses::total 374 # number of ReadReq MSHR misses
620 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
621 system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
622 system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
623 system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
624 system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses
625 system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
626 system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
627 system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses
628 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336452 # number of ReadReq MSHR miss cycles
629 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles
630 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14280524 # number of ReadReq MSHR miss cycles
631 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles
632 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles
633 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336452 # number of demand (read+write) MSHR miss cycles
634 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles
635 system.cpu.l2cache.demand_mshr_miss_latency::total 17309634 # number of demand (read+write) MSHR miss cycles
636 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336452 # number of overall MSHR miss cycles
637 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles
638 system.cpu.l2cache.overall_mshr_miss_latency::total 17309634 # number of overall MSHR miss cycles
639 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
640 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
641 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses
642 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
643 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
644 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses
645 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
646 system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses
647 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
648 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
649 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses
650 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency
651 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency
652 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency
653 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency
654 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency
655 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
656 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
657 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
658 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
659 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
660 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
661 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
662 system.cpu.dcache.replacements 0 # number of replacements
663 system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
664 system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
665 system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
666 system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
667 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
668 system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
669 system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
670 system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
671 system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits
672 system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits
673 system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
674 system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
675 system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
676 system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
677 system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
678 system.cpu.dcache.overall_hits::total 2284 # number of overall hits
679 system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
680 system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
681 system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
682 system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
683 system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
684 system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
685 system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
686 system.cpu.dcache.overall_misses::total 202 # number of overall misses
687 system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles
688 system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles
689 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
690 system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
691 system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles
692 system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles
693 system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles
694 system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
695 system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses)
696 system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses)
697 system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
698 system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
699 system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
700 system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
701 system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
702 system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
703 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081186 # miss rate for ReadReq accesses
704 system.cpu.dcache.ReadReq_miss_rate::total 0.081186 # miss rate for ReadReq accesses
705 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
706 system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
707 system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
708 system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
709 system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
710 system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
711 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
712 system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
713 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
714 system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
715 system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
716 system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
717 system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
718 system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
719 system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
720 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
721 system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
722 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
723 system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
724 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
725 system.cpu.dcache.fast_writes 0 # number of fast writes performed
726 system.cpu.dcache.cache_copies 0 # number of cache copies performed
727 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
728 system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
729 system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
730 system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
731 system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
732 system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
733 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
734 system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
735 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
736 system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
737 system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
738 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
739 system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
740 system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
741 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles
742 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles
743 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
744 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
745 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles
746 system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles
747 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles
748 system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles
749 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045747 # mshr miss rate for ReadReq accesses
750 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045747 # mshr miss rate for ReadReq accesses
751 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
752 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
753 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
754 system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
755 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
756 system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
757 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
758 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
759 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
760 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
761 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
762 system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
763 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
764 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
765 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
767 ---------- End Simulation Statistics ----------
projects / gem5.git / blob