2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000015 # Number of seconds simulated
4 sim_ticks 15471000 # Number of ticks simulated
5 final_tick 15471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 25126 # Simulator instruction rate (inst/s)
8 host_op_rate 45518 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 72243012 # Simulator tick rate (ticks/s)
10 host_mem_usage 287412 # Number of bytes of host memory used
11 host_seconds 0.21 # Real time elapsed on the host
12 sim_insts 5380 # Number of instructions simulated
13 sim_ops 9747 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1253441924 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 603968716 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 1857410639 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1253441924 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1253441924 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1253441924 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 603968716 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 1857410639 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 451 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 28736 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 49 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 36 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 34 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 8 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 11 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 5 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 15455000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 451 # Categorize read packet sizes
81 system.physmem.writePktSize::0 0 # Categorize write packet sizes
82 system.physmem.writePktSize::1 0 # Categorize write packet sizes
83 system.physmem.writePktSize::2 0 # Categorize write packet sizes
84 system.physmem.writePktSize::3 0 # Categorize write packet sizes
85 system.physmem.writePktSize::4 0 # Categorize write packet sizes
86 system.physmem.writePktSize::5 0 # Categorize write packet sizes
87 system.physmem.writePktSize::6 0 # Categorize write packet sizes
88 system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see
89 system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152 system.physmem.totQLat 1899500 # Total cycles spent in queuing delays
153 system.physmem.totMemAccLat 13160750 # Sum of mem lat for all requests
154 system.physmem.totBusLat 2255000 # Total cycles spent in databus access
155 system.physmem.totBankLat 9006250 # Total cycles spent in bank access
156 system.physmem.avgQLat 4211.75 # Average queueing delay per request
157 system.physmem.avgBankLat 19969.51 # Average bank access latency per request
158 system.physmem.avgBusLat 5000.00 # Average bus latency per request
159 system.physmem.avgMemAccLat 29181.26 # Average memory access latency
160 system.physmem.avgRdBW 1857.41 # Average achieved read bandwidth in MB/s
161 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
162 system.physmem.avgConsumedRdBW 1857.41 # Average consumed read bandwidth in MB/s
163 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
164 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
165 system.physmem.busUtil 14.51 # Data bus utilization in percentage
166 system.physmem.avgRdQLen 0.85 # Average read queue length over time
167 system.physmem.avgWrQLen 0.00 # Average write queue length over time
168 system.physmem.readRowHits 333 # Number of row buffer hits during reads
169 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
170 system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads
171 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
172 system.physmem.avgGap 34268.29 # Average gap between requests
173 system.cpu.branchPred.lookups 2992 # Number of BP lookups
174 system.cpu.branchPred.condPredicted 2992 # Number of conditional branches predicted
175 system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
176 system.cpu.branchPred.BTBLookups 2482 # Number of BTB lookups
177 system.cpu.branchPred.BTBHits 793 # Number of BTB hits
178 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
179 system.cpu.branchPred.BTBHitPct 31.950040 # BTB Hit Percentage
180 system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
181 system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
182 system.cpu.workload.num_syscalls 11 # Number of system calls
183 system.cpu.numCycles 30943 # number of cpu cycles simulated
184 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
185 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
186 system.cpu.fetch.icacheStallCycles 8896 # Number of cycles fetch is stalled on an Icache miss
187 system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed
188 system.cpu.fetch.Branches 2992 # Number of branches that fetch encountered
189 system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken
190 system.cpu.fetch.Cycles 3908 # Number of cycles fetch has run and was not squashing or blocked
191 system.cpu.fetch.SquashCycles 2410 # Number of cycles fetch has spent squashing
192 system.cpu.fetch.BlockedCycles 3707 # Number of cycles fetch has spent blocked
193 system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
194 system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps
195 system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
196 system.cpu.fetch.CacheLines 1872 # Number of cache lines fetched
197 system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
198 system.cpu.fetch.rateDist::samples 18558 # Number of instructions fetched each cycle (Total)
199 system.cpu.fetch.rateDist::mean 1.369490 # Number of instructions fetched each cycle (Total)
200 system.cpu.fetch.rateDist::stdev 2.871739 # Number of instructions fetched each cycle (Total)
201 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
202 system.cpu.fetch.rateDist::0 14749 79.48% 79.48% # Number of instructions fetched each cycle (Total)
203 system.cpu.fetch.rateDist::1 190 1.02% 80.50% # Number of instructions fetched each cycle (Total)
204 system.cpu.fetch.rateDist::2 153 0.82% 81.32% # Number of instructions fetched each cycle (Total)
205 system.cpu.fetch.rateDist::3 193 1.04% 82.36% # Number of instructions fetched each cycle (Total)
206 system.cpu.fetch.rateDist::4 163 0.88% 83.24% # Number of instructions fetched each cycle (Total)
207 system.cpu.fetch.rateDist::5 168 0.91% 84.15% # Number of instructions fetched each cycle (Total)
208 system.cpu.fetch.rateDist::6 264 1.42% 85.57% # Number of instructions fetched each cycle (Total)
209 system.cpu.fetch.rateDist::7 160 0.86% 86.43% # Number of instructions fetched each cycle (Total)
210 system.cpu.fetch.rateDist::8 2518 13.57% 100.00% # Number of instructions fetched each cycle (Total)
211 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
212 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
213 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
214 system.cpu.fetch.rateDist::total 18558 # Number of instructions fetched each cycle (Total)
215 system.cpu.fetch.branchRate 0.096694 # Number of branch fetches per cycle
216 system.cpu.fetch.rate 0.464952 # Number of inst fetches per cycle
217 system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle
218 system.cpu.decode.BlockedCycles 3646 # Number of cycles decode is blocked
219 system.cpu.decode.RunCycles 3518 # Number of cycles decode is running
220 system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking
221 system.cpu.decode.SquashCycles 1817 # Number of cycles decode is squashing
222 system.cpu.decode.DecodedInsts 24275 # Number of instructions handled by decode
223 system.cpu.rename.SquashCycles 1817 # Number of cycles rename is squashing
224 system.cpu.rename.IdleCycles 9777 # Number of cycles rename is idle
225 system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking
226 system.cpu.rename.serializeStallCycles 497 # count of cycles rename stalled for serializing inst
227 system.cpu.rename.RunCycles 3304 # Number of cycles rename is running
228 system.cpu.rename.UnblockCycles 765 # Number of cycles rename is unblocking
229 system.cpu.rename.RenamedInsts 22769 # Number of instructions processed by rename
230 system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
231 system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
232 system.cpu.rename.LSQFullEvents 649 # Number of times rename has blocked due to LSQ full
233 system.cpu.rename.RenamedOperands 24875 # Number of destination operands rename has renamed
234 system.cpu.rename.RenameLookups 54688 # Number of register rename lookups that rename has made
235 system.cpu.rename.int_rename_lookups 54672 # Number of integer rename lookups
236 system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
237 system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
238 system.cpu.rename.UndoneMaps 13812 # Number of HB maps that are undone due to squashing
239 system.cpu.rename.serializingInsts 34 # count of serializing insts renamed
240 system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed
241 system.cpu.rename.skidInsts 2061 # count of insts added to the skid buffer
242 system.cpu.memDep0.insertedLoads 2202 # Number of loads inserted to the mem dependence unit.
243 system.cpu.memDep0.insertedStores 1748 # Number of stores inserted to the mem dependence unit.
244 system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
245 system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
246 system.cpu.iq.iqInstsAdded 20301 # Number of instructions added to the IQ (excludes non-spec)
247 system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ
248 system.cpu.iq.iqInstsIssued 17266 # Number of instructions issued
249 system.cpu.iq.iqSquashedInstsIssued 205 # Number of squashed instructions issued
250 system.cpu.iq.iqSquashedInstsExamined 9813 # Number of squashed instructions iterated over during squash; mainly for profiling
251 system.cpu.iq.iqSquashedOperandsExamined 13640 # Number of squashed operands that are examined and possibly removed from graph
252 system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
253 system.cpu.iq.issued_per_cycle::samples 18558 # Number of insts issued each cycle
254 system.cpu.iq.issued_per_cycle::mean 0.930380 # Number of insts issued each cycle
255 system.cpu.iq.issued_per_cycle::stdev 1.788216 # Number of insts issued each cycle
256 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
257 system.cpu.iq.issued_per_cycle::0 13171 70.97% 70.97% # Number of insts issued each cycle
258 system.cpu.iq.issued_per_cycle::1 1403 7.56% 78.53% # Number of insts issued each cycle
259 system.cpu.iq.issued_per_cycle::2 1055 5.68% 84.22% # Number of insts issued each cycle
260 system.cpu.iq.issued_per_cycle::3 693 3.73% 87.95% # Number of insts issued each cycle
261 system.cpu.iq.issued_per_cycle::4 728 3.92% 91.87% # Number of insts issued each cycle
262 system.cpu.iq.issued_per_cycle::5 621 3.35% 95.22% # Number of insts issued each cycle
263 system.cpu.iq.issued_per_cycle::6 594 3.20% 98.42% # Number of insts issued each cycle
264 system.cpu.iq.issued_per_cycle::7 251 1.35% 99.77% # Number of insts issued each cycle
265 system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle
266 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
267 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
268 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
269 system.cpu.iq.issued_per_cycle::total 18558 # Number of insts issued each cycle
270 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
271 system.cpu.iq.fu_full::IntAlu 132 76.30% 76.30% # attempts to use FU when none available
272 system.cpu.iq.fu_full::IntMult 0 0.00% 76.30% # attempts to use FU when none available
273 system.cpu.iq.fu_full::IntDiv 0 0.00% 76.30% # attempts to use FU when none available
274 system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.30% # attempts to use FU when none available
275 system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.30% # attempts to use FU when none available
276 system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.30% # attempts to use FU when none available
277 system.cpu.iq.fu_full::FloatMult 0 0.00% 76.30% # attempts to use FU when none available
278 system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.30% # attempts to use FU when none available
279 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.30% # attempts to use FU when none available
280 system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.30% # attempts to use FU when none available
281 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.30% # attempts to use FU when none available
282 system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.30% # attempts to use FU when none available
283 system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.30% # attempts to use FU when none available
284 system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.30% # attempts to use FU when none available
285 system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.30% # attempts to use FU when none available
286 system.cpu.iq.fu_full::SimdMult 0 0.00% 76.30% # attempts to use FU when none available
287 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.30% # attempts to use FU when none available
288 system.cpu.iq.fu_full::SimdShift 0 0.00% 76.30% # attempts to use FU when none available
289 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.30% # attempts to use FU when none available
290 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.30% # attempts to use FU when none available
291 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.30% # attempts to use FU when none available
292 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.30% # attempts to use FU when none available
293 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.30% # attempts to use FU when none available
294 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.30% # attempts to use FU when none available
295 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.30% # attempts to use FU when none available
296 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.30% # attempts to use FU when none available
297 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.30% # attempts to use FU when none available
298 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.30% # attempts to use FU when none available
299 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.30% # attempts to use FU when none available
300 system.cpu.iq.fu_full::MemRead 20 11.56% 87.86% # attempts to use FU when none available
301 system.cpu.iq.fu_full::MemWrite 21 12.14% 100.00% # attempts to use FU when none available
302 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
303 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
304 system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
305 system.cpu.iq.FU_type_0::IntAlu 13880 80.39% 80.41% # Type of FU issued
306 system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.41% # Type of FU issued
307 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.41% # Type of FU issued
308 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.41% # Type of FU issued
309 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.41% # Type of FU issued
310 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.41% # Type of FU issued
311 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.41% # Type of FU issued
312 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.41% # Type of FU issued
313 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.41% # Type of FU issued
314 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.41% # Type of FU issued
315 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.41% # Type of FU issued
316 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.41% # Type of FU issued
317 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.41% # Type of FU issued
318 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.41% # Type of FU issued
319 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.41% # Type of FU issued
320 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.41% # Type of FU issued
321 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.41% # Type of FU issued
322 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.41% # Type of FU issued
323 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.41% # Type of FU issued
324 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.41% # Type of FU issued
325 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.41% # Type of FU issued
326 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.41% # Type of FU issued
327 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.41% # Type of FU issued
328 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.41% # Type of FU issued
329 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.41% # Type of FU issued
330 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.41% # Type of FU issued
331 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.41% # Type of FU issued
332 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.41% # Type of FU issued
333 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.41% # Type of FU issued
334 system.cpu.iq.FU_type_0::MemRead 1903 11.02% 91.43% # Type of FU issued
335 system.cpu.iq.FU_type_0::MemWrite 1480 8.57% 100.00% # Type of FU issued
336 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
337 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
338 system.cpu.iq.FU_type_0::total 17266 # Type of FU issued
339 system.cpu.iq.rate 0.557994 # Inst issue rate
340 system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
341 system.cpu.iq.fu_busy_rate 0.010020 # FU busy rate (busy events/executed inst)
342 system.cpu.iq.int_inst_queue_reads 53460 # Number of integer instruction queue reads
343 system.cpu.iq.int_inst_queue_writes 30157 # Number of integer instruction queue writes
344 system.cpu.iq.int_inst_queue_wakeup_accesses 15915 # Number of integer instruction queue wakeup accesses
345 system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
346 system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
347 system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
348 system.cpu.iq.int_alu_accesses 17432 # Number of integer alu accesses
349 system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
350 system.cpu.iew.lsq.thread0.forwLoads 159 # Number of loads that had data forwarded from stores
351 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
352 system.cpu.iew.lsq.thread0.squashedLoads 1149 # Number of loads squashed
353 system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed
354 system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
355 system.cpu.iew.lsq.thread0.squashedStores 813 # Number of stores squashed
356 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
357 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
358 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
359 system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
360 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
361 system.cpu.iew.iewSquashCycles 1817 # Number of cycles IEW is squashing
362 system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking
363 system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
364 system.cpu.iew.iewDispatchedInsts 20337 # Number of instructions dispatched to IQ
365 system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
366 system.cpu.iew.iewDispLoadInsts 2202 # Number of dispatched load instructions
367 system.cpu.iew.iewDispStoreInsts 1748 # Number of dispatched store instructions
368 system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions
369 system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
370 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
371 system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
372 system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
373 system.cpu.iew.predictedNotTakenIncorrect 606 # Number of branches that were predicted not taken incorrectly
374 system.cpu.iew.branchMispredicts 662 # Number of branch mispredicts detected at execute
375 system.cpu.iew.iewExecutedInsts 16344 # Number of executed instructions
376 system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed
377 system.cpu.iew.iewExecSquashedInsts 922 # Number of squashed instructions skipped in execute
378 system.cpu.iew.exec_swp 0 # number of swp insts executed
379 system.cpu.iew.exec_nop 0 # number of nop insts executed
380 system.cpu.iew.exec_refs 3142 # number of memory reference insts executed
381 system.cpu.iew.exec_branches 1619 # Number of branches executed
382 system.cpu.iew.exec_stores 1362 # Number of stores executed
383 system.cpu.iew.exec_rate 0.528197 # Inst execution rate
384 system.cpu.iew.wb_sent 16113 # cumulative count of insts sent to commit
385 system.cpu.iew.wb_count 15919 # cumulative count of insts written-back
386 system.cpu.iew.wb_producers 10115 # num instructions producing a value
387 system.cpu.iew.wb_consumers 15622 # num instructions consuming a value
388 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
389 system.cpu.iew.wb_rate 0.514462 # insts written-back per cycle
390 system.cpu.iew.wb_fanout 0.647484 # average fanout of values written-back
391 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
392 system.cpu.commit.commitSquashedInsts 10589 # The number of squashed insts skipped by commit
393 system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
394 system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted
395 system.cpu.commit.committed_per_cycle::samples 16741 # Number of insts commited each cycle
396 system.cpu.commit.committed_per_cycle::mean 0.582223 # Number of insts commited each cycle
397 system.cpu.commit.committed_per_cycle::stdev 1.458057 # Number of insts commited each cycle
398 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
399 system.cpu.commit.committed_per_cycle::0 13206 78.88% 78.88% # Number of insts commited each cycle
400 system.cpu.commit.committed_per_cycle::1 1328 7.93% 86.82% # Number of insts commited each cycle
401 system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle
402 system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle
403 system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle
404 system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle
405 system.cpu.commit.committed_per_cycle::6 118 0.70% 98.24% # Number of insts commited each cycle
406 system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle
407 system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle
408 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
409 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
410 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
411 system.cpu.commit.committed_per_cycle::total 16741 # Number of insts commited each cycle
412 system.cpu.commit.committedInsts 5380 # Number of instructions committed
413 system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
414 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
415 system.cpu.commit.refs 1988 # Number of memory references committed
416 system.cpu.commit.loads 1053 # Number of loads committed
417 system.cpu.commit.membars 0 # Number of memory barriers committed
418 system.cpu.commit.branches 1208 # Number of branches committed
419 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
420 system.cpu.commit.int_insts 9654 # Number of committed integer instructions.
421 system.cpu.commit.function_calls 0 # Number of function calls committed.
422 system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
423 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
424 system.cpu.rob.rob_reads 36856 # The number of ROB reads
425 system.cpu.rob.rob_writes 42518 # The number of ROB writes
426 system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself
427 system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling
428 system.cpu.committedInsts 5380 # Number of Instructions Simulated
429 system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
430 system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
431 system.cpu.cpi 5.751487 # CPI: Cycles Per Instruction
432 system.cpu.cpi_total 5.751487 # CPI: Total CPI of All Threads
433 system.cpu.ipc 0.173868 # IPC: Instructions Per Cycle
434 system.cpu.ipc_total 0.173868 # IPC: Total IPC of All Threads
435 system.cpu.int_regfile_reads 28772 # number of integer regfile reads
436 system.cpu.int_regfile_writes 17143 # number of integer regfile writes
437 system.cpu.fp_regfile_reads 4 # number of floating regfile reads
438 system.cpu.misc_regfile_reads 7129 # number of misc regfile reads
439 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
440 system.cpu.icache.replacements 0 # number of replacements
441 system.cpu.icache.tagsinuse 144.801510 # Cycle average of tags in use
442 system.cpu.icache.total_refs 1474 # Total number of references to valid blocks.
443 system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
444 system.cpu.icache.avg_refs 4.848684 # Average number of references to valid blocks.
445 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
446 system.cpu.icache.occ_blocks::cpu.inst 144.801510 # Average occupied blocks per requestor
447 system.cpu.icache.occ_percent::cpu.inst 0.070704 # Average percentage of cache occupancy
448 system.cpu.icache.occ_percent::total 0.070704 # Average percentage of cache occupancy
449 system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits
450 system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits
451 system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits
452 system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits
453 system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits
454 system.cpu.icache.overall_hits::total 1474 # number of overall hits
455 system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses
456 system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses
457 system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses
458 system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses
459 system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses
460 system.cpu.icache.overall_misses::total 398 # number of overall misses
461 system.cpu.icache.ReadReq_miss_latency::cpu.inst 20575500 # number of ReadReq miss cycles
462 system.cpu.icache.ReadReq_miss_latency::total 20575500 # number of ReadReq miss cycles
463 system.cpu.icache.demand_miss_latency::cpu.inst 20575500 # number of demand (read+write) miss cycles
464 system.cpu.icache.demand_miss_latency::total 20575500 # number of demand (read+write) miss cycles
465 system.cpu.icache.overall_miss_latency::cpu.inst 20575500 # number of overall miss cycles
466 system.cpu.icache.overall_miss_latency::total 20575500 # number of overall miss cycles
467 system.cpu.icache.ReadReq_accesses::cpu.inst 1872 # number of ReadReq accesses(hits+misses)
468 system.cpu.icache.ReadReq_accesses::total 1872 # number of ReadReq accesses(hits+misses)
469 system.cpu.icache.demand_accesses::cpu.inst 1872 # number of demand (read+write) accesses
470 system.cpu.icache.demand_accesses::total 1872 # number of demand (read+write) accesses
471 system.cpu.icache.overall_accesses::cpu.inst 1872 # number of overall (read+write) accesses
472 system.cpu.icache.overall_accesses::total 1872 # number of overall (read+write) accesses
473 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212607 # miss rate for ReadReq accesses
474 system.cpu.icache.ReadReq_miss_rate::total 0.212607 # miss rate for ReadReq accesses
475 system.cpu.icache.demand_miss_rate::cpu.inst 0.212607 # miss rate for demand accesses
476 system.cpu.icache.demand_miss_rate::total 0.212607 # miss rate for demand accesses
477 system.cpu.icache.overall_miss_rate::cpu.inst 0.212607 # miss rate for overall accesses
478 system.cpu.icache.overall_miss_rate::total 0.212607 # miss rate for overall accesses
479 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51697.236181 # average ReadReq miss latency
480 system.cpu.icache.ReadReq_avg_miss_latency::total 51697.236181 # average ReadReq miss latency
481 system.cpu.icache.demand_avg_miss_latency::cpu.inst 51697.236181 # average overall miss latency
482 system.cpu.icache.demand_avg_miss_latency::total 51697.236181 # average overall miss latency
483 system.cpu.icache.overall_avg_miss_latency::cpu.inst 51697.236181 # average overall miss latency
484 system.cpu.icache.overall_avg_miss_latency::total 51697.236181 # average overall miss latency
485 system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked
486 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
487 system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
488 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
489 system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 # average number of cycles each access was blocked
490 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
491 system.cpu.icache.fast_writes 0 # number of fast writes performed
492 system.cpu.icache.cache_copies 0 # number of cache copies performed
493 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
494 system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
495 system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
496 system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
497 system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
498 system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
499 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
500 system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
501 system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
502 system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
503 system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
504 system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
505 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157000 # number of ReadReq MSHR miss cycles
506 system.cpu.icache.ReadReq_mshr_miss_latency::total 16157000 # number of ReadReq MSHR miss cycles
507 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000 # number of demand (read+write) MSHR miss cycles
508 system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles
509 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles
510 system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles
511 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for ReadReq accesses
512 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162393 # mshr miss rate for ReadReq accesses
513 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for demand accesses
514 system.cpu.icache.demand_mshr_miss_rate::total 0.162393 # mshr miss rate for demand accesses
515 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for overall accesses
516 system.cpu.icache.overall_mshr_miss_rate::total 0.162393 # mshr miss rate for overall accesses
517 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency
518 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency
519 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency
520 system.cpu.icache.demand_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency
521 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency
522 system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency
523 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
524 system.cpu.l2cache.replacements 0 # number of replacements
525 system.cpu.l2cache.tagsinuse 177.956413 # Cycle average of tags in use
526 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
527 system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
528 system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
529 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
530 system.cpu.l2cache.occ_blocks::cpu.inst 144.938671 # Average occupied blocks per requestor
531 system.cpu.l2cache.occ_blocks::cpu.data 33.017743 # Average occupied blocks per requestor
532 system.cpu.l2cache.occ_percent::cpu.inst 0.004423 # Average percentage of cache occupancy
533 system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
534 system.cpu.l2cache.occ_percent::total 0.005431 # Average percentage of cache occupancy
535 system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
536 system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
537 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
538 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
539 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
540 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
541 system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
542 system.cpu.l2cache.ReadReq_misses::cpu.data 72 # number of ReadReq misses
543 system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses
544 system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
545 system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
546 system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
547 system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
548 system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses
549 system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses
550 system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
551 system.cpu.l2cache.overall_misses::total 451 # number of overall misses
552 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842000 # number of ReadReq miss cycles
553 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3892500 # number of ReadReq miss cycles
554 system.cpu.l2cache.ReadReq_miss_latency::total 19734500 # number of ReadReq miss cycles
555 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3990500 # number of ReadExReq miss cycles
556 system.cpu.l2cache.ReadExReq_miss_latency::total 3990500 # number of ReadExReq miss cycles
557 system.cpu.l2cache.demand_miss_latency::cpu.inst 15842000 # number of demand (read+write) miss cycles
558 system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles
559 system.cpu.l2cache.demand_miss_latency::total 23725000 # number of demand (read+write) miss cycles
560 system.cpu.l2cache.overall_miss_latency::cpu.inst 15842000 # number of overall miss cycles
561 system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles
562 system.cpu.l2cache.overall_miss_latency::total 23725000 # number of overall miss cycles
563 system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
564 system.cpu.l2cache.ReadReq_accesses::cpu.data 72 # number of ReadReq accesses(hits+misses)
565 system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses)
566 system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
567 system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
568 system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
569 system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
570 system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses
571 system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
572 system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
573 system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses
574 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses
575 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
576 system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses
577 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
578 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
579 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses
580 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
581 system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses
582 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses
583 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
584 system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses
585 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52283.828383 # average ReadReq miss latency
586 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency
587 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52625.333333 # average ReadReq miss latency
588 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency
589 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency
590 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency
591 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency
592 system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency
593 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency
594 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency
595 system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency
596 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
597 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
598 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
599 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
600 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
601 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
602 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
603 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
604 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
605 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses
606 system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses
607 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
608 system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
609 system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
610 system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
611 system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses
612 system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
613 system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
614 system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
615 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles
616 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles
617 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles
618 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles
619 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles
620 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles
621 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles
622 system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles
623 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles
624 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles
625 system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles
626 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
627 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
628 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses
629 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
630 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
631 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses
632 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
633 system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses
634 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
635 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
636 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses
637 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency
638 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency
639 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency
640 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency
641 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency
642 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
643 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
644 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
645 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
646 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
647 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
648 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
649 system.cpu.dcache.replacements 0 # number of replacements
650 system.cpu.dcache.tagsinuse 83.486269 # Cycle average of tags in use
651 system.cpu.dcache.total_refs 2285 # Total number of references to valid blocks.
652 system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
653 system.cpu.dcache.avg_refs 15.650685 # Average number of references to valid blocks.
654 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
655 system.cpu.dcache.occ_blocks::cpu.data 83.486269 # Average occupied blocks per requestor
656 system.cpu.dcache.occ_percent::cpu.data 0.020382 # Average percentage of cache occupancy
657 system.cpu.dcache.occ_percent::total 0.020382 # Average percentage of cache occupancy
658 system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits
659 system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits
660 system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
661 system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
662 system.cpu.dcache.demand_hits::cpu.data 2285 # number of demand (read+write) hits
663 system.cpu.dcache.demand_hits::total 2285 # number of demand (read+write) hits
664 system.cpu.dcache.overall_hits::cpu.data 2285 # number of overall hits
665 system.cpu.dcache.overall_hits::total 2285 # number of overall hits
666 system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses
667 system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses
668 system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
669 system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
670 system.cpu.dcache.demand_misses::cpu.data 203 # number of demand (read+write) misses
671 system.cpu.dcache.demand_misses::total 203 # number of demand (read+write) misses
672 system.cpu.dcache.overall_misses::cpu.data 203 # number of overall misses
673 system.cpu.dcache.overall_misses::total 203 # number of overall misses
674 system.cpu.dcache.ReadReq_miss_latency::cpu.data 6648000 # number of ReadReq miss cycles
675 system.cpu.dcache.ReadReq_miss_latency::total 6648000 # number of ReadReq miss cycles
676 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4218500 # number of WriteReq miss cycles
677 system.cpu.dcache.WriteReq_miss_latency::total 4218500 # number of WriteReq miss cycles
678 system.cpu.dcache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles
679 system.cpu.dcache.demand_miss_latency::total 10866500 # number of demand (read+write) miss cycles
680 system.cpu.dcache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles
681 system.cpu.dcache.overall_miss_latency::total 10866500 # number of overall miss cycles
682 system.cpu.dcache.ReadReq_accesses::cpu.data 1553 # number of ReadReq accesses(hits+misses)
683 system.cpu.dcache.ReadReq_accesses::total 1553 # number of ReadReq accesses(hits+misses)
684 system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
685 system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
686 system.cpu.dcache.demand_accesses::cpu.data 2488 # number of demand (read+write) accesses
687 system.cpu.dcache.demand_accesses::total 2488 # number of demand (read+write) accesses
688 system.cpu.dcache.overall_accesses::cpu.data 2488 # number of overall (read+write) accesses
689 system.cpu.dcache.overall_accesses::total 2488 # number of overall (read+write) accesses
690 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081777 # miss rate for ReadReq accesses
691 system.cpu.dcache.ReadReq_miss_rate::total 0.081777 # miss rate for ReadReq accesses
692 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
693 system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
694 system.cpu.dcache.demand_miss_rate::cpu.data 0.081592 # miss rate for demand accesses
695 system.cpu.dcache.demand_miss_rate::total 0.081592 # miss rate for demand accesses
696 system.cpu.dcache.overall_miss_rate::cpu.data 0.081592 # miss rate for overall accesses
697 system.cpu.dcache.overall_miss_rate::total 0.081592 # miss rate for overall accesses
698 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency
699 system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency
700 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency
701 system.cpu.dcache.WriteReq_avg_miss_latency::total 55506.578947 # average WriteReq miss latency
702 system.cpu.dcache.demand_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency
703 system.cpu.dcache.demand_avg_miss_latency::total 53529.556650 # average overall miss latency
704 system.cpu.dcache.overall_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency
705 system.cpu.dcache.overall_avg_miss_latency::total 53529.556650 # average overall miss latency
706 system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked
707 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
708 system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
709 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
710 system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.600000 # average number of cycles each access was blocked
711 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
712 system.cpu.dcache.fast_writes 0 # number of fast writes performed
713 system.cpu.dcache.cache_copies 0 # number of cache copies performed
714 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
715 system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
716 system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
717 system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
718 system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
719 system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
720 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses
721 system.cpu.dcache.ReadReq_mshr_misses::total 72 # number of ReadReq MSHR misses
722 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
723 system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
724 system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
725 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
726 system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
727 system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
728 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles
729 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3962500 # number of ReadReq MSHR miss cycles
730 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4066500 # number of WriteReq MSHR miss cycles
731 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4066500 # number of WriteReq MSHR miss cycles
732 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000 # number of demand (read+write) MSHR miss cycles
733 system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles
734 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles
735 system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles
736 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046362 # mshr miss rate for ReadReq accesses
737 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046362 # mshr miss rate for ReadReq accesses
738 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
739 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
740 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for demand accesses
741 system.cpu.dcache.demand_mshr_miss_rate::total 0.059486 # mshr miss rate for demand accesses
742 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for overall accesses
743 system.cpu.dcache.overall_mshr_miss_rate::total 0.059486 # mshr miss rate for overall accesses
744 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency
745 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency
746 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency
747 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53506.578947 # average WriteReq mshr miss latency
748 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency
749 system.cpu.dcache.demand_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency
750 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency
751 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency
752 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
754 ---------- End Simulation Statistics ----------
projects / gem5.git / blob