2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000012 # Number of seconds simulated
4 sim_ticks 12198000 # Number of ticks simulated
5 final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 27776 # Simulator instruction rate (inst/s)
8 host_op_rate 50299 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 62542635 # Simulator tick rate (ticks/s)
10 host_mem_usage 245428 # Number of bytes of host memory used
11 host_seconds 0.20 # Real time elapsed on the host
12 sim_insts 5416 # Number of instructions simulated
13 sim_ops 9809 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 28864 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 0 # Number of bytes written to this memory
17 system.physmem.num_reads 451 # Number of read requests responded to by this memory
18 system.physmem.num_writes 0 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s)
23 system.cpu.workload.num_syscalls 11 # Number of system calls
24 system.cpu.numCycles 24397 # number of cpu cycles simulated
25 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27 system.cpu.BPredUnit.lookups 3206 # Number of BP lookups
28 system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted
29 system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect
30 system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups
31 system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits
32 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
33 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
34 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
35 system.cpu.fetch.icacheStallCycles 7375 # Number of cycles fetch is stalled on an Icache miss
36 system.cpu.fetch.Insts 15410 # Number of instructions fetch has processed
37 system.cpu.fetch.Branches 3206 # Number of branches that fetch encountered
38 system.cpu.fetch.predictedBranches 792 # Number of branches that fetch has predicted taken
39 system.cpu.fetch.Cycles 4170 # Number of cycles fetch has run and was not squashing or blocked
40 system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing
41 system.cpu.fetch.BlockedCycles 3163 # Number of cycles fetch has spent blocked
42 system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
43 system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps
44 system.cpu.fetch.CacheLines 1951 # Number of cache lines fetched
45 system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed
46 system.cpu.fetch.rateDist::samples 16727 # Number of instructions fetched each cycle (Total)
47 system.cpu.fetch.rateDist::mean 1.635918 # Number of instructions fetched each cycle (Total)
48 system.cpu.fetch.rateDist::stdev 3.075272 # Number of instructions fetched each cycle (Total)
49 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
50 system.cpu.fetch.rateDist::0 12659 75.68% 75.68% # Number of instructions fetched each cycle (Total)
51 system.cpu.fetch.rateDist::1 177 1.06% 76.74% # Number of instructions fetched each cycle (Total)
52 system.cpu.fetch.rateDist::2 166 0.99% 77.73% # Number of instructions fetched each cycle (Total)
53 system.cpu.fetch.rateDist::3 214 1.28% 79.01% # Number of instructions fetched each cycle (Total)
54 system.cpu.fetch.rateDist::4 171 1.02% 80.03% # Number of instructions fetched each cycle (Total)
55 system.cpu.fetch.rateDist::5 175 1.05% 81.08% # Number of instructions fetched each cycle (Total)
56 system.cpu.fetch.rateDist::6 250 1.49% 82.57% # Number of instructions fetched each cycle (Total)
57 system.cpu.fetch.rateDist::7 166 0.99% 83.57% # Number of instructions fetched each cycle (Total)
58 system.cpu.fetch.rateDist::8 2749 16.43% 100.00% # Number of instructions fetched each cycle (Total)
59 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
60 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
61 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
62 system.cpu.fetch.rateDist::total 16727 # Number of instructions fetched each cycle (Total)
63 system.cpu.fetch.branchRate 0.131410 # Number of branch fetches per cycle
64 system.cpu.fetch.rate 0.631635 # Number of inst fetches per cycle
65 system.cpu.decode.IdleCycles 7836 # Number of cycles decode is idle
66 system.cpu.decode.BlockedCycles 3109 # Number of cycles decode is blocked
67 system.cpu.decode.RunCycles 3749 # Number of cycles decode is running
68 system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking
69 system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing
70 system.cpu.decode.DecodedInsts 26025 # Number of instructions handled by decode
71 system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing
72 system.cpu.rename.IdleCycles 8180 # Number of cycles rename is idle
73 system.cpu.rename.BlockCycles 1960 # Number of cycles rename is blocking
74 system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst
75 system.cpu.rename.RunCycles 3522 # Number of cycles rename is running
76 system.cpu.rename.UnblockCycles 718 # Number of cycles rename is unblocking
77 system.cpu.rename.RenamedInsts 24463 # Number of instructions processed by rename
78 system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
79 system.cpu.rename.IQFullEvents 50 # Number of times rename has blocked due to IQ full
80 system.cpu.rename.LSQFullEvents 591 # Number of times rename has blocked due to LSQ full
81 system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
82 system.cpu.rename.RenamedOperands 35223 # Number of destination operands rename has renamed
83 system.cpu.rename.RenameLookups 70488 # Number of register rename lookups that rename has made
84 system.cpu.rename.int_rename_lookups 70472 # Number of integer rename lookups
85 system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
86 system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed
87 system.cpu.rename.UndoneMaps 20516 # Number of HB maps that are undone due to squashing
88 system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
89 system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
90 system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer
91 system.cpu.memDep0.insertedLoads 2376 # Number of loads inserted to the mem dependence unit.
92 system.cpu.memDep0.insertedStores 1791 # Number of stores inserted to the mem dependence unit.
93 system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
94 system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
95 system.cpu.iq.iqInstsAdded 21692 # Number of instructions added to the IQ (excludes non-spec)
96 system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
97 system.cpu.iq.iqInstsIssued 17854 # Number of instructions issued
98 system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued
99 system.cpu.iq.iqSquashedInstsExamined 11255 # Number of squashed instructions iterated over during squash; mainly for profiling
100 system.cpu.iq.iqSquashedOperandsExamined 20549 # Number of squashed operands that are examined and possibly removed from graph
101 system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
102 system.cpu.iq.issued_per_cycle::samples 16727 # Number of insts issued each cycle
103 system.cpu.iq.issued_per_cycle::mean 1.067376 # Number of insts issued each cycle
104 system.cpu.iq.issued_per_cycle::stdev 1.893384 # Number of insts issued each cycle
105 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
106 system.cpu.iq.issued_per_cycle::0 11276 67.41% 67.41% # Number of insts issued each cycle
107 system.cpu.iq.issued_per_cycle::1 1383 8.27% 75.68% # Number of insts issued each cycle
108 system.cpu.iq.issued_per_cycle::2 1035 6.19% 81.87% # Number of insts issued each cycle
109 system.cpu.iq.issued_per_cycle::3 667 3.99% 85.86% # Number of insts issued each cycle
110 system.cpu.iq.issued_per_cycle::4 692 4.14% 89.99% # Number of insts issued each cycle
111 system.cpu.iq.issued_per_cycle::5 723 4.32% 94.31% # Number of insts issued each cycle
112 system.cpu.iq.issued_per_cycle::6 673 4.02% 98.34% # Number of insts issued each cycle
113 system.cpu.iq.issued_per_cycle::7 245 1.46% 99.80% # Number of insts issued each cycle
114 system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle
115 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
116 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
117 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
118 system.cpu.iq.issued_per_cycle::total 16727 # Number of insts issued each cycle
119 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
120 system.cpu.iq.fu_full::IntAlu 140 73.30% 73.30% # attempts to use FU when none available
121 system.cpu.iq.fu_full::IntMult 0 0.00% 73.30% # attempts to use FU when none available
122 system.cpu.iq.fu_full::IntDiv 0 0.00% 73.30% # attempts to use FU when none available
123 system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.30% # attempts to use FU when none available
124 system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.30% # attempts to use FU when none available
125 system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.30% # attempts to use FU when none available
126 system.cpu.iq.fu_full::FloatMult 0 0.00% 73.30% # attempts to use FU when none available
127 system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.30% # attempts to use FU when none available
128 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.30% # attempts to use FU when none available
129 system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.30% # attempts to use FU when none available
130 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.30% # attempts to use FU when none available
131 system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.30% # attempts to use FU when none available
132 system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.30% # attempts to use FU when none available
133 system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.30% # attempts to use FU when none available
134 system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.30% # attempts to use FU when none available
135 system.cpu.iq.fu_full::SimdMult 0 0.00% 73.30% # attempts to use FU when none available
136 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.30% # attempts to use FU when none available
137 system.cpu.iq.fu_full::SimdShift 0 0.00% 73.30% # attempts to use FU when none available
138 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.30% # attempts to use FU when none available
139 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.30% # attempts to use FU when none available
140 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.30% # attempts to use FU when none available
141 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.30% # attempts to use FU when none available
142 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.30% # attempts to use FU when none available
143 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.30% # attempts to use FU when none available
144 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.30% # attempts to use FU when none available
145 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.30% # attempts to use FU when none available
146 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.30% # attempts to use FU when none available
147 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.30% # attempts to use FU when none available
148 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.30% # attempts to use FU when none available
149 system.cpu.iq.fu_full::MemRead 30 15.71% 89.01% # attempts to use FU when none available
150 system.cpu.iq.fu_full::MemWrite 21 10.99% 100.00% # attempts to use FU when none available
151 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
152 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
153 system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
154 system.cpu.iq.FU_type_0::IntAlu 14397 80.64% 80.66% # Type of FU issued
155 system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.66% # Type of FU issued
156 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.66% # Type of FU issued
157 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.66% # Type of FU issued
158 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.66% # Type of FU issued
159 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.66% # Type of FU issued
160 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.66% # Type of FU issued
161 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.66% # Type of FU issued
162 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.66% # Type of FU issued
163 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.66% # Type of FU issued
164 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.66% # Type of FU issued
165 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.66% # Type of FU issued
166 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.66% # Type of FU issued
167 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.66% # Type of FU issued
168 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.66% # Type of FU issued
169 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.66% # Type of FU issued
170 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.66% # Type of FU issued
171 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.66% # Type of FU issued
172 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.66% # Type of FU issued
173 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.66% # Type of FU issued
174 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.66% # Type of FU issued
175 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.66% # Type of FU issued
176 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.66% # Type of FU issued
177 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.66% # Type of FU issued
178 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.66% # Type of FU issued
179 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.66% # Type of FU issued
180 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.66% # Type of FU issued
181 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.66% # Type of FU issued
182 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.66% # Type of FU issued
183 system.cpu.iq.FU_type_0::MemRead 1982 11.10% 91.76% # Type of FU issued
184 system.cpu.iq.FU_type_0::MemWrite 1471 8.24% 100.00% # Type of FU issued
185 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
186 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
187 system.cpu.iq.FU_type_0::total 17854 # Type of FU issued
188 system.cpu.iq.rate 0.731811 # Inst issue rate
189 system.cpu.iq.fu_busy_cnt 191 # FU busy when requested
190 system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst)
191 system.cpu.iq.int_inst_queue_reads 52700 # Number of integer instruction queue reads
192 system.cpu.iq.int_inst_queue_writes 32991 # Number of integer instruction queue writes
193 system.cpu.iq.int_inst_queue_wakeup_accesses 16402 # Number of integer instruction queue wakeup accesses
194 system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
195 system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
196 system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
197 system.cpu.iq.int_alu_accesses 18037 # Number of integer alu accesses
198 system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
199 system.cpu.iew.lsq.thread0.forwLoads 151 # Number of loads that had data forwarded from stores
200 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
201 system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed
202 system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed
203 system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
204 system.cpu.iew.lsq.thread0.squashedStores 857 # Number of stores squashed
205 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
206 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
207 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
208 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
209 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
210 system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing
211 system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking
212 system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
213 system.cpu.iew.iewDispatchedInsts 21730 # Number of instructions dispatched to IQ
214 system.cpu.iew.iewDispSquashedInsts 24 # Number of squashed instructions skipped by dispatch
215 system.cpu.iew.iewDispLoadInsts 2376 # Number of dispatched load instructions
216 system.cpu.iew.iewDispStoreInsts 1791 # Number of dispatched store instructions
217 system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
218 system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
219 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
220 system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
221 system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly
222 system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly
223 system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute
224 system.cpu.iew.iewExecutedInsts 16824 # Number of executed instructions
225 system.cpu.iew.iewExecLoadInsts 1844 # Number of load instructions executed
226 system.cpu.iew.iewExecSquashedInsts 1030 # Number of squashed instructions skipped in execute
227 system.cpu.iew.exec_swp 0 # number of swp insts executed
228 system.cpu.iew.exec_nop 0 # number of nop insts executed
229 system.cpu.iew.exec_refs 3203 # number of memory reference insts executed
230 system.cpu.iew.exec_branches 1645 # Number of branches executed
231 system.cpu.iew.exec_stores 1359 # Number of stores executed
232 system.cpu.iew.exec_rate 0.689593 # Inst execution rate
233 system.cpu.iew.wb_sent 16593 # cumulative count of insts sent to commit
234 system.cpu.iew.wb_count 16406 # cumulative count of insts written-back
235 system.cpu.iew.wb_producers 10679 # num instructions producing a value
236 system.cpu.iew.wb_consumers 24448 # num instructions consuming a value
237 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
238 system.cpu.iew.wb_rate 0.672460 # insts written-back per cycle
239 system.cpu.iew.wb_fanout 0.436805 # average fanout of values written-back
240 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
241 system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions
242 system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions
243 system.cpu.commit.commitSquashedInsts 11920 # The number of squashed insts skipped by commit
244 system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
245 system.cpu.commit.branchMispredicts 571 # The number of times a branch was mispredicted
246 system.cpu.commit.committed_per_cycle::samples 14822 # Number of insts commited each cycle
247 system.cpu.commit.committed_per_cycle::mean 0.661787 # Number of insts commited each cycle
248 system.cpu.commit.committed_per_cycle::stdev 1.507902 # Number of insts commited each cycle
249 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
250 system.cpu.commit.committed_per_cycle::0 11181 75.44% 75.44% # Number of insts commited each cycle
251 system.cpu.commit.committed_per_cycle::1 1365 9.21% 84.64% # Number of insts commited each cycle
252 system.cpu.commit.committed_per_cycle::2 653 4.41% 89.05% # Number of insts commited each cycle
253 system.cpu.commit.committed_per_cycle::3 730 4.93% 93.98% # Number of insts commited each cycle
254 system.cpu.commit.committed_per_cycle::4 365 2.46% 96.44% # Number of insts commited each cycle
255 system.cpu.commit.committed_per_cycle::5 129 0.87% 97.31% # Number of insts commited each cycle
256 system.cpu.commit.committed_per_cycle::6 139 0.94% 98.25% # Number of insts commited each cycle
257 system.cpu.commit.committed_per_cycle::7 71 0.48% 98.72% # Number of insts commited each cycle
258 system.cpu.commit.committed_per_cycle::8 189 1.28% 100.00% # Number of insts commited each cycle
259 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
260 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
261 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
262 system.cpu.commit.committed_per_cycle::total 14822 # Number of insts commited each cycle
263 system.cpu.commit.committedInsts 5416 # Number of instructions committed
264 system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed
265 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
266 system.cpu.commit.refs 1990 # Number of memory references committed
267 system.cpu.commit.loads 1056 # Number of loads committed
268 system.cpu.commit.membars 0 # Number of memory barriers committed
269 system.cpu.commit.branches 1214 # Number of branches committed
270 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
271 system.cpu.commit.int_insts 9714 # Number of committed integer instructions.
272 system.cpu.commit.function_calls 0 # Number of function calls committed.
273 system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached
274 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
275 system.cpu.rob.rob_reads 36362 # The number of ROB reads
276 system.cpu.rob.rob_writes 45397 # The number of ROB writes
277 system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself
278 system.cpu.idleCycles 7670 # Total number of cycles that the CPU has spent unscheduled due to idling
279 system.cpu.committedInsts 5416 # Number of Instructions Simulated
280 system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated
281 system.cpu.committedInsts_total 5416 # Number of Instructions Simulated
282 system.cpu.cpi 4.504616 # CPI: Cycles Per Instruction
283 system.cpu.cpi_total 4.504616 # CPI: Total CPI of All Threads
284 system.cpu.ipc 0.221995 # IPC: Instructions Per Cycle
285 system.cpu.ipc_total 0.221995 # IPC: Total IPC of All Threads
286 system.cpu.int_regfile_reads 35460 # number of integer regfile reads
287 system.cpu.int_regfile_writes 22063 # number of integer regfile writes
288 system.cpu.fp_regfile_reads 4 # number of floating regfile reads
289 system.cpu.misc_regfile_reads 7402 # number of misc regfile reads
290 system.cpu.icache.replacements 0 # number of replacements
291 system.cpu.icache.tagsinuse 145.636183 # Cycle average of tags in use
292 system.cpu.icache.total_refs 1561 # Total number of references to valid blocks.
293 system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
294 system.cpu.icache.avg_refs 5.134868 # Average number of references to valid blocks.
295 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
296 system.cpu.icache.occ_blocks::cpu.inst 145.636183 # Average occupied blocks per requestor
297 system.cpu.icache.occ_percent::cpu.inst 0.071111 # Average percentage of cache occupancy
298 system.cpu.icache.occ_percent::total 0.071111 # Average percentage of cache occupancy
299 system.cpu.icache.ReadReq_hits::cpu.inst 1561 # number of ReadReq hits
300 system.cpu.icache.ReadReq_hits::total 1561 # number of ReadReq hits
301 system.cpu.icache.demand_hits::cpu.inst 1561 # number of demand (read+write) hits
302 system.cpu.icache.demand_hits::total 1561 # number of demand (read+write) hits
303 system.cpu.icache.overall_hits::cpu.inst 1561 # number of overall hits
304 system.cpu.icache.overall_hits::total 1561 # number of overall hits
305 system.cpu.icache.ReadReq_misses::cpu.inst 390 # number of ReadReq misses
306 system.cpu.icache.ReadReq_misses::total 390 # number of ReadReq misses
307 system.cpu.icache.demand_misses::cpu.inst 390 # number of demand (read+write) misses
308 system.cpu.icache.demand_misses::total 390 # number of demand (read+write) misses
309 system.cpu.icache.overall_misses::cpu.inst 390 # number of overall misses
310 system.cpu.icache.overall_misses::total 390 # number of overall misses
311 system.cpu.icache.ReadReq_miss_latency::cpu.inst 13866500 # number of ReadReq miss cycles
312 system.cpu.icache.ReadReq_miss_latency::total 13866500 # number of ReadReq miss cycles
313 system.cpu.icache.demand_miss_latency::cpu.inst 13866500 # number of demand (read+write) miss cycles
314 system.cpu.icache.demand_miss_latency::total 13866500 # number of demand (read+write) miss cycles
315 system.cpu.icache.overall_miss_latency::cpu.inst 13866500 # number of overall miss cycles
316 system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles
317 system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses)
318 system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses)
319 system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses
320 system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses
321 system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses
322 system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses
323 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses
324 system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses
325 system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses
326 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency
327 system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency
328 system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency
329 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
330 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
331 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
332 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
333 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
334 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
335 system.cpu.icache.fast_writes 0 # number of fast writes performed
336 system.cpu.icache.cache_copies 0 # number of cache copies performed
337 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits
338 system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
339 system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits
340 system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits
341 system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits
342 system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits
343 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
344 system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
345 system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
346 system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
347 system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
348 system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
349 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles
350 system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles
351 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles
352 system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles
353 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles
354 system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles
355 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses
356 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses
357 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses
358 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency
359 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency
360 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency
361 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
362 system.cpu.dcache.replacements 0 # number of replacements
363 system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use
364 system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks.
365 system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
366 system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks.
367 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
368 system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor
369 system.cpu.dcache.occ_percent::cpu.data 0.020691 # Average percentage of cache occupancy
370 system.cpu.dcache.occ_percent::total 0.020691 # Average percentage of cache occupancy
371 system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits
372 system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits
373 system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
374 system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
375 system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits
376 system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits
377 system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits
378 system.cpu.dcache.overall_hits::total 2365 # number of overall hits
379 system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
380 system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
381 system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
382 system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
383 system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses
384 system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses
385 system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses
386 system.cpu.dcache.overall_misses::total 191 # number of overall misses
387 system.cpu.dcache.ReadReq_miss_latency::cpu.data 4030500 # number of ReadReq miss cycles
388 system.cpu.dcache.ReadReq_miss_latency::total 4030500 # number of ReadReq miss cycles
389 system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles
390 system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles
391 system.cpu.dcache.demand_miss_latency::cpu.data 6948000 # number of demand (read+write) miss cycles
392 system.cpu.dcache.demand_miss_latency::total 6948000 # number of demand (read+write) miss cycles
393 system.cpu.dcache.overall_miss_latency::cpu.data 6948000 # number of overall miss cycles
394 system.cpu.dcache.overall_miss_latency::total 6948000 # number of overall miss cycles
395 system.cpu.dcache.ReadReq_accesses::cpu.data 1622 # number of ReadReq accesses(hits+misses)
396 system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses)
397 system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
398 system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
399 system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses
400 system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses
401 system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses
402 system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses
403 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses
404 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
405 system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses
406 system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses
407 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency
408 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency
409 system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency
410 system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency
411 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
412 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
413 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
414 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
415 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
416 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
417 system.cpu.dcache.fast_writes 0 # number of fast writes performed
418 system.cpu.dcache.cache_copies 0 # number of cache copies performed
419 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
420 system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
421 system.cpu.dcache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits
422 system.cpu.dcache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits
423 system.cpu.dcache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
424 system.cpu.dcache.overall_mshr_hits::total 42 # number of overall MSHR hits
425 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses
426 system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses
427 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
428 system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
429 system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses
430 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses
431 system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
432 system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses
433 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2574000 # number of ReadReq MSHR miss cycles
434 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2574000 # number of ReadReq MSHR miss cycles
435 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles
436 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles
437 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5263500 # number of demand (read+write) MSHR miss cycles
438 system.cpu.dcache.demand_mshr_miss_latency::total 5263500 # number of demand (read+write) MSHR miss cycles
439 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles
440 system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles
441 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses
442 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
443 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses
444 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses
445 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency
446 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency
447 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency
448 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency
449 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
450 system.cpu.l2cache.replacements 0 # number of replacements
451 system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use
452 system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
453 system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks.
454 system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks.
455 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
456 system.cpu.l2cache.occ_blocks::cpu.inst 145.234150 # Average occupied blocks per requestor
457 system.cpu.l2cache.occ_blocks::cpu.data 34.388427 # Average occupied blocks per requestor
458 system.cpu.l2cache.occ_percent::cpu.inst 0.004432 # Average percentage of cache occupancy
459 system.cpu.l2cache.occ_percent::cpu.data 0.001049 # Average percentage of cache occupancy
460 system.cpu.l2cache.occ_percent::total 0.005482 # Average percentage of cache occupancy
461 system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
462 system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
463 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
464 system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
465 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
466 system.cpu.l2cache.overall_hits::total 2 # number of overall hits
467 system.cpu.l2cache.ReadReq_misses::cpu.inst 302 # number of ReadReq misses
468 system.cpu.l2cache.ReadReq_misses::cpu.data 73 # number of ReadReq misses
469 system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses
470 system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
471 system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
472 system.cpu.l2cache.demand_misses::cpu.inst 302 # number of demand (read+write) misses
473 system.cpu.l2cache.demand_misses::cpu.data 149 # number of demand (read+write) misses
474 system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses
475 system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses
476 system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses
477 system.cpu.l2cache.overall_misses::total 451 # number of overall misses
478 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10368000 # number of ReadReq miss cycles
479 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles
480 system.cpu.l2cache.ReadReq_miss_latency::total 12854500 # number of ReadReq miss cycles
481 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles
482 system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles
483 system.cpu.l2cache.demand_miss_latency::cpu.inst 10368000 # number of demand (read+write) miss cycles
484 system.cpu.l2cache.demand_miss_latency::cpu.data 5089500 # number of demand (read+write) miss cycles
485 system.cpu.l2cache.demand_miss_latency::total 15457500 # number of demand (read+write) miss cycles
486 system.cpu.l2cache.overall_miss_latency::cpu.inst 10368000 # number of overall miss cycles
487 system.cpu.l2cache.overall_miss_latency::cpu.data 5089500 # number of overall miss cycles
488 system.cpu.l2cache.overall_miss_latency::total 15457500 # number of overall miss cycles
489 system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
490 system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses)
491 system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses)
492 system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
493 system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
494 system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
495 system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses
496 system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses
497 system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
498 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
499 system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses
500 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses
501 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
502 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
503 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses
504 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
505 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses
506 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
507 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency
508 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency
509 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency
510 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency
511 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency
512 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency
513 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency
514 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
515 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
516 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
517 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
518 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
519 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
520 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
521 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
522 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
523 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses
524 system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses
525 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
526 system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
527 system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
528 system.cpu.l2cache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses
529 system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses
530 system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
531 system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
532 system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
533 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9394000 # number of ReadReq MSHR miss cycles
534 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2263500 # number of ReadReq MSHR miss cycles
535 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11657500 # number of ReadReq MSHR miss cycles
536 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles
537 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles
538 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles
539 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles
540 system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles
541 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles
542 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles
543 system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles
544 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses
545 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
546 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
547 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses
548 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
549 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses
550 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
551 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency
552 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency
553 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency
554 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency
555 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency
556 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency
557 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency
558 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
560 ---------- End Simulation Statistics ----------
projects / gem5.git / blob