stats: bump stats to reflect ruby tester changes
[gem5.git] / tests / quick / se / 00.hello / ref / x86 / linux / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=false
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=System
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14 boot_osflags=a
15 cache_line_size=64
16 clk_domain=system.clk_domain
17 eventq_index=0
18 init_param=0
19 kernel=
20 kernel_addr_check=true
21 load_addr_mask=1099511627775
22 load_offset=0
23 mem_mode=timing
24 mem_ranges=
25 memories=system.physmem
26 mmap_using_noreserve=false
27 multi_thread=false
28 num_work_ids=16
29 readfile=
30 symbolfile=
31 work_begin_ckpt_count=0
32 work_begin_cpu_id_exit=-1
33 work_begin_exit_count=0
34 work_cpus_ckpt_count=0
35 work_end_ckpt_count=0
36 work_end_exit_count=0
37 work_item_id=-1
38 system_port=system.membus.slave[0]
39
40 [system.clk_domain]
41 type=SrcClockDomain
42 clock=1000
43 domain_id=-1
44 eventq_index=0
45 init_perf_level=0
46 voltage_domain=system.voltage_domain
47
48 [system.cpu]
49 type=TimingSimpleCPU
50 children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
51 branchPred=Null
52 checker=Null
53 clk_domain=system.cpu_clk_domain
54 cpu_id=0
55 do_checkpoint_insts=true
56 do_quiesce=true
57 do_statistics_insts=true
58 dtb=system.cpu.dtb
59 eventq_index=0
60 function_trace=false
61 function_trace_start=0
62 interrupts=system.cpu.interrupts
63 isa=system.cpu.isa
64 itb=system.cpu.itb
65 max_insts_all_threads=0
66 max_insts_any_thread=0
67 max_loads_all_threads=0
68 max_loads_any_thread=0
69 numThreads=1
70 profile=0
71 progress_interval=0
72 simpoint_start_insts=
73 socket_id=0
74 switched_out=false
75 system=system
76 tracer=system.cpu.tracer
77 workload=system.cpu.workload
78 dcache_port=system.cpu.dcache.cpu_side
79 icache_port=system.cpu.icache.cpu_side
80
81 [system.cpu.apic_clk_domain]
82 type=DerivedClockDomain
83 clk_divider=16
84 clk_domain=system.cpu_clk_domain
85 eventq_index=0
86
87 [system.cpu.dcache]
88 type=Cache
89 children=tags
90 addr_ranges=0:18446744073709551615
91 assoc=2
92 clk_domain=system.cpu_clk_domain
93 clusivity=mostly_incl
94 demand_mshr_reserve=1
95 eventq_index=0
96 forward_snoops=true
97 hit_latency=2
98 is_read_only=false
99 max_miss_count=0
100 mshrs=4
101 prefetch_on_access=false
102 prefetcher=Null
103 response_latency=2
104 sequential_access=false
105 size=262144
106 system=system
107 tags=system.cpu.dcache.tags
108 tgts_per_mshr=20
109 write_buffers=8
110 writeback_clean=false
111 cpu_side=system.cpu.dcache_port
112 mem_side=system.cpu.toL2Bus.slave[1]
113
114 [system.cpu.dcache.tags]
115 type=LRU
116 assoc=2
117 block_size=64
118 clk_domain=system.cpu_clk_domain
119 eventq_index=0
120 hit_latency=2
121 sequential_access=false
122 size=262144
123
124 [system.cpu.dtb]
125 type=X86TLB
126 children=walker
127 eventq_index=0
128 size=64
129 walker=system.cpu.dtb.walker
130
131 [system.cpu.dtb.walker]
132 type=X86PagetableWalker
133 clk_domain=system.cpu_clk_domain
134 eventq_index=0
135 num_squash_per_cycle=4
136 system=system
137 port=system.cpu.toL2Bus.slave[3]
138
139 [system.cpu.icache]
140 type=Cache
141 children=tags
142 addr_ranges=0:18446744073709551615
143 assoc=2
144 clk_domain=system.cpu_clk_domain
145 clusivity=mostly_incl
146 demand_mshr_reserve=1
147 eventq_index=0
148 forward_snoops=true
149 hit_latency=2
150 is_read_only=true
151 max_miss_count=0
152 mshrs=4
153 prefetch_on_access=false
154 prefetcher=Null
155 response_latency=2
156 sequential_access=false
157 size=131072
158 system=system
159 tags=system.cpu.icache.tags
160 tgts_per_mshr=20
161 write_buffers=8
162 writeback_clean=true
163 cpu_side=system.cpu.icache_port
164 mem_side=system.cpu.toL2Bus.slave[0]
165
166 [system.cpu.icache.tags]
167 type=LRU
168 assoc=2
169 block_size=64
170 clk_domain=system.cpu_clk_domain
171 eventq_index=0
172 hit_latency=2
173 sequential_access=false
174 size=131072
175
176 [system.cpu.interrupts]
177 type=X86LocalApic
178 clk_domain=system.cpu.apic_clk_domain
179 eventq_index=0
180 int_latency=1000
181 pio_addr=2305843009213693952
182 pio_latency=100000
183 system=system
184 int_master=system.membus.slave[2]
185 int_slave=system.membus.master[2]
186 pio=system.membus.master[1]
187
188 [system.cpu.isa]
189 type=X86ISA
190 eventq_index=0
191
192 [system.cpu.itb]
193 type=X86TLB
194 children=walker
195 eventq_index=0
196 size=64
197 walker=system.cpu.itb.walker
198
199 [system.cpu.itb.walker]
200 type=X86PagetableWalker
201 clk_domain=system.cpu_clk_domain
202 eventq_index=0
203 num_squash_per_cycle=4
204 system=system
205 port=system.cpu.toL2Bus.slave[2]
206
207 [system.cpu.l2cache]
208 type=Cache
209 children=tags
210 addr_ranges=0:18446744073709551615
211 assoc=8
212 clk_domain=system.cpu_clk_domain
213 clusivity=mostly_incl
214 demand_mshr_reserve=1
215 eventq_index=0
216 forward_snoops=true
217 hit_latency=20
218 is_read_only=false
219 max_miss_count=0
220 mshrs=20
221 prefetch_on_access=false
222 prefetcher=Null
223 response_latency=20
224 sequential_access=false
225 size=2097152
226 system=system
227 tags=system.cpu.l2cache.tags
228 tgts_per_mshr=12
229 write_buffers=8
230 writeback_clean=false
231 cpu_side=system.cpu.toL2Bus.master[0]
232 mem_side=system.membus.slave[1]
233
234 [system.cpu.l2cache.tags]
235 type=LRU
236 assoc=8
237 block_size=64
238 clk_domain=system.cpu_clk_domain
239 eventq_index=0
240 hit_latency=20
241 sequential_access=false
242 size=2097152
243
244 [system.cpu.toL2Bus]
245 type=CoherentXBar
246 children=snoop_filter
247 clk_domain=system.cpu_clk_domain
248 eventq_index=0
249 forward_latency=0
250 frontend_latency=1
251 response_latency=1
252 snoop_filter=system.cpu.toL2Bus.snoop_filter
253 snoop_response_latency=1
254 system=system
255 use_default_range=false
256 width=32
257 master=system.cpu.l2cache.cpu_side
258 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
259
260 [system.cpu.toL2Bus.snoop_filter]
261 type=SnoopFilter
262 eventq_index=0
263 lookup_latency=0
264 max_capacity=8388608
265 system=system
266
267 [system.cpu.tracer]
268 type=ExeTracer
269 eventq_index=0
270
271 [system.cpu.workload]
272 type=LiveProcess
273 cmd=hello
274 cwd=
275 drivers=
276 egid=100
277 env=
278 errout=cerr
279 euid=100
280 eventq_index=0
281 executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
282 gid=100
283 input=cin
284 kvmInSE=false
285 max_stack_size=67108864
286 output=cout
287 pid=100
288 ppid=99
289 simpoint=0
290 system=system
291 uid=100
292 useArchPT=false
293
294 [system.cpu_clk_domain]
295 type=SrcClockDomain
296 clock=500
297 domain_id=-1
298 eventq_index=0
299 init_perf_level=0
300 voltage_domain=system.voltage_domain
301
302 [system.dvfs_handler]
303 type=DVFSHandler
304 domains=
305 enable=false
306 eventq_index=0
307 sys_clk_domain=system.clk_domain
308 transition_latency=100000000
309
310 [system.membus]
311 type=CoherentXBar
312 clk_domain=system.clk_domain
313 eventq_index=0
314 forward_latency=4
315 frontend_latency=3
316 response_latency=2
317 snoop_filter=Null
318 snoop_response_latency=4
319 system=system
320 use_default_range=false
321 width=16
322 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
323 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
324
325 [system.physmem]
326 type=SimpleMemory
327 bandwidth=73.000000
328 clk_domain=system.clk_domain
329 conf_table_reported=true
330 eventq_index=0
331 in_addr_map=true
332 latency=30000
333 latency_var=0
334 null=false
335 range=0:134217727
336 port=system.membus.master[0]
337
338 [system.voltage_domain]
339 type=VoltageDomain
340 eventq_index=0
341 voltage=1.000000
342