2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000028 # Number of seconds simulated
4 sim_ticks 28357000 # Number of ticks simulated
5 final_tick 28357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 55225 # Simulator instruction rate (inst/s)
8 host_op_rate 100013 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 290910277 # Simulator tick rate (ticks/s)
10 host_mem_usage 285604 # Number of bytes of host memory used
11 host_seconds 0.10 # Real time elapsed on the host
12 sim_insts 5381 # Number of instructions simulated
13 sim_ops 9747 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 512324999 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 302429735 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 814754734 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 512324999 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 512324999 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 512324999 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 302429735 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 814754734 # Total bandwidth to/from this memory (bytes/s)
30 system.cpu.workload.num_syscalls 11 # Number of system calls
31 system.cpu.numCycles 56714 # number of cpu cycles simulated
32 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
34 system.cpu.committedInsts 5381 # Number of instructions committed
35 system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
36 system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
37 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
38 system.cpu.num_func_calls 0 # number of times a function call or return occured
39 system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
40 system.cpu.num_int_insts 9653 # number of integer instructions
41 system.cpu.num_fp_insts 0 # number of float instructions
42 system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
43 system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
44 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
45 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
46 system.cpu.num_mem_refs 1987 # number of memory refs
47 system.cpu.num_load_insts 1052 # Number of load instructions
48 system.cpu.num_store_insts 935 # Number of store instructions
49 system.cpu.num_idle_cycles 0 # Number of idle cycles
50 system.cpu.num_busy_cycles 56714 # Number of busy cycles
51 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
52 system.cpu.idle_fraction 0 # Percentage of idle cycles
53 system.cpu.icache.replacements 0 # number of replacements
54 system.cpu.icache.tagsinuse 105.553131 # Cycle average of tags in use
55 system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
56 system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
57 system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
58 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
59 system.cpu.icache.occ_blocks::cpu.inst 105.553131 # Average occupied blocks per requestor
60 system.cpu.icache.occ_percent::cpu.inst 0.051540 # Average percentage of cache occupancy
61 system.cpu.icache.occ_percent::total 0.051540 # Average percentage of cache occupancy
62 system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
63 system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
64 system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
65 system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits
66 system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits
67 system.cpu.icache.overall_hits::total 6637 # number of overall hits
68 system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
69 system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
70 system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
71 system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
72 system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
73 system.cpu.icache.overall_misses::total 228 # number of overall misses
74 system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles
75 system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles
76 system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles
77 system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
78 system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
79 system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
80 system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
81 system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
82 system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
83 system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses
84 system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses
85 system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses
86 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses
87 system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
88 system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses
89 system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
90 system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
91 system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
92 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
93 system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
94 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
95 system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency
96 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
97 system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency
98 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
99 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
100 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
101 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
102 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
103 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
104 system.cpu.icache.fast_writes 0 # number of fast writes performed
105 system.cpu.icache.cache_copies 0 # number of cache copies performed
106 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
107 system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
108 system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
109 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
110 system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
111 system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
112 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
113 system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
114 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
115 system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
116 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
117 system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
118 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses
119 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses
120 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses
121 system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses
122 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses
123 system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses
124 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
125 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
126 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
127 system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
128 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
129 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
130 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
131 system.cpu.l2cache.replacements 0 # number of replacements
132 system.cpu.l2cache.tagsinuse 134.037527 # Cycle average of tags in use
133 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
134 system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
135 system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
136 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
137 system.cpu.l2cache.occ_blocks::cpu.inst 105.561241 # Average occupied blocks per requestor
138 system.cpu.l2cache.occ_blocks::cpu.data 28.476285 # Average occupied blocks per requestor
139 system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
140 system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
141 system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy
142 system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
143 system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
144 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
145 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
146 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
147 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
148 system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
149 system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
150 system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
151 system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
152 system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
153 system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
154 system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
155 system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
156 system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
157 system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
158 system.cpu.l2cache.overall_misses::total 361 # number of overall misses
159 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
160 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
161 system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
162 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
163 system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
164 system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
165 system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
166 system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
167 system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
168 system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
169 system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
170 system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
171 system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
172 system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
173 system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
174 system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
175 system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
176 system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
177 system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
178 system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
179 system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
180 system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
181 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
182 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
183 system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses
184 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
185 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
186 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
187 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
188 system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses
189 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
190 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
191 system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
192 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
193 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
194 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
195 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
196 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
197 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
198 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
199 system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
200 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
201 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
202 system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
203 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
204 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
205 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
206 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
207 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
208 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
209 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
210 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
211 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
212 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
213 system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
214 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
215 system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
216 system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
217 system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
218 system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
219 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
220 system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
221 system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
222 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
223 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
224 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
225 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
226 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
227 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
228 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
229 system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
230 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
231 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
232 system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
233 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
234 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
235 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
236 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
237 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
238 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
239 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
240 system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
241 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
242 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
243 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
244 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
245 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
246 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
247 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
248 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
249 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
250 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
251 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
252 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
253 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
254 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
255 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
256 system.cpu.dcache.replacements 0 # number of replacements
257 system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
258 system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
259 system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
260 system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
261 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
262 system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
263 system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
264 system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
265 system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
266 system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
267 system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
268 system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
269 system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
270 system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
271 system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
272 system.cpu.dcache.overall_hits::total 1853 # number of overall hits
273 system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
274 system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
275 system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
276 system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
277 system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
278 system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
279 system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
280 system.cpu.dcache.overall_misses::total 134 # number of overall misses
281 system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
282 system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
283 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
284 system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
285 system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
286 system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
287 system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
288 system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
289 system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
290 system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
291 system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
292 system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
293 system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
294 system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
295 system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
296 system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
297 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
298 system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
299 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
300 system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
301 system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
302 system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
303 system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
304 system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
305 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
306 system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
307 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
308 system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
309 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
310 system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
311 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
312 system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
313 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
314 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
315 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
316 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
317 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
318 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
319 system.cpu.dcache.fast_writes 0 # number of fast writes performed
320 system.cpu.dcache.cache_copies 0 # number of cache copies performed
321 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
322 system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
323 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
324 system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
325 system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
326 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
327 system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
328 system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
329 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
330 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
331 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
332 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
333 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
334 system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
335 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
336 system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
337 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
338 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
339 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
340 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
341 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
342 system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
343 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
344 system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
345 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
346 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
347 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
348 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
349 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
350 system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
351 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
352 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
353 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
355 ---------- End Simulation Statistics ----------
projects / gem5.git / blob