2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000029 # Number of seconds simulated
4 sim_ticks 28768000 # Number of ticks simulated
5 final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 320748 # Simulator instruction rate (inst/s)
8 host_tick_rate 940055576 # Simulator tick rate (ticks/s)
9 host_mem_usage 211332 # Number of bytes of host memory used
10 host_seconds 0.03 # Real time elapsed on the host
11 sim_insts 9810 # Number of instructions simulated
12 system.physmem.bytes_read 23104 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 0 # Number of bytes written to this memory
15 system.physmem.num_reads 361 # Number of read requests responded to by this memory
16 system.physmem.num_writes 0 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s)
21 system.cpu.workload.num_syscalls 11 # Number of system calls
22 system.cpu.numCycles 57536 # number of cpu cycles simulated
23 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
24 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
25 system.cpu.num_insts 9810 # Number of instructions executed
26 system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
27 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
28 system.cpu.num_func_calls 0 # number of times a function call or return occured
29 system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
30 system.cpu.num_int_insts 9715 # number of integer instructions
31 system.cpu.num_fp_insts 0 # number of float instructions
32 system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
33 system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
34 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
35 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
36 system.cpu.num_mem_refs 1990 # number of memory refs
37 system.cpu.num_load_insts 1056 # Number of load instructions
38 system.cpu.num_store_insts 934 # Number of store instructions
39 system.cpu.num_idle_cycles 0 # Number of idle cycles
40 system.cpu.num_busy_cycles 57536 # Number of busy cycles
41 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
42 system.cpu.idle_fraction 0 # Percentage of idle cycles
43 system.cpu.icache.replacements 0 # number of replacements
44 system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
45 system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
46 system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
47 system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
48 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
49 system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
50 system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy
51 system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
52 system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
53 system.cpu.icache.overall_hits 6683 # number of overall hits
54 system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
55 system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
56 system.cpu.icache.overall_misses 228 # number of overall misses
57 system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
58 system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
59 system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
60 system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
61 system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
62 system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
63 system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
64 system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
65 system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
66 system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
67 system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
68 system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
69 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
70 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
71 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
72 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
73 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
74 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
75 system.cpu.icache.fast_writes 0 # number of fast writes performed
76 system.cpu.icache.cache_copies 0 # number of cache copies performed
77 system.cpu.icache.writebacks 0 # number of writebacks
78 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
79 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
80 system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
81 system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
82 system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
83 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
84 system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
85 system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
86 system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
87 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
88 system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses
89 system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses
90 system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses
91 system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
92 system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
93 system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
94 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
95 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
96 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
97 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
98 system.cpu.dcache.replacements 0 # number of replacements
99 system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
100 system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
101 system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
102 system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
103 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
104 system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context
105 system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy
106 system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits
107 system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits
108 system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits
109 system.cpu.dcache.overall_hits 1856 # number of overall hits
110 system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
111 system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses
112 system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses
113 system.cpu.dcache.overall_misses 134 # number of overall misses
114 system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
115 system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles
116 system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
117 system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles
118 system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
119 system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
120 system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
121 system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
122 system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses
123 system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses
124 system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses
125 system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses
126 system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
127 system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
128 system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
129 system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
130 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
131 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
132 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
133 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
134 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
135 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
136 system.cpu.dcache.fast_writes 0 # number of fast writes performed
137 system.cpu.dcache.cache_copies 0 # number of cache copies performed
138 system.cpu.dcache.writebacks 0 # number of writebacks
139 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
140 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
141 system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
142 system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses
143 system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses
144 system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses
145 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
146 system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
147 system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles
148 system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles
149 system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles
150 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
151 system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
152 system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses
153 system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses
154 system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses
155 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
156 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
157 system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
158 system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
159 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
160 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
161 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
162 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
163 system.cpu.l2cache.replacements 0 # number of replacements
164 system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
165 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
166 system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
167 system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
168 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
169 system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
170 system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy
171 system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
172 system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
173 system.cpu.l2cache.overall_hits 1 # number of overall hits
174 system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
175 system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
176 system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
177 system.cpu.l2cache.overall_misses 361 # number of overall misses
178 system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles
179 system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
180 system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
181 system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
182 system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
183 system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
184 system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
185 system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
186 system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses
187 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
188 system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
189 system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
190 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
191 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
192 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
193 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
194 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
195 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
196 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
197 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
198 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
199 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
200 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
201 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
202 system.cpu.l2cache.writebacks 0 # number of writebacks
203 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
204 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
205 system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
206 system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
207 system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
208 system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
209 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
210 system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
211 system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
212 system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles
213 system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
214 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
215 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
216 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
217 system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
218 system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
219 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
220 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
221 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
222 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
223 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
224 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
225 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
226 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
228 ---------- End Simulation Statistics ----------
projects / gem5.git / blob