2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000029 # Number of seconds simulated
4 sim_ticks 28768000 # Number of ticks simulated
5 final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 265683 # Simulator instruction rate (inst/s)
8 host_op_rate 480724 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1408532008 # Simulator tick rate (ticks/s)
10 host_mem_usage 216996 # Number of bytes of host memory used
11 host_seconds 0.02 # Real time elapsed on the host
12 sim_insts 5417 # Number of instructions simulated
13 sim_ops 9810 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 23104 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 0 # Number of bytes written to this memory
17 system.physmem.num_reads 361 # Number of read requests responded to by this memory
18 system.physmem.num_writes 0 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s)
23 system.cpu.workload.num_syscalls 11 # Number of system calls
24 system.cpu.numCycles 57536 # number of cpu cycles simulated
25 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27 system.cpu.committedInsts 5417 # Number of instructions committed
28 system.cpu.committedOps 9810 # Number of ops (including micro ops) committed
29 system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
30 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
31 system.cpu.num_func_calls 0 # number of times a function call or return occured
32 system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
33 system.cpu.num_int_insts 9715 # number of integer instructions
34 system.cpu.num_fp_insts 0 # number of float instructions
35 system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
36 system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
37 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
38 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
39 system.cpu.num_mem_refs 1990 # number of memory refs
40 system.cpu.num_load_insts 1056 # Number of load instructions
41 system.cpu.num_store_insts 934 # Number of store instructions
42 system.cpu.num_idle_cycles 0 # Number of idle cycles
43 system.cpu.num_busy_cycles 57536 # Number of busy cycles
44 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
45 system.cpu.idle_fraction 0 # Percentage of idle cycles
46 system.cpu.icache.replacements 0 # number of replacements
47 system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
48 system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
49 system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
50 system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
51 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
52 system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor
53 system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy
54 system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy
55 system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits
56 system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits
57 system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits
58 system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits
59 system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits
60 system.cpu.icache.overall_hits::total 6683 # number of overall hits
61 system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
62 system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
63 system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
64 system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
65 system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
66 system.cpu.icache.overall_misses::total 228 # number of overall misses
67 system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
68 system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
69 system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
70 system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
71 system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
72 system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
73 system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses)
74 system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses)
75 system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses
76 system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses
77 system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses
78 system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses
79 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses
80 system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses
81 system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses
82 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
83 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
84 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
85 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
86 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
87 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
88 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
89 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
90 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
91 system.cpu.icache.fast_writes 0 # number of fast writes performed
92 system.cpu.icache.cache_copies 0 # number of cache copies performed
93 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
94 system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
95 system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
96 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
97 system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
98 system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
99 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
100 system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
101 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
102 system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
103 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
104 system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
105 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses
106 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses
107 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses
108 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
109 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
110 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
111 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
112 system.cpu.dcache.replacements 0 # number of replacements
113 system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
114 system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
115 system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
116 system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
117 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
118 system.cpu.dcache.occ_blocks::cpu.data 80.668870 # Average occupied blocks per requestor
119 system.cpu.dcache.occ_percent::cpu.data 0.019695 # Average percentage of cache occupancy
120 system.cpu.dcache.occ_percent::total 0.019695 # Average percentage of cache occupancy
121 system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits
122 system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits
123 system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
124 system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
125 system.cpu.dcache.demand_hits::cpu.data 1856 # number of demand (read+write) hits
126 system.cpu.dcache.demand_hits::total 1856 # number of demand (read+write) hits
127 system.cpu.dcache.overall_hits::cpu.data 1856 # number of overall hits
128 system.cpu.dcache.overall_hits::total 1856 # number of overall hits
129 system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
130 system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
131 system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
132 system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
133 system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
134 system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
135 system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
136 system.cpu.dcache.overall_misses::total 134 # number of overall misses
137 system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
138 system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
139 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles
140 system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles
141 system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles
142 system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles
143 system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles
144 system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles
145 system.cpu.dcache.ReadReq_accesses::cpu.data 1056 # number of ReadReq accesses(hits+misses)
146 system.cpu.dcache.ReadReq_accesses::total 1056 # number of ReadReq accesses(hits+misses)
147 system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
148 system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
149 system.cpu.dcache.demand_accesses::cpu.data 1990 # number of demand (read+write) accesses
150 system.cpu.dcache.demand_accesses::total 1990 # number of demand (read+write) accesses
151 system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses
152 system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses
153 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses
154 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
155 system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses
156 system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses
157 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
158 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
159 system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
160 system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
161 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
163 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
164 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
165 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
166 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
167 system.cpu.dcache.fast_writes 0 # number of fast writes performed
168 system.cpu.dcache.cache_copies 0 # number of cache copies performed
169 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
170 system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
171 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
172 system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
173 system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
174 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
175 system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
176 system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
177 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
178 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
179 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
180 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
181 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
182 system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
183 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
184 system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
185 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses
186 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses
187 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses
188 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses
189 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
190 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
191 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
192 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
193 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
194 system.cpu.l2cache.replacements 0 # number of replacements
195 system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
196 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
197 system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
198 system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
199 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
200 system.cpu.l2cache.occ_blocks::cpu.inst 105.370729 # Average occupied blocks per requestor
201 system.cpu.l2cache.occ_blocks::cpu.data 28.438613 # Average occupied blocks per requestor
202 system.cpu.l2cache.occ_percent::cpu.inst 0.003216 # Average percentage of cache occupancy
203 system.cpu.l2cache.occ_percent::cpu.data 0.000868 # Average percentage of cache occupancy
204 system.cpu.l2cache.occ_percent::total 0.004084 # Average percentage of cache occupancy
205 system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
206 system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
207 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
208 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
209 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
210 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
211 system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
212 system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
213 system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
214 system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
215 system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
216 system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
217 system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
218 system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
219 system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
220 system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
221 system.cpu.l2cache.overall_misses::total 361 # number of overall misses
222 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
223 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
224 system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
225 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
226 system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
227 system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
228 system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
229 system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
230 system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
231 system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
232 system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
233 system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
234 system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
235 system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
236 system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
237 system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
238 system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
239 system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
240 system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
241 system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
242 system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
243 system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
244 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
245 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
246 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
247 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
248 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
249 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
250 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
251 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
252 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
253 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
254 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
255 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
256 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
257 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
258 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
259 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
260 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
261 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
262 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
263 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
264 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
265 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
266 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
267 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
268 system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
269 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
270 system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
271 system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
272 system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
273 system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
274 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
275 system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
276 system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
277 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
278 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
279 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
280 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
281 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
282 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
283 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
284 system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
285 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
286 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
287 system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
288 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
289 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
290 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
291 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
292 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
293 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
294 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
295 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
296 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
297 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
298 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
299 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
300 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
301 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
302 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
304 ---------- End Simulation Statistics ----------
projects / gem5.git / blob