708085ca546e2acdfb6dfc1e3c52611e7e92e7f5
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 load_addr_mask=1099511627775
23 memories=system.physmem
27 work_begin_ckpt_count=0
28 work_begin_cpu_id_exit=-1
29 work_begin_exit_count=0
30 work_cpus_ckpt_count=0
34 system_port=system.membus.slave[0]
40 voltage_domain=system.voltage_domain
44 children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
53 branchPred=system.cpu.branchPred
56 clk_domain=system.cpu_clk_domain
67 do_checkpoint_insts=true
69 do_statistics_insts=true
77 fuPool=system.cpu.fuPool
79 function_trace_start=0
84 interrupts=system.cpu.interrupts
85 isa=system.cpu.isa0 system.cpu.isa1
89 max_insts_all_threads=0
90 max_insts_any_thread=0
91 max_loads_all_threads=0
92 max_loads_any_thread=0
103 renameToDecodeDelay=1
108 simpoint_start_insts=
109 smtCommitPolicy=RoundRobin
110 smtFetchPolicy=SingleThread
111 smtIQPolicy=Partitioned
113 smtLSQPolicy=Partitioned
115 smtNumFetchingThreads=1
116 smtROBPolicy=Partitioned
119 store_set_clear_period=250000
122 tracer=system.cpu.tracer
126 workload=system.cpu.workload0 system.cpu.workload1
127 dcache_port=system.cpu.dcache.cpu_side
128 icache_port=system.cpu.icache.cpu_side
130 [system.cpu.branchPred]
136 choicePredictorSize=8192
139 globalPredictorSize=8192
142 localHistoryTableSize=2048
143 localPredictorSize=2048
150 addr_ranges=0:18446744073709551615
152 clk_domain=system.cpu_clk_domain
159 prefetch_on_access=false
164 tags=system.cpu.dcache.tags
168 cpu_side=system.cpu.dcache_port
169 mem_side=system.cpu.toL2Bus.slave[1]
171 [system.cpu.dcache.tags]
175 clk_domain=system.cpu_clk_domain
187 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
188 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
191 [system.cpu.fuPool.FUList0]
196 opList=system.cpu.fuPool.FUList0.opList
198 [system.cpu.fuPool.FUList0.opList]
205 [system.cpu.fuPool.FUList1]
207 children=opList0 opList1
210 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
212 [system.cpu.fuPool.FUList1.opList0]
219 [system.cpu.fuPool.FUList1.opList1]
226 [system.cpu.fuPool.FUList2]
228 children=opList0 opList1 opList2
231 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
233 [system.cpu.fuPool.FUList2.opList0]
240 [system.cpu.fuPool.FUList2.opList1]
247 [system.cpu.fuPool.FUList2.opList2]
254 [system.cpu.fuPool.FUList3]
256 children=opList0 opList1 opList2
259 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
261 [system.cpu.fuPool.FUList3.opList0]
268 [system.cpu.fuPool.FUList3.opList1]
275 [system.cpu.fuPool.FUList3.opList2]
282 [system.cpu.fuPool.FUList4]
287 opList=system.cpu.fuPool.FUList4.opList
289 [system.cpu.fuPool.FUList4.opList]
296 [system.cpu.fuPool.FUList5]
298 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
301 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
303 [system.cpu.fuPool.FUList5.opList00]
310 [system.cpu.fuPool.FUList5.opList01]
317 [system.cpu.fuPool.FUList5.opList02]
324 [system.cpu.fuPool.FUList5.opList03]
331 [system.cpu.fuPool.FUList5.opList04]
338 [system.cpu.fuPool.FUList5.opList05]
345 [system.cpu.fuPool.FUList5.opList06]
352 [system.cpu.fuPool.FUList5.opList07]
359 [system.cpu.fuPool.FUList5.opList08]
366 [system.cpu.fuPool.FUList5.opList09]
373 [system.cpu.fuPool.FUList5.opList10]
380 [system.cpu.fuPool.FUList5.opList11]
387 [system.cpu.fuPool.FUList5.opList12]
394 [system.cpu.fuPool.FUList5.opList13]
401 [system.cpu.fuPool.FUList5.opList14]
408 [system.cpu.fuPool.FUList5.opList15]
415 [system.cpu.fuPool.FUList5.opList16]
419 opClass=SimdFloatMisc
422 [system.cpu.fuPool.FUList5.opList17]
426 opClass=SimdFloatMult
429 [system.cpu.fuPool.FUList5.opList18]
433 opClass=SimdFloatMultAcc
436 [system.cpu.fuPool.FUList5.opList19]
440 opClass=SimdFloatSqrt
443 [system.cpu.fuPool.FUList6]
448 opList=system.cpu.fuPool.FUList6.opList
450 [system.cpu.fuPool.FUList6.opList]
457 [system.cpu.fuPool.FUList7]
459 children=opList0 opList1
462 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
464 [system.cpu.fuPool.FUList7.opList0]
471 [system.cpu.fuPool.FUList7.opList1]
478 [system.cpu.fuPool.FUList8]
483 opList=system.cpu.fuPool.FUList8.opList
485 [system.cpu.fuPool.FUList8.opList]
495 addr_ranges=0:18446744073709551615
497 clk_domain=system.cpu_clk_domain
504 prefetch_on_access=false
509 tags=system.cpu.icache.tags
513 cpu_side=system.cpu.icache_port
514 mem_side=system.cpu.toL2Bus.slave[0]
516 [system.cpu.icache.tags]
520 clk_domain=system.cpu_clk_domain
525 [system.cpu.interrupts]
545 addr_ranges=0:18446744073709551615
547 clk_domain=system.cpu_clk_domain
554 prefetch_on_access=false
559 tags=system.cpu.l2cache.tags
563 cpu_side=system.cpu.toL2Bus.master[0]
564 mem_side=system.membus.slave[1]
566 [system.cpu.l2cache.tags]
570 clk_domain=system.cpu_clk_domain
577 clk_domain=system.cpu_clk_domain
581 use_default_range=false
583 master=system.cpu.l2cache.cpu_side
584 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
590 [system.cpu.workload0]
599 executable=tests/test-progs/hello/bin/alpha/linux/hello
602 max_stack_size=67108864
610 [system.cpu.workload1]
619 executable=tests/test-progs/hello/bin/alpha/linux/hello
622 max_stack_size=67108864
630 [system.cpu_clk_domain]
634 voltage_domain=system.voltage_domain
638 clk_domain=system.clk_domain
642 use_default_range=false
644 master=system.physmem.port
645 slave=system.system_port system.cpu.l2cache.mem_side
650 addr_mapping=RaBaChCo
654 clk_domain=system.clk_domain
655 conf_table_reported=true
657 device_rowbuffer_size=1024
661 mem_sched_policy=frfcfs
667 static_backend_latency=10000
668 static_frontend_latency=10000
680 write_high_thresh_perc=70
681 write_low_thresh_perc=0
682 port=system.membus.master[0]
684 [system.voltage_domain]