2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000013 # Number of seconds simulated
4 sim_ticks 13202000 # Number of ticks simulated
5 final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 91406 # Simulator instruction rate (inst/s)
8 host_op_rate 91394 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 94452628 # Simulator tick rate (ticks/s)
10 host_mem_usage 210624 # Number of bytes of host memory used
11 host_seconds 0.14 # Real time elapsed on the host
12 sim_insts 12773 # Number of instructions simulated
13 sim_ops 12773 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 62144 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 0 # Number of bytes written to this memory
17 system.physmem.num_reads 971 # Number of read requests responded to by this memory
18 system.physmem.num_writes 0 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 4707165581 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 3024996213 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_total 4707165581 # Total bandwidth to/from this memory (bytes/s)
23 system.cpu.dtb.fetch_hits 0 # ITB hits
24 system.cpu.dtb.fetch_misses 0 # ITB misses
25 system.cpu.dtb.fetch_acv 0 # ITB acv
26 system.cpu.dtb.fetch_accesses 0 # ITB accesses
27 system.cpu.dtb.read_hits 3722 # DTB read hits
28 system.cpu.dtb.read_misses 94 # DTB read misses
29 system.cpu.dtb.read_acv 0 # DTB read access violations
30 system.cpu.dtb.read_accesses 3816 # DTB read accesses
31 system.cpu.dtb.write_hits 1984 # DTB write hits
32 system.cpu.dtb.write_misses 61 # DTB write misses
33 system.cpu.dtb.write_acv 0 # DTB write access violations
34 system.cpu.dtb.write_accesses 2045 # DTB write accesses
35 system.cpu.dtb.data_hits 5706 # DTB hits
36 system.cpu.dtb.data_misses 155 # DTB misses
37 system.cpu.dtb.data_acv 0 # DTB access violations
38 system.cpu.dtb.data_accesses 5861 # DTB accesses
39 system.cpu.itb.fetch_hits 4091 # ITB hits
40 system.cpu.itb.fetch_misses 56 # ITB misses
41 system.cpu.itb.fetch_acv 0 # ITB acv
42 system.cpu.itb.fetch_accesses 4147 # ITB accesses
43 system.cpu.itb.read_hits 0 # DTB read hits
44 system.cpu.itb.read_misses 0 # DTB read misses
45 system.cpu.itb.read_acv 0 # DTB read access violations
46 system.cpu.itb.read_accesses 0 # DTB read accesses
47 system.cpu.itb.write_hits 0 # DTB write hits
48 system.cpu.itb.write_misses 0 # DTB write misses
49 system.cpu.itb.write_acv 0 # DTB write access violations
50 system.cpu.itb.write_accesses 0 # DTB write accesses
51 system.cpu.itb.data_hits 0 # DTB hits
52 system.cpu.itb.data_misses 0 # DTB misses
53 system.cpu.itb.data_acv 0 # DTB access violations
54 system.cpu.itb.data_accesses 0 # DTB accesses
55 system.cpu.workload0.num_syscalls 17 # Number of system calls
56 system.cpu.workload1.num_syscalls 17 # Number of system calls
57 system.cpu.numCycles 26405 # number of cpu cycles simulated
58 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
59 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
60 system.cpu.BPredUnit.lookups 5174 # Number of BP lookups
61 system.cpu.BPredUnit.condPredicted 2964 # Number of conditional branches predicted
62 system.cpu.BPredUnit.condIncorrect 1252 # Number of conditional branches incorrect
63 system.cpu.BPredUnit.BTBLookups 3548 # Number of BTB lookups
64 system.cpu.BPredUnit.BTBHits 1004 # Number of BTB hits
65 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
66 system.cpu.BPredUnit.usedRAS 734 # Number of times the RAS was used to get a target.
67 system.cpu.BPredUnit.RASInCorrect 158 # Number of incorrect RAS predictions.
68 system.cpu.fetch.icacheStallCycles 1115 # Number of cycles fetch is stalled on an Icache miss
69 system.cpu.fetch.Insts 28962 # Number of instructions fetch has processed
70 system.cpu.fetch.Branches 5174 # Number of branches that fetch encountered
71 system.cpu.fetch.predictedBranches 1738 # Number of branches that fetch has predicted taken
72 system.cpu.fetch.Cycles 4987 # Number of cycles fetch has run and was not squashing or blocked
73 system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing
74 system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
75 system.cpu.fetch.CacheLines 4091 # Number of cache lines fetched
76 system.cpu.fetch.IcacheSquashes 637 # Number of outstanding Icache misses that were squashed
77 system.cpu.fetch.rateDist::samples 20201 # Number of instructions fetched each cycle (Total)
78 system.cpu.fetch.rateDist::mean 1.433691 # Number of instructions fetched each cycle (Total)
79 system.cpu.fetch.rateDist::stdev 2.801868 # Number of instructions fetched each cycle (Total)
80 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
81 system.cpu.fetch.rateDist::0 15214 75.31% 75.31% # Number of instructions fetched each cycle (Total)
82 system.cpu.fetch.rateDist::1 449 2.22% 77.54% # Number of instructions fetched each cycle (Total)
83 system.cpu.fetch.rateDist::2 365 1.81% 79.34% # Number of instructions fetched each cycle (Total)
84 system.cpu.fetch.rateDist::3 384 1.90% 81.24% # Number of instructions fetched each cycle (Total)
85 system.cpu.fetch.rateDist::4 390 1.93% 83.17% # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::5 328 1.62% 84.80% # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::6 404 2.00% 86.80% # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.rateDist::7 329 1.63% 88.43% # Number of instructions fetched each cycle (Total)
89 system.cpu.fetch.rateDist::8 2338 11.57% 100.00% # Number of instructions fetched each cycle (Total)
90 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
91 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
92 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
93 system.cpu.fetch.rateDist::total 20201 # Number of instructions fetched each cycle (Total)
94 system.cpu.fetch.branchRate 0.195948 # Number of branch fetches per cycle
95 system.cpu.fetch.rate 1.096838 # Number of inst fetches per cycle
96 system.cpu.decode.IdleCycles 27985 # Number of cycles decode is idle
97 system.cpu.decode.BlockedCycles 5533 # Number of cycles decode is blocked
98 system.cpu.decode.RunCycles 4328 # Number of cycles decode is running
99 system.cpu.decode.UnblockCycles 445 # Number of cycles decode is unblocking
100 system.cpu.decode.SquashCycles 1869 # Number of cycles decode is squashing
101 system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch
102 system.cpu.decode.BranchMispred 315 # Number of times decode detected a branch misprediction
103 system.cpu.decode.DecodedInsts 25962 # Number of instructions handled by decode
104 system.cpu.decode.SquashedInsts 512 # Number of squashed instructions handled by decode
105 system.cpu.rename.SquashCycles 1869 # Number of cycles rename is squashing
106 system.cpu.rename.IdleCycles 28534 # Number of cycles rename is idle
107 system.cpu.rename.BlockCycles 2990 # Number of cycles rename is blocking
108 system.cpu.rename.serializeStallCycles 752 # count of cycles rename stalled for serializing inst
109 system.cpu.rename.RunCycles 4136 # Number of cycles rename is running
110 system.cpu.rename.UnblockCycles 1879 # Number of cycles rename is unblocking
111 system.cpu.rename.RenamedInsts 24542 # Number of instructions processed by rename
112 system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
113 system.cpu.rename.LSQFullEvents 1739 # Number of times rename has blocked due to LSQ full
114 system.cpu.rename.RenamedOperands 18358 # Number of destination operands rename has renamed
115 system.cpu.rename.RenameLookups 30575 # Number of register rename lookups that rename has made
116 system.cpu.rename.int_rename_lookups 30541 # Number of integer rename lookups
117 system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
118 system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed
119 system.cpu.rename.UndoneMaps 9192 # Number of HB maps that are undone due to squashing
120 system.cpu.rename.serializingInsts 52 # count of serializing insts renamed
121 system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed
122 system.cpu.rename.skidInsts 4646 # count of insts added to the skid buffer
123 system.cpu.memDep0.insertedLoads 2308 # Number of loads inserted to the mem dependence unit.
124 system.cpu.memDep0.insertedStores 1190 # Number of stores inserted to the mem dependence unit.
125 system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
126 system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
127 system.cpu.memDep1.insertedLoads 2319 # Number of loads inserted to the mem dependence unit.
128 system.cpu.memDep1.insertedStores 1181 # Number of stores inserted to the mem dependence unit.
129 system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads.
130 system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
131 system.cpu.iq.iqInstsAdded 22288 # Number of instructions added to the IQ (excludes non-spec)
132 system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
133 system.cpu.iq.iqInstsIssued 19435 # Number of instructions issued
134 system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued
135 system.cpu.iq.iqSquashedInstsExamined 8694 # Number of squashed instructions iterated over during squash; mainly for profiling
136 system.cpu.iq.iqSquashedOperandsExamined 4709 # Number of squashed operands that are examined and possibly removed from graph
137 system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
138 system.cpu.iq.issued_per_cycle::samples 20201 # Number of insts issued each cycle
139 system.cpu.iq.issued_per_cycle::mean 0.962081 # Number of insts issued each cycle
140 system.cpu.iq.issued_per_cycle::stdev 1.481018 # Number of insts issued each cycle
141 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
142 system.cpu.iq.issued_per_cycle::0 11990 59.35% 59.35% # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::1 2928 14.49% 73.85% # Number of insts issued each cycle
144 system.cpu.iq.issued_per_cycle::2 2232 11.05% 84.90% # Number of insts issued each cycle
145 system.cpu.iq.issued_per_cycle::3 1366 6.76% 91.66% # Number of insts issued each cycle
146 system.cpu.iq.issued_per_cycle::4 891 4.41% 96.07% # Number of insts issued each cycle
147 system.cpu.iq.issued_per_cycle::5 479 2.37% 98.44% # Number of insts issued each cycle
148 system.cpu.iq.issued_per_cycle::6 237 1.17% 99.61% # Number of insts issued each cycle
149 system.cpu.iq.issued_per_cycle::7 60 0.30% 99.91% # Number of insts issued each cycle
150 system.cpu.iq.issued_per_cycle::8 18 0.09% 100.00% # Number of insts issued each cycle
151 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
152 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
153 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
154 system.cpu.iq.issued_per_cycle::total 20201 # Number of insts issued each cycle
155 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
156 system.cpu.iq.fu_full::IntAlu 9 4.92% 4.92% # attempts to use FU when none available
157 system.cpu.iq.fu_full::IntMult 0 0.00% 4.92% # attempts to use FU when none available
158 system.cpu.iq.fu_full::IntDiv 0 0.00% 4.92% # attempts to use FU when none available
159 system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.92% # attempts to use FU when none available
160 system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.92% # attempts to use FU when none available
161 system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.92% # attempts to use FU when none available
162 system.cpu.iq.fu_full::FloatMult 0 0.00% 4.92% # attempts to use FU when none available
163 system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.92% # attempts to use FU when none available
164 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.92% # attempts to use FU when none available
165 system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.92% # attempts to use FU when none available
166 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.92% # attempts to use FU when none available
167 system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.92% # attempts to use FU when none available
168 system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.92% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.92% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.92% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdMult 0 0.00% 4.92% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.92% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdShift 0 0.00% 4.92% # attempts to use FU when none available
174 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.92% # attempts to use FU when none available
175 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.92% # attempts to use FU when none available
176 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.92% # attempts to use FU when none available
177 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.92% # attempts to use FU when none available
178 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.92% # attempts to use FU when none available
179 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.92% # attempts to use FU when none available
180 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.92% # attempts to use FU when none available
181 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.92% # attempts to use FU when none available
182 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.92% # attempts to use FU when none available
183 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.92% # attempts to use FU when none available
184 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.92% # attempts to use FU when none available
185 system.cpu.iq.fu_full::MemRead 106 57.92% 62.84% # attempts to use FU when none available
186 system.cpu.iq.fu_full::MemWrite 68 37.16% 100.00% # attempts to use FU when none available
187 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
188 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
189 system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
190 system.cpu.iq.FU_type_0::IntAlu 6617 67.89% 67.91% # Type of FU issued
191 system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.92% # Type of FU issued
192 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.92% # Type of FU issued
193 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.94% # Type of FU issued
194 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued
195 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued
196 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued
197 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued
198 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued
199 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued
200 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued
201 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued
202 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued
208 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued
209 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued
210 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued
211 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued
212 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued
213 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued
214 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued
215 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.94% # Type of FU issued
216 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued
217 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued
218 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued
219 system.cpu.iq.FU_type_0::MemRead 2056 21.09% 89.03% # Type of FU issued
220 system.cpu.iq.FU_type_0::MemWrite 1069 10.97% 100.00% # Type of FU issued
221 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
222 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
223 system.cpu.iq.FU_type_0::total 9747 # Type of FU issued
224 system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
225 system.cpu.iq.FU_type_1::IntAlu 6565 67.76% 67.78% # Type of FU issued
226 system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued
227 system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued
228 system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued
229 system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued
230 system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued
231 system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued
232 system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued
233 system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued
234 system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued
235 system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued
236 system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued
237 system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued
238 system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued
239 system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued
240 system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued
241 system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued
242 system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued
243 system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued
244 system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued
245 system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued
246 system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued
247 system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued
248 system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued
249 system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued
250 system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued
251 system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued
252 system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued
253 system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued
254 system.cpu.iq.FU_type_1::MemRead 2046 21.12% 88.93% # Type of FU issued
255 system.cpu.iq.FU_type_1::MemWrite 1072 11.07% 100.00% # Type of FU issued
256 system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
257 system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
258 system.cpu.iq.FU_type_1::total 9688 # Type of FU issued
259 system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
260 system.cpu.iq.FU_type::IntAlu 13182 67.83% 67.85% # Type of FU issued
261 system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued
262 system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued
263 system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued
264 system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued
265 system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued
266 system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued
267 system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued
268 system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued
269 system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued
270 system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued
271 system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued
272 system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued
273 system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued
274 system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued
275 system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued
276 system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued
277 system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued
278 system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued
279 system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued
280 system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued
281 system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued
282 system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued
283 system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued
284 system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued
285 system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued
286 system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued
287 system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued
288 system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued
289 system.cpu.iq.FU_type::MemRead 4102 21.11% 88.98% # Type of FU issued
290 system.cpu.iq.FU_type::MemWrite 2141 11.02% 100.00% # Type of FU issued
291 system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
292 system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
293 system.cpu.iq.FU_type::total 19435 # Type of FU issued
294 system.cpu.iq.rate 0.736035 # Inst issue rate
295 system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested
296 system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested
297 system.cpu.iq.fu_busy_cnt::total 183 # FU busy when requested
298 system.cpu.iq.fu_busy_rate::0 0.004837 # FU busy rate (busy events/executed inst)
299 system.cpu.iq.fu_busy_rate::1 0.004579 # FU busy rate (busy events/executed inst)
300 system.cpu.iq.fu_busy_rate::total 0.009416 # FU busy rate (busy events/executed inst)
301 system.cpu.iq.int_inst_queue_reads 59279 # Number of integer instruction queue reads
302 system.cpu.iq.int_inst_queue_writes 31036 # Number of integer instruction queue writes
303 system.cpu.iq.int_inst_queue_wakeup_accesses 17747 # Number of integer instruction queue wakeup accesses
304 system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
305 system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
306 system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
307 system.cpu.iq.int_alu_accesses 19592 # Number of integer alu accesses
308 system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
309 system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores
310 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
311 system.cpu.iew.lsq.thread0.squashedLoads 1123 # Number of loads squashed
312 system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
313 system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
314 system.cpu.iew.lsq.thread0.squashedStores 325 # Number of stores squashed
315 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
316 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
317 system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
318 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
319 system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores
320 system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
321 system.cpu.iew.lsq.thread1.squashedLoads 1134 # Number of loads squashed
322 system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
323 system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations
324 system.cpu.iew.lsq.thread1.squashedStores 316 # Number of stores squashed
325 system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
326 system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
327 system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
328 system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
329 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
330 system.cpu.iew.iewSquashCycles 1869 # Number of cycles IEW is squashing
331 system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking
332 system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
333 system.cpu.iew.iewDispatchedInsts 22477 # Number of instructions dispatched to IQ
334 system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
335 system.cpu.iew.iewDispLoadInsts 4627 # Number of dispatched load instructions
336 system.cpu.iew.iewDispStoreInsts 2371 # Number of dispatched store instructions
337 system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions
338 system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
339 system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
340 system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
341 system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly
342 system.cpu.iew.predictedNotTakenIncorrect 882 # Number of branches that were predicted not taken incorrectly
343 system.cpu.iew.branchMispredicts 1100 # Number of branch mispredicts detected at execute
344 system.cpu.iew.iewExecutedInsts 18425 # Number of executed instructions
345 system.cpu.iew.iewExecLoadInsts::0 1901 # Number of load instructions executed
346 system.cpu.iew.iewExecLoadInsts::1 1921 # Number of load instructions executed
347 system.cpu.iew.iewExecLoadInsts::total 3822 # Number of load instructions executed
348 system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute
349 system.cpu.iew.exec_swp::0 0 # number of swp insts executed
350 system.cpu.iew.exec_swp::1 0 # number of swp insts executed
351 system.cpu.iew.exec_swp::total 0 # number of swp insts executed
352 system.cpu.iew.exec_nop::0 75 # number of nop insts executed
353 system.cpu.iew.exec_nop::1 65 # number of nop insts executed
354 system.cpu.iew.exec_nop::total 140 # number of nop insts executed
355 system.cpu.iew.exec_refs::0 2932 # number of memory reference insts executed
356 system.cpu.iew.exec_refs::1 2948 # number of memory reference insts executed
357 system.cpu.iew.exec_refs::total 5880 # number of memory reference insts executed
358 system.cpu.iew.exec_branches::0 1521 # Number of branches executed
359 system.cpu.iew.exec_branches::1 1526 # Number of branches executed
360 system.cpu.iew.exec_branches::total 3047 # Number of branches executed
361 system.cpu.iew.exec_stores::0 1031 # Number of stores executed
362 system.cpu.iew.exec_stores::1 1027 # Number of stores executed
363 system.cpu.iew.exec_stores::total 2058 # Number of stores executed
364 system.cpu.iew.exec_rate 0.697785 # Inst execution rate
365 system.cpu.iew.wb_sent::0 9024 # cumulative count of insts sent to commit
366 system.cpu.iew.wb_sent::1 8991 # cumulative count of insts sent to commit
367 system.cpu.iew.wb_sent::total 18015 # cumulative count of insts sent to commit
368 system.cpu.iew.wb_count::0 8913 # cumulative count of insts written-back
369 system.cpu.iew.wb_count::1 8854 # cumulative count of insts written-back
370 system.cpu.iew.wb_count::total 17767 # cumulative count of insts written-back
371 system.cpu.iew.wb_producers::0 4555 # num instructions producing a value
372 system.cpu.iew.wb_producers::1 4549 # num instructions producing a value
373 system.cpu.iew.wb_producers::total 9104 # num instructions producing a value
374 system.cpu.iew.wb_consumers::0 5963 # num instructions consuming a value
375 system.cpu.iew.wb_consumers::1 5961 # num instructions consuming a value
376 system.cpu.iew.wb_consumers::total 11924 # num instructions consuming a value
377 system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
378 system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
379 system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
380 system.cpu.iew.wb_rate::0 0.337550 # insts written-back per cycle
381 system.cpu.iew.wb_rate::1 0.335315 # insts written-back per cycle
382 system.cpu.iew.wb_rate::total 0.672865 # insts written-back per cycle
383 system.cpu.iew.wb_fanout::0 0.763877 # average fanout of values written-back
384 system.cpu.iew.wb_fanout::1 0.763127 # average fanout of values written-back
385 system.cpu.iew.wb_fanout::total 1.527004 # average fanout of values written-back
386 system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
387 system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
388 system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
389 system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
390 system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions
391 system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit
392 system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
393 system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted
394 system.cpu.commit.committed_per_cycle::samples 20176 # Number of insts commited each cycle
395 system.cpu.commit.committed_per_cycle::mean 0.634764 # Number of insts commited each cycle
396 system.cpu.commit.committed_per_cycle::stdev 1.436773 # Number of insts commited each cycle
397 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
398 system.cpu.commit.committed_per_cycle::0 14631 72.52% 72.52% # Number of insts commited each cycle
399 system.cpu.commit.committed_per_cycle::1 2865 14.20% 86.72% # Number of insts commited each cycle
400 system.cpu.commit.committed_per_cycle::2 1050 5.20% 91.92% # Number of insts commited each cycle
401 system.cpu.commit.committed_per_cycle::3 518 2.57% 94.49% # Number of insts commited each cycle
402 system.cpu.commit.committed_per_cycle::4 346 1.71% 96.20% # Number of insts commited each cycle
403 system.cpu.commit.committed_per_cycle::5 239 1.18% 97.39% # Number of insts commited each cycle
404 system.cpu.commit.committed_per_cycle::6 208 1.03% 98.42% # Number of insts commited each cycle
405 system.cpu.commit.committed_per_cycle::7 91 0.45% 98.87% # Number of insts commited each cycle
406 system.cpu.commit.committed_per_cycle::8 228 1.13% 100.00% # Number of insts commited each cycle
407 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
408 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
409 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
410 system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle
411 system.cpu.commit.committedInsts::0 6403 # Number of instructions committed
412 system.cpu.commit.committedInsts::1 6404 # Number of instructions committed
413 system.cpu.commit.committedInsts::total 12807 # Number of instructions committed
414 system.cpu.commit.committedOps::0 6403 # Number of ops (including micro ops) committed
415 system.cpu.commit.committedOps::1 6404 # Number of ops (including micro ops) committed
416 system.cpu.commit.committedOps::total 12807 # Number of ops (including micro ops) committed
417 system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
418 system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
419 system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
420 system.cpu.commit.refs::0 2050 # Number of memory references committed
421 system.cpu.commit.refs::1 2050 # Number of memory references committed
422 system.cpu.commit.refs::total 4100 # Number of memory references committed
423 system.cpu.commit.loads::0 1185 # Number of loads committed
424 system.cpu.commit.loads::1 1185 # Number of loads committed
425 system.cpu.commit.loads::total 2370 # Number of loads committed
426 system.cpu.commit.membars::0 0 # Number of memory barriers committed
427 system.cpu.commit.membars::1 0 # Number of memory barriers committed
428 system.cpu.commit.membars::total 0 # Number of memory barriers committed
429 system.cpu.commit.branches::0 1051 # Number of branches committed
430 system.cpu.commit.branches::1 1051 # Number of branches committed
431 system.cpu.commit.branches::total 2102 # Number of branches committed
432 system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
433 system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
434 system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
435 system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions.
436 system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions.
437 system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions.
438 system.cpu.commit.function_calls::0 127 # Number of function calls committed.
439 system.cpu.commit.function_calls::1 127 # Number of function calls committed.
440 system.cpu.commit.function_calls::total 254 # Number of function calls committed.
441 system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached
442 system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
443 system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
444 system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
445 system.cpu.rob.rob_reads 101307 # The number of ROB reads
446 system.cpu.rob.rob_writes 46689 # The number of ROB writes
447 system.cpu.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself
448 system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling
449 system.cpu.committedInsts::0 6386 # Number of Instructions Simulated
450 system.cpu.committedInsts::1 6387 # Number of Instructions Simulated
451 system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated
452 system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated
453 system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
454 system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction
455 system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction
456 system.cpu.cpi_total 2.067251 # CPI: Total CPI of All Threads
457 system.cpu.ipc::0 0.241848 # IPC: Instructions Per Cycle
458 system.cpu.ipc::1 0.241886 # IPC: Instructions Per Cycle
459 system.cpu.ipc_total 0.483734 # IPC: Total IPC of All Threads
460 system.cpu.int_regfile_reads 23374 # number of integer regfile reads
461 system.cpu.int_regfile_writes 13316 # number of integer regfile writes
462 system.cpu.fp_regfile_reads 16 # number of floating regfile reads
463 system.cpu.fp_regfile_writes 4 # number of floating regfile writes
464 system.cpu.misc_regfile_reads 2 # number of misc regfile reads
465 system.cpu.misc_regfile_writes 2 # number of misc regfile writes
466 system.cpu.icache.replacements::0 6 # number of replacements
467 system.cpu.icache.replacements::1 0 # number of replacements
468 system.cpu.icache.replacements::total 6 # number of replacements
469 system.cpu.icache.tagsinuse 314.165301 # Cycle average of tags in use
470 system.cpu.icache.total_refs 3236 # Total number of references to valid blocks.
471 system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks.
472 system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks.
473 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
474 system.cpu.icache.occ_blocks::cpu.inst 314.165301 # Average occupied blocks per requestor
475 system.cpu.icache.occ_percent::cpu.inst 0.153401 # Average percentage of cache occupancy
476 system.cpu.icache.occ_percent::total 0.153401 # Average percentage of cache occupancy
477 system.cpu.icache.ReadReq_hits::cpu.inst 3236 # number of ReadReq hits
478 system.cpu.icache.ReadReq_hits::total 3236 # number of ReadReq hits
479 system.cpu.icache.demand_hits::cpu.inst 3236 # number of demand (read+write) hits
480 system.cpu.icache.demand_hits::total 3236 # number of demand (read+write) hits
481 system.cpu.icache.overall_hits::cpu.inst 3236 # number of overall hits
482 system.cpu.icache.overall_hits::total 3236 # number of overall hits
483 system.cpu.icache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
484 system.cpu.icache.ReadReq_misses::total 855 # number of ReadReq misses
485 system.cpu.icache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
486 system.cpu.icache.demand_misses::total 855 # number of demand (read+write) misses
487 system.cpu.icache.overall_misses::cpu.inst 855 # number of overall misses
488 system.cpu.icache.overall_misses::total 855 # number of overall misses
489 system.cpu.icache.ReadReq_miss_latency::cpu.inst 30710500 # number of ReadReq miss cycles
490 system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles
491 system.cpu.icache.demand_miss_latency::cpu.inst 30710500 # number of demand (read+write) miss cycles
492 system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles
493 system.cpu.icache.overall_miss_latency::cpu.inst 30710500 # number of overall miss cycles
494 system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles
495 system.cpu.icache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses)
496 system.cpu.icache.ReadReq_accesses::total 4091 # number of ReadReq accesses(hits+misses)
497 system.cpu.icache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses
498 system.cpu.icache.demand_accesses::total 4091 # number of demand (read+write) accesses
499 system.cpu.icache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses
500 system.cpu.icache.overall_accesses::total 4091 # number of overall (read+write) accesses
501 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.208995 # miss rate for ReadReq accesses
502 system.cpu.icache.demand_miss_rate::cpu.inst 0.208995 # miss rate for demand accesses
503 system.cpu.icache.overall_miss_rate::cpu.inst 0.208995 # miss rate for overall accesses
504 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450 # average ReadReq miss latency
505 system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency
506 system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency
507 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
508 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
509 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
510 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
511 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
512 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
513 system.cpu.icache.fast_writes 0 # number of fast writes performed
514 system.cpu.icache.cache_copies 0 # number of cache copies performed
515 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits
516 system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits
517 system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits
518 system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits
519 system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits
520 system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits
521 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses
522 system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses
523 system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses
524 system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses
525 system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses
526 system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses
527 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22267000 # number of ReadReq MSHR miss cycles
528 system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles
529 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22267000 # number of demand (read+write) MSHR miss cycles
530 system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles
531 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22267000 # number of overall MSHR miss cycles
532 system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles
533 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for ReadReq accesses
534 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for demand accesses
535 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for overall accesses
536 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35570.287540 # average ReadReq mshr miss latency
537 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency
538 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency
539 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
540 system.cpu.dcache.replacements::0 0 # number of replacements
541 system.cpu.dcache.replacements::1 0 # number of replacements
542 system.cpu.dcache.replacements::total 0 # number of replacements
543 system.cpu.dcache.tagsinuse 216.133399 # Cycle average of tags in use
544 system.cpu.dcache.total_refs 4323 # Total number of references to valid blocks.
545 system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks.
546 system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks.
547 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
548 system.cpu.dcache.occ_blocks::cpu.data 216.133399 # Average occupied blocks per requestor
549 system.cpu.dcache.occ_percent::cpu.data 0.052767 # Average percentage of cache occupancy
550 system.cpu.dcache.occ_percent::total 0.052767 # Average percentage of cache occupancy
551 system.cpu.dcache.ReadReq_hits::cpu.data 3303 # number of ReadReq hits
552 system.cpu.dcache.ReadReq_hits::total 3303 # number of ReadReq hits
553 system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
554 system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits
555 system.cpu.dcache.demand_hits::cpu.data 4323 # number of demand (read+write) hits
556 system.cpu.dcache.demand_hits::total 4323 # number of demand (read+write) hits
557 system.cpu.dcache.overall_hits::cpu.data 4323 # number of overall hits
558 system.cpu.dcache.overall_hits::total 4323 # number of overall hits
559 system.cpu.dcache.ReadReq_misses::cpu.data 308 # number of ReadReq misses
560 system.cpu.dcache.ReadReq_misses::total 308 # number of ReadReq misses
561 system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses
562 system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses
563 system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses
564 system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses
565 system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses
566 system.cpu.dcache.overall_misses::total 1018 # number of overall misses
567 system.cpu.dcache.ReadReq_miss_latency::cpu.data 11179500 # number of ReadReq miss cycles
568 system.cpu.dcache.ReadReq_miss_latency::total 11179500 # number of ReadReq miss cycles
569 system.cpu.dcache.WriteReq_miss_latency::cpu.data 24106500 # number of WriteReq miss cycles
570 system.cpu.dcache.WriteReq_miss_latency::total 24106500 # number of WriteReq miss cycles
571 system.cpu.dcache.demand_miss_latency::cpu.data 35286000 # number of demand (read+write) miss cycles
572 system.cpu.dcache.demand_miss_latency::total 35286000 # number of demand (read+write) miss cycles
573 system.cpu.dcache.overall_miss_latency::cpu.data 35286000 # number of overall miss cycles
574 system.cpu.dcache.overall_miss_latency::total 35286000 # number of overall miss cycles
575 system.cpu.dcache.ReadReq_accesses::cpu.data 3611 # number of ReadReq accesses(hits+misses)
576 system.cpu.dcache.ReadReq_accesses::total 3611 # number of ReadReq accesses(hits+misses)
577 system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
578 system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
579 system.cpu.dcache.demand_accesses::cpu.data 5341 # number of demand (read+write) accesses
580 system.cpu.dcache.demand_accesses::total 5341 # number of demand (read+write) accesses
581 system.cpu.dcache.overall_accesses::cpu.data 5341 # number of overall (read+write) accesses
582 system.cpu.dcache.overall_accesses::total 5341 # number of overall (read+write) accesses
583 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085295 # miss rate for ReadReq accesses
584 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses
585 system.cpu.dcache.demand_miss_rate::cpu.data 0.190601 # miss rate for demand accesses
586 system.cpu.dcache.overall_miss_rate::cpu.data 0.190601 # miss rate for overall accesses
587 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36297.077922 # average ReadReq miss latency
588 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33952.816901 # average WriteReq miss latency
589 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency
590 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency
591 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
592 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
593 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
594 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
595 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
596 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
597 system.cpu.dcache.fast_writes 0 # number of fast writes performed
598 system.cpu.dcache.cache_copies 0 # number of cache copies performed
599 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 107 # number of ReadReq MSHR hits
600 system.cpu.dcache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits
601 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits
602 system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits
603 system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits
604 system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits
605 system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits
606 system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits
607 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses
608 system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses
609 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
610 system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
611 system.cpu.dcache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses
612 system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses
613 system.cpu.dcache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses
614 system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses
615 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7376000 # number of ReadReq MSHR miss cycles
616 system.cpu.dcache.ReadReq_mshr_miss_latency::total 7376000 # number of ReadReq MSHR miss cycles
617 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5298000 # number of WriteReq MSHR miss cycles
618 system.cpu.dcache.WriteReq_mshr_miss_latency::total 5298000 # number of WriteReq MSHR miss cycles
619 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12674000 # number of demand (read+write) MSHR miss cycles
620 system.cpu.dcache.demand_mshr_miss_latency::total 12674000 # number of demand (read+write) MSHR miss cycles
621 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12674000 # number of overall MSHR miss cycles
622 system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles
623 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055663 # mshr miss rate for ReadReq accesses
624 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
625 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for demand accesses
626 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for overall accesses
627 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36696.517413 # average ReadReq mshr miss latency
628 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36287.671233 # average WriteReq mshr miss latency
629 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency
630 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency
631 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
632 system.cpu.l2cache.replacements::0 0 # number of replacements
633 system.cpu.l2cache.replacements::1 0 # number of replacements
634 system.cpu.l2cache.replacements::total 0 # number of replacements
635 system.cpu.l2cache.tagsinuse 435.235373 # Cycle average of tags in use
636 system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
637 system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks.
638 system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks.
639 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
640 system.cpu.l2cache.occ_blocks::cpu.inst 314.499531 # Average occupied blocks per requestor
641 system.cpu.l2cache.occ_blocks::cpu.data 120.735842 # Average occupied blocks per requestor
642 system.cpu.l2cache.occ_percent::cpu.inst 0.009598 # Average percentage of cache occupancy
643 system.cpu.l2cache.occ_percent::cpu.data 0.003685 # Average percentage of cache occupancy
644 system.cpu.l2cache.occ_percent::total 0.013282 # Average percentage of cache occupancy
645 system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
646 system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
647 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
648 system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
649 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
650 system.cpu.l2cache.overall_hits::total 2 # number of overall hits
651 system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses
652 system.cpu.l2cache.ReadReq_misses::cpu.data 201 # number of ReadReq misses
653 system.cpu.l2cache.ReadReq_misses::total 825 # number of ReadReq misses
654 system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
655 system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
656 system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses
657 system.cpu.l2cache.demand_misses::cpu.data 347 # number of demand (read+write) misses
658 system.cpu.l2cache.demand_misses::total 971 # number of demand (read+write) misses
659 system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses
660 system.cpu.l2cache.overall_misses::cpu.data 347 # number of overall misses
661 system.cpu.l2cache.overall_misses::total 971 # number of overall misses
662 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21475000 # number of ReadReq miss cycles
663 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6995000 # number of ReadReq miss cycles
664 system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles
665 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5066000 # number of ReadExReq miss cycles
666 system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles
667 system.cpu.l2cache.demand_miss_latency::cpu.inst 21475000 # number of demand (read+write) miss cycles
668 system.cpu.l2cache.demand_miss_latency::cpu.data 12061000 # number of demand (read+write) miss cycles
669 system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles
670 system.cpu.l2cache.overall_miss_latency::cpu.inst 21475000 # number of overall miss cycles
671 system.cpu.l2cache.overall_miss_latency::cpu.data 12061000 # number of overall miss cycles
672 system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles
673 system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses)
674 system.cpu.l2cache.ReadReq_accesses::cpu.data 201 # number of ReadReq accesses(hits+misses)
675 system.cpu.l2cache.ReadReq_accesses::total 827 # number of ReadReq accesses(hits+misses)
676 system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
677 system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
678 system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses
679 system.cpu.l2cache.demand_accesses::cpu.data 347 # number of demand (read+write) accesses
680 system.cpu.l2cache.demand_accesses::total 973 # number of demand (read+write) accesses
681 system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses
682 system.cpu.l2cache.overall_accesses::cpu.data 347 # number of overall (read+write) accesses
683 system.cpu.l2cache.overall_accesses::total 973 # number of overall (read+write) accesses
684 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses
685 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
686 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
687 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses
688 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
689 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
690 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
691 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103 # average ReadReq miss latency
692 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025 # average ReadReq miss latency
693 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137 # average ReadExReq miss latency
694 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency
695 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency
696 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency
697 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency
698 system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked
699 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
700 system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
701 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
702 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked
703 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
704 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
705 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
706 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses
707 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses
708 system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses
709 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
710 system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
711 system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses
712 system.cpu.l2cache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses
713 system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses
714 system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses
715 system.cpu.l2cache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses
716 system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses
717 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19514500 # number of ReadReq MSHR miss cycles
718 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6372500 # number of ReadReq MSHR miss cycles
719 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles
720 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4614000 # number of ReadExReq MSHR miss cycles
721 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles
722 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19514500 # number of demand (read+write) MSHR miss cycles
723 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10986500 # number of demand (read+write) MSHR miss cycles
724 system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles
725 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19514500 # number of overall MSHR miss cycles
726 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10986500 # number of overall MSHR miss cycles
727 system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles
728 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses
729 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
730 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
731 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses
732 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
733 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
734 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
735 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179 # average ReadReq mshr miss latency
736 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100 # average ReadReq mshr miss latency
737 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726 # average ReadExReq mshr miss latency
738 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency
739 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency
740 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency
741 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency
742 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
744 ---------- End Simulation Statistics ----------
projects / gem5.git / blob