tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=true
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=DerivO3CPU
  58 children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
  59 LFSTSize=1024
  60 LQEntries=32
  61 LSQCheckLoads=true
  62 LSQDepCheckShift=4
  63 SQEntries=32
  64 SSITSize=1024
  65 activity=0
  66 backComSize=5
  67 branchPred=system.cpu.branchPred
  68 cacheStorePorts=200
  69 checker=Null
  70 clk_domain=system.cpu_clk_domain
  71 commitToDecodeDelay=1
  72 commitToFetchDelay=1
  73 commitToIEWDelay=1
  74 commitToRenameDelay=1
  75 commitWidth=8
  76 cpu_id=0
  77 decodeToFetchDelay=1
  78 decodeToRenameDelay=1
  79 decodeWidth=8
  80 default_p_state=UNDEFINED
  81 dispatchWidth=8
  82 do_checkpoint_insts=true
  83 do_quiesce=true
  84 do_statistics_insts=true
  85 dtb=system.cpu.dtb
  86 eventq_index=0
  87 fetchBufferSize=64
  88 fetchQueueSize=32
  89 fetchToDecodeDelay=1
  90 fetchTrapLatency=1
  91 fetchWidth=8
  92 forwardComSize=5
  93 fuPool=system.cpu.fuPool
  94 function_trace=false
  95 function_trace_start=0
  96 iewToCommitDelay=1
  97 iewToDecodeDelay=1
  98 iewToFetchDelay=1
  99 iewToRenameDelay=1
 100 interrupts=system.cpu.interrupts0 system.cpu.interrupts1
 101 isa=system.cpu.isa0 system.cpu.isa1
 102 issueToExecuteDelay=1
 103 issueWidth=8
 104 itb=system.cpu.itb
 105 max_insts_all_threads=0
 106 max_insts_any_thread=0
 107 max_loads_all_threads=0
 108 max_loads_any_thread=0
 109 needsTSO=false
 110 numIQEntries=64
 111 numPhysCCRegs=0
 112 numPhysFloatRegs=256
 113 numPhysIntRegs=256
 114 numROBEntries=192
 115 numRobs=1
 116 numThreads=2
 117 p_state_clk_gate_bins=20
 118 p_state_clk_gate_max=1000000000000
 119 p_state_clk_gate_min=1000
 120 power_model=Null
 121 profile=0
 122 progress_interval=0
 123 renameToDecodeDelay=1
 124 renameToFetchDelay=1
 125 renameToIEWDelay=2
 126 renameToROBDelay=1
 127 renameWidth=8
 128 simpoint_start_insts=
 129 smtCommitPolicy=RoundRobin
 130 smtFetchPolicy=SingleThread
 131 smtIQPolicy=Partitioned
 132 smtIQThreshold=100
 133 smtLSQPolicy=Partitioned
 134 smtLSQThreshold=100
 135 smtNumFetchingThreads=1
 136 smtROBPolicy=Partitioned
 137 smtROBThreshold=100
 138 socket_id=0
 139 squashWidth=8
 140 store_set_clear_period=250000
 141 switched_out=false
 142 syscallRetryLatency=10000
 143 system=system
 144 tracer=system.cpu.tracer
 145 trapLatency=13
 146 wbWidth=8
 147 workload=system.cpu.workload0 system.cpu.workload1
 148 dcache_port=system.cpu.dcache.cpu_side
 149 icache_port=system.cpu.icache.cpu_side
 150
 151 [system.cpu.branchPred]
 152 type=TournamentBP
 153 BTBEntries=4096
 154 BTBTagSize=16
 155 RASSize=16
 156 choiceCtrBits=2
 157 choicePredictorSize=8192
 158 eventq_index=0
 159 globalCtrBits=2
 160 globalPredictorSize=8192
 161 indirectHashGHR=true
 162 indirectHashTargets=true
 163 indirectPathLength=3
 164 indirectSets=256
 165 indirectTagSize=16
 166 indirectWays=2
 167 instShiftAmt=2
 168 localCtrBits=2
 169 localHistoryTableSize=2048
 170 localPredictorSize=2048
 171 numThreads=2
 172 useIndirect=true
 173
 174 [system.cpu.dcache]
 175 type=Cache
 176 children=tags
 177 addr_ranges=0:18446744073709551615:0:0:0:0
 178 assoc=2
 179 clk_domain=system.cpu_clk_domain
 180 clusivity=mostly_incl
 181 data_latency=2
 182 default_p_state=UNDEFINED
 183 demand_mshr_reserve=1
 184 eventq_index=0
 185 is_read_only=false
 186 max_miss_count=0
 187 mshrs=4
 188 p_state_clk_gate_bins=20
 189 p_state_clk_gate_max=1000000000000
 190 p_state_clk_gate_min=1000
 191 power_model=Null
 192 prefetch_on_access=false
 193 prefetcher=Null
 194 response_latency=2
 195 sequential_access=false
 196 size=262144
 197 system=system
 198 tag_latency=2
 199 tags=system.cpu.dcache.tags
 200 tgts_per_mshr=20
 201 write_buffers=8
 202 writeback_clean=false
 203 cpu_side=system.cpu.dcache_port
 204 mem_side=system.cpu.toL2Bus.slave[1]
 205
 206 [system.cpu.dcache.tags]
 207 type=LRU
 208 assoc=2
 209 block_size=64
 210 clk_domain=system.cpu_clk_domain
 211 data_latency=2
 212 default_p_state=UNDEFINED
 213 eventq_index=0
 214 p_state_clk_gate_bins=20
 215 p_state_clk_gate_max=1000000000000
 216 p_state_clk_gate_min=1000
 217 power_model=Null
 218 sequential_access=false
 219 size=262144
 220 tag_latency=2
 221
 222 [system.cpu.dtb]
 223 type=AlphaTLB
 224 eventq_index=0
 225 size=64
 226
 227 [system.cpu.fuPool]
 228 type=FUPool
 229 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 230 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 231 eventq_index=0
 232
 233 [system.cpu.fuPool.FUList0]
 234 type=FUDesc
 235 children=opList
 236 count=6
 237 eventq_index=0
 238 opList=system.cpu.fuPool.FUList0.opList
 239
 240 [system.cpu.fuPool.FUList0.opList]
 241 type=OpDesc
 242 eventq_index=0
 243 opClass=IntAlu
 244 opLat=1
 245 pipelined=true
 246
 247 [system.cpu.fuPool.FUList1]
 248 type=FUDesc
 249 children=opList0 opList1
 250 count=2
 251 eventq_index=0
 252 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 253
 254 [system.cpu.fuPool.FUList1.opList0]
 255 type=OpDesc
 256 eventq_index=0
 257 opClass=IntMult
 258 opLat=3
 259 pipelined=true
 260
 261 [system.cpu.fuPool.FUList1.opList1]
 262 type=OpDesc
 263 eventq_index=0
 264 opClass=IntDiv
 265 opLat=20
 266 pipelined=false
 267
 268 [system.cpu.fuPool.FUList2]
 269 type=FUDesc
 270 children=opList0 opList1 opList2
 271 count=4
 272 eventq_index=0
 273 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 274
 275 [system.cpu.fuPool.FUList2.opList0]
 276 type=OpDesc
 277 eventq_index=0
 278 opClass=FloatAdd
 279 opLat=2
 280 pipelined=true
 281
 282 [system.cpu.fuPool.FUList2.opList1]
 283 type=OpDesc
 284 eventq_index=0
 285 opClass=FloatCmp
 286 opLat=2
 287 pipelined=true
 288
 289 [system.cpu.fuPool.FUList2.opList2]
 290 type=OpDesc
 291 eventq_index=0
 292 opClass=FloatCvt
 293 opLat=2
 294 pipelined=true
 295
 296 [system.cpu.fuPool.FUList3]
 297 type=FUDesc
 298 children=opList0 opList1 opList2 opList3 opList4
 299 count=2
 300 eventq_index=0
 301 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
 302
 303 [system.cpu.fuPool.FUList3.opList0]
 304 type=OpDesc
 305 eventq_index=0
 306 opClass=FloatMult
 307 opLat=4
 308 pipelined=true
 309
 310 [system.cpu.fuPool.FUList3.opList1]
 311 type=OpDesc
 312 eventq_index=0
 313 opClass=FloatMultAcc
 314 opLat=5
 315 pipelined=true
 316
 317 [system.cpu.fuPool.FUList3.opList2]
 318 type=OpDesc
 319 eventq_index=0
 320 opClass=FloatMisc
 321 opLat=3
 322 pipelined=true
 323
 324 [system.cpu.fuPool.FUList3.opList3]
 325 type=OpDesc
 326 eventq_index=0
 327 opClass=FloatDiv
 328 opLat=12
 329 pipelined=false
 330
 331 [system.cpu.fuPool.FUList3.opList4]
 332 type=OpDesc
 333 eventq_index=0
 334 opClass=FloatSqrt
 335 opLat=24
 336 pipelined=false
 337
 338 [system.cpu.fuPool.FUList4]
 339 type=FUDesc
 340 children=opList0 opList1
 341 count=0
 342 eventq_index=0
 343 opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
 344
 345 [system.cpu.fuPool.FUList4.opList0]
 346 type=OpDesc
 347 eventq_index=0
 348 opClass=MemRead
 349 opLat=1
 350 pipelined=true
 351
 352 [system.cpu.fuPool.FUList4.opList1]
 353 type=OpDesc
 354 eventq_index=0
 355 opClass=FloatMemRead
 356 opLat=1
 357 pipelined=true
 358
 359 [system.cpu.fuPool.FUList5]
 360 type=FUDesc
 361 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 362 count=4
 363 eventq_index=0
 364 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 365
 366 [system.cpu.fuPool.FUList5.opList00]
 367 type=OpDesc
 368 eventq_index=0
 369 opClass=SimdAdd
 370 opLat=1
 371 pipelined=true
 372
 373 [system.cpu.fuPool.FUList5.opList01]
 374 type=OpDesc
 375 eventq_index=0
 376 opClass=SimdAddAcc
 377 opLat=1
 378 pipelined=true
 379
 380 [system.cpu.fuPool.FUList5.opList02]
 381 type=OpDesc
 382 eventq_index=0
 383 opClass=SimdAlu
 384 opLat=1
 385 pipelined=true
 386
 387 [system.cpu.fuPool.FUList5.opList03]
 388 type=OpDesc
 389 eventq_index=0
 390 opClass=SimdCmp
 391 opLat=1
 392 pipelined=true
 393
 394 [system.cpu.fuPool.FUList5.opList04]
 395 type=OpDesc
 396 eventq_index=0
 397 opClass=SimdCvt
 398 opLat=1
 399 pipelined=true
 400
 401 [system.cpu.fuPool.FUList5.opList05]
 402 type=OpDesc
 403 eventq_index=0
 404 opClass=SimdMisc
 405 opLat=1
 406 pipelined=true
 407
 408 [system.cpu.fuPool.FUList5.opList06]
 409 type=OpDesc
 410 eventq_index=0
 411 opClass=SimdMult
 412 opLat=1
 413 pipelined=true
 414
 415 [system.cpu.fuPool.FUList5.opList07]
 416 type=OpDesc
 417 eventq_index=0
 418 opClass=SimdMultAcc
 419 opLat=1
 420 pipelined=true
 421
 422 [system.cpu.fuPool.FUList5.opList08]
 423 type=OpDesc
 424 eventq_index=0
 425 opClass=SimdShift
 426 opLat=1
 427 pipelined=true
 428
 429 [system.cpu.fuPool.FUList5.opList09]
 430 type=OpDesc
 431 eventq_index=0
 432 opClass=SimdShiftAcc
 433 opLat=1
 434 pipelined=true
 435
 436 [system.cpu.fuPool.FUList5.opList10]
 437 type=OpDesc
 438 eventq_index=0
 439 opClass=SimdSqrt
 440 opLat=1
 441 pipelined=true
 442
 443 [system.cpu.fuPool.FUList5.opList11]
 444 type=OpDesc
 445 eventq_index=0
 446 opClass=SimdFloatAdd
 447 opLat=1
 448 pipelined=true
 449
 450 [system.cpu.fuPool.FUList5.opList12]
 451 type=OpDesc
 452 eventq_index=0
 453 opClass=SimdFloatAlu
 454 opLat=1
 455 pipelined=true
 456
 457 [system.cpu.fuPool.FUList5.opList13]
 458 type=OpDesc
 459 eventq_index=0
 460 opClass=SimdFloatCmp
 461 opLat=1
 462 pipelined=true
 463
 464 [system.cpu.fuPool.FUList5.opList14]
 465 type=OpDesc
 466 eventq_index=0
 467 opClass=SimdFloatCvt
 468 opLat=1
 469 pipelined=true
 470
 471 [system.cpu.fuPool.FUList5.opList15]
 472 type=OpDesc
 473 eventq_index=0
 474 opClass=SimdFloatDiv
 475 opLat=1
 476 pipelined=true
 477
 478 [system.cpu.fuPool.FUList5.opList16]
 479 type=OpDesc
 480 eventq_index=0
 481 opClass=SimdFloatMisc
 482 opLat=1
 483 pipelined=true
 484
 485 [system.cpu.fuPool.FUList5.opList17]
 486 type=OpDesc
 487 eventq_index=0
 488 opClass=SimdFloatMult
 489 opLat=1
 490 pipelined=true
 491
 492 [system.cpu.fuPool.FUList5.opList18]
 493 type=OpDesc
 494 eventq_index=0
 495 opClass=SimdFloatMultAcc
 496 opLat=1
 497 pipelined=true
 498
 499 [system.cpu.fuPool.FUList5.opList19]
 500 type=OpDesc
 501 eventq_index=0
 502 opClass=SimdFloatSqrt
 503 opLat=1
 504 pipelined=true
 505
 506 [system.cpu.fuPool.FUList6]
 507 type=FUDesc
 508 children=opList0 opList1
 509 count=0
 510 eventq_index=0
 511 opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 512
 513 [system.cpu.fuPool.FUList6.opList0]
 514 type=OpDesc
 515 eventq_index=0
 516 opClass=MemWrite
 517 opLat=1
 518 pipelined=true
 519
 520 [system.cpu.fuPool.FUList6.opList1]
 521 type=OpDesc
 522 eventq_index=0
 523 opClass=FloatMemWrite
 524 opLat=1
 525 pipelined=true
 526
 527 [system.cpu.fuPool.FUList7]
 528 type=FUDesc
 529 children=opList0 opList1 opList2 opList3
 530 count=4
 531 eventq_index=0
 532 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
 533
 534 [system.cpu.fuPool.FUList7.opList0]
 535 type=OpDesc
 536 eventq_index=0
 537 opClass=MemRead
 538 opLat=1
 539 pipelined=true
 540
 541 [system.cpu.fuPool.FUList7.opList1]
 542 type=OpDesc
 543 eventq_index=0
 544 opClass=MemWrite
 545 opLat=1
 546 pipelined=true
 547
 548 [system.cpu.fuPool.FUList7.opList2]
 549 type=OpDesc
 550 eventq_index=0
 551 opClass=FloatMemRead
 552 opLat=1
 553 pipelined=true
 554
 555 [system.cpu.fuPool.FUList7.opList3]
 556 type=OpDesc
 557 eventq_index=0
 558 opClass=FloatMemWrite
 559 opLat=1
 560 pipelined=true
 561
 562 [system.cpu.fuPool.FUList8]
 563 type=FUDesc
 564 children=opList
 565 count=1
 566 eventq_index=0
 567 opList=system.cpu.fuPool.FUList8.opList
 568
 569 [system.cpu.fuPool.FUList8.opList]
 570 type=OpDesc
 571 eventq_index=0
 572 opClass=IprAccess
 573 opLat=3
 574 pipelined=false
 575
 576 [system.cpu.icache]
 577 type=Cache
 578 children=tags
 579 addr_ranges=0:18446744073709551615:0:0:0:0
 580 assoc=2
 581 clk_domain=system.cpu_clk_domain
 582 clusivity=mostly_incl
 583 data_latency=2
 584 default_p_state=UNDEFINED
 585 demand_mshr_reserve=1
 586 eventq_index=0
 587 is_read_only=true
 588 max_miss_count=0
 589 mshrs=4
 590 p_state_clk_gate_bins=20
 591 p_state_clk_gate_max=1000000000000
 592 p_state_clk_gate_min=1000
 593 power_model=Null
 594 prefetch_on_access=false
 595 prefetcher=Null
 596 response_latency=2
 597 sequential_access=false
 598 size=131072
 599 system=system
 600 tag_latency=2
 601 tags=system.cpu.icache.tags
 602 tgts_per_mshr=20
 603 write_buffers=8
 604 writeback_clean=true
 605 cpu_side=system.cpu.icache_port
 606 mem_side=system.cpu.toL2Bus.slave[0]
 607
 608 [system.cpu.icache.tags]
 609 type=LRU
 610 assoc=2
 611 block_size=64
 612 clk_domain=system.cpu_clk_domain
 613 data_latency=2
 614 default_p_state=UNDEFINED
 615 eventq_index=0
 616 p_state_clk_gate_bins=20
 617 p_state_clk_gate_max=1000000000000
 618 p_state_clk_gate_min=1000
 619 power_model=Null
 620 sequential_access=false
 621 size=131072
 622 tag_latency=2
 623
 624 [system.cpu.interrupts0]
 625 type=AlphaInterrupts
 626 eventq_index=0
 627
 628 [system.cpu.interrupts1]
 629 type=AlphaInterrupts
 630 eventq_index=0
 631
 632 [system.cpu.isa0]
 633 type=AlphaISA
 634 eventq_index=0
 635 system=system
 636
 637 [system.cpu.isa1]
 638 type=AlphaISA
 639 eventq_index=0
 640 system=system
 641
 642 [system.cpu.itb]
 643 type=AlphaTLB
 644 eventq_index=0
 645 size=48
 646
 647 [system.cpu.l2cache]
 648 type=Cache
 649 children=tags
 650 addr_ranges=0:18446744073709551615:0:0:0:0
 651 assoc=8
 652 clk_domain=system.cpu_clk_domain
 653 clusivity=mostly_incl
 654 data_latency=20
 655 default_p_state=UNDEFINED
 656 demand_mshr_reserve=1
 657 eventq_index=0
 658 is_read_only=false
 659 max_miss_count=0
 660 mshrs=20
 661 p_state_clk_gate_bins=20
 662 p_state_clk_gate_max=1000000000000
 663 p_state_clk_gate_min=1000
 664 power_model=Null
 665 prefetch_on_access=false
 666 prefetcher=Null
 667 response_latency=20
 668 sequential_access=false
 669 size=2097152
 670 system=system
 671 tag_latency=20
 672 tags=system.cpu.l2cache.tags
 673 tgts_per_mshr=12
 674 write_buffers=8
 675 writeback_clean=false
 676 cpu_side=system.cpu.toL2Bus.master[0]
 677 mem_side=system.membus.slave[1]
 678
 679 [system.cpu.l2cache.tags]
 680 type=LRU
 681 assoc=8
 682 block_size=64
 683 clk_domain=system.cpu_clk_domain
 684 data_latency=20
 685 default_p_state=UNDEFINED
 686 eventq_index=0
 687 p_state_clk_gate_bins=20
 688 p_state_clk_gate_max=1000000000000
 689 p_state_clk_gate_min=1000
 690 power_model=Null
 691 sequential_access=false
 692 size=2097152
 693 tag_latency=20
 694
 695 [system.cpu.toL2Bus]
 696 type=CoherentXBar
 697 children=snoop_filter
 698 clk_domain=system.cpu_clk_domain
 699 default_p_state=UNDEFINED
 700 eventq_index=0
 701 forward_latency=0
 702 frontend_latency=1
 703 p_state_clk_gate_bins=20
 704 p_state_clk_gate_max=1000000000000
 705 p_state_clk_gate_min=1000
 706 point_of_coherency=false
 707 power_model=Null
 708 response_latency=1
 709 snoop_filter=system.cpu.toL2Bus.snoop_filter
 710 snoop_response_latency=1
 711 system=system
 712 use_default_range=false
 713 width=32
 714 master=system.cpu.l2cache.cpu_side
 715 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 716
 717 [system.cpu.toL2Bus.snoop_filter]
 718 type=SnoopFilter
 719 eventq_index=0
 720 lookup_latency=0
 721 max_capacity=8388608
 722 system=system
 723
 724 [system.cpu.tracer]
 725 type=ExeTracer
 726 eventq_index=0
 727
 728 [system.cpu.workload0]
 729 type=Process
 730 cmd=hello
 731 cwd=
 732 drivers=
 733 egid=100
 734 env=
 735 errout=cerr
 736 euid=100
 737 eventq_index=0
 738 executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 739 gid=100
 740 input=cin
 741 kvmInSE=false
 742 maxStackSize=67108864
 743 output=cout
 744 pgid=100
 745 pid=100
 746 ppid=0
 747 simpoint=0
 748 system=system
 749 uid=100
 750 useArchPT=false
 751
 752 [system.cpu.workload1]
 753 type=Process
 754 cmd=hello
 755 cwd=
 756 drivers=
 757 egid=100
 758 env=
 759 errout=cerr
 760 euid=100
 761 eventq_index=0
 762 executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 763 gid=100
 764 input=cin
 765 kvmInSE=false
 766 maxStackSize=67108864
 767 output=cout
 768 pgid=100
 769 pid=101
 770 ppid=100
 771 simpoint=0
 772 system=system
 773 uid=100
 774 useArchPT=false
 775
 776 [system.cpu_clk_domain]
 777 type=SrcClockDomain
 778 clock=500
 779 domain_id=-1
 780 eventq_index=0
 781 init_perf_level=0
 782 voltage_domain=system.voltage_domain
 783
 784 [system.dvfs_handler]
 785 type=DVFSHandler
 786 domains=
 787 enable=false
 788 eventq_index=0
 789 sys_clk_domain=system.clk_domain
 790 transition_latency=100000000
 791
 792 [system.membus]
 793 type=CoherentXBar
 794 children=snoop_filter
 795 clk_domain=system.clk_domain
 796 default_p_state=UNDEFINED
 797 eventq_index=0
 798 forward_latency=4
 799 frontend_latency=3
 800 p_state_clk_gate_bins=20
 801 p_state_clk_gate_max=1000000000000
 802 p_state_clk_gate_min=1000
 803 point_of_coherency=true
 804 power_model=Null
 805 response_latency=2
 806 snoop_filter=system.membus.snoop_filter
 807 snoop_response_latency=4
 808 system=system
 809 use_default_range=false
 810 width=16
 811 master=system.physmem.port
 812 slave=system.system_port system.cpu.l2cache.mem_side
 813
 814 [system.membus.snoop_filter]
 815 type=SnoopFilter
 816 eventq_index=0
 817 lookup_latency=1
 818 max_capacity=8388608
 819 system=system
 820
 821 [system.physmem]
 822 type=DRAMCtrl
 823 IDD0=0.055000
 824 IDD02=0.000000
 825 IDD2N=0.032000
 826 IDD2N2=0.000000
 827 IDD2P0=0.000000
 828 IDD2P02=0.000000
 829 IDD2P1=0.032000
 830 IDD2P12=0.000000
 831 IDD3N=0.038000
 832 IDD3N2=0.000000
 833 IDD3P0=0.000000
 834 IDD3P02=0.000000
 835 IDD3P1=0.038000
 836 IDD3P12=0.000000
 837 IDD4R=0.157000
 838 IDD4R2=0.000000
 839 IDD4W=0.125000
 840 IDD4W2=0.000000
 841 IDD5=0.235000
 842 IDD52=0.000000
 843 IDD6=0.020000
 844 IDD62=0.000000
 845 VDD=1.500000
 846 VDD2=0.000000
 847 activation_limit=4
 848 addr_mapping=RoRaBaCoCh
 849 bank_groups_per_rank=0
 850 banks_per_rank=8
 851 burst_length=8
 852 channels=1
 853 clk_domain=system.clk_domain
 854 conf_table_reported=true
 855 default_p_state=UNDEFINED
 856 device_bus_width=8
 857 device_rowbuffer_size=1024
 858 device_size=536870912
 859 devices_per_rank=8
 860 dll=true
 861 eventq_index=0
 862 in_addr_map=true
 863 kvm_map=true
 864 max_accesses_per_row=16
 865 mem_sched_policy=frfcfs
 866 min_writes_per_switch=16
 867 null=false
 868 p_state_clk_gate_bins=20
 869 p_state_clk_gate_max=1000000000000
 870 p_state_clk_gate_min=1000
 871 page_policy=open_adaptive
 872 power_model=Null
 873 range=0:134217727:0:0:0:0
 874 ranks_per_channel=2
 875 read_buffer_size=32
 876 static_backend_latency=10000
 877 static_frontend_latency=10000
 878 tBURST=5000
 879 tCCD_L=0
 880 tCK=1250
 881 tCL=13750
 882 tCS=2500
 883 tRAS=35000
 884 tRCD=13750
 885 tREFI=7800000
 886 tRFC=260000
 887 tRP=13750
 888 tRRD=6000
 889 tRRD_L=0
 890 tRTP=7500
 891 tRTW=2500
 892 tWR=15000
 893 tWTR=7500
 894 tXAW=30000
 895 tXP=6000
 896 tXPDLL=0
 897 tXS=270000
 898 tXSDLL=0
 899 write_buffer_size=64
 900 write_high_thresh_perc=85
 901 write_low_thresh_perc=50
 902 port=system.membus.master[0]
 903
 904 [system.voltage_domain]
 905 type=VoltageDomain
 906 eventq_index=0
 907 voltage=1.000000
 908