2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000167 # Number of seconds simulated
4 sim_ticks 167318000 # Number of ticks simulated
5 final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 259842 # Simulator instruction rate (inst/s)
8 host_op_rate 259907 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 381385356 # Simulator tick rate (ticks/s)
10 host_mem_usage 261864 # Number of bytes of host memory used
11 host_seconds 0.44 # Real time elapsed on the host
12 sim_insts 113991 # Number of instructions simulated
13 sim_ops 114022 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 69760 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.readReqs 1090 # Number of read requests accepted
34 system.physmem.writeReqs 0 # Number of write requests accepted
35 system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue
36 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37 system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM
38 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40 system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side
41 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45 system.physmem.perBankRdBursts::0 110 # Per bank write bursts
46 system.physmem.perBankRdBursts::1 4 # Per bank write bursts
47 system.physmem.perBankRdBursts::2 9 # Per bank write bursts
48 system.physmem.perBankRdBursts::3 124 # Per bank write bursts
49 system.physmem.perBankRdBursts::4 62 # Per bank write bursts
50 system.physmem.perBankRdBursts::5 92 # Per bank write bursts
51 system.physmem.perBankRdBursts::6 88 # Per bank write bursts
52 system.physmem.perBankRdBursts::7 18 # Per bank write bursts
53 system.physmem.perBankRdBursts::8 55 # Per bank write bursts
54 system.physmem.perBankRdBursts::9 86 # Per bank write bursts
55 system.physmem.perBankRdBursts::10 90 # Per bank write bursts
56 system.physmem.perBankRdBursts::11 38 # Per bank write bursts
57 system.physmem.perBankRdBursts::12 113 # Per bank write bursts
58 system.physmem.perBankRdBursts::13 94 # Per bank write bursts
59 system.physmem.perBankRdBursts::14 101 # Per bank write bursts
60 system.physmem.perBankRdBursts::15 6 # Per bank write bursts
61 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79 system.physmem.totGap 166987000 # Total gap between requests
80 system.physmem.readPktSize::0 0 # Read request sizes (log2)
81 system.physmem.readPktSize::1 0 # Read request sizes (log2)
82 system.physmem.readPktSize::2 0 # Read request sizes (log2)
83 system.physmem.readPktSize::3 0 # Read request sizes (log2)
84 system.physmem.readPktSize::4 0 # Read request sizes (log2)
85 system.physmem.readPktSize::5 0 # Read request sizes (log2)
86 system.physmem.readPktSize::6 1090 # Read request sizes (log2)
87 system.physmem.writePktSize::0 0 # Write request sizes (log2)
88 system.physmem.writePktSize::1 0 # Write request sizes (log2)
89 system.physmem.writePktSize::2 0 # Write request sizes (log2)
90 system.physmem.writePktSize::3 0 # Write request sizes (log2)
91 system.physmem.writePktSize::4 0 # Write request sizes (log2)
92 system.physmem.writePktSize::5 0 # Write request sizes (log2)
93 system.physmem.writePktSize::6 0 # Write request sizes (log2)
94 system.physmem.rdQLenPdf::0 1032 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::1 53 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190 system.physmem.bytesPerActivate::samples 207 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::mean 327.729469 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::gmean 215.587083 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::stdev 297.390992 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::0-127 56 27.05% 27.05% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::128-255 46 22.22% 49.28% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation
204 system.physmem.totQLat 15449500 # Total ticks spent queuing
205 system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM
206 system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers
207 system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst
208 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209 system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst
210 system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s
211 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212 system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s
213 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215 system.physmem.busUtil 3.26 # Data bus utilization in percentage
216 system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads
217 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218 system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
219 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220 system.physmem.readRowHits 874 # Number of row buffer hits during reads
221 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222 system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads
223 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224 system.physmem.avgGap 153199.08 # Average gap between requests
225 system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
226 system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ)
227 system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ)
228 system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ)
229 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230 system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
231 system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ)
232 system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ)
233 system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ)
234 system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ)
235 system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ)
236 system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ)
237 system.physmem_0.averagePower 555.517657 # Core power per rank (mW)
238 system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank
239 system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states
240 system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
241 system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states
242 system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states
243 system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states
244 system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states
245 system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ)
246 system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ)
247 system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ)
248 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249 system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
250 system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ)
251 system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ)
252 system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ)
253 system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ)
254 system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ)
255 system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ)
256 system.physmem_1.averagePower 539.101715 # Core power per rank (mW)
257 system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank
258 system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states
259 system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
260 system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states
261 system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states
262 system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states
263 system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states
264 system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
265 system.cpu.branchPred.lookups 31578 # Number of BP lookups
266 system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted
267 system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect
268 system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups
269 system.cpu.branchPred.BTBHits 15512 # Number of BTB hits
270 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271 system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage
272 system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
273 system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
274 system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups.
275 system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits.
276 system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses.
277 system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches.
278 system.cpu_clk_domain.clock 500 # Clock period in ticks
279 system.cpu.dtb.read_hits 0 # DTB read hits
280 system.cpu.dtb.read_misses 0 # DTB read misses
281 system.cpu.dtb.read_accesses 0 # DTB read accesses
282 system.cpu.dtb.write_hits 0 # DTB write hits
283 system.cpu.dtb.write_misses 0 # DTB write misses
284 system.cpu.dtb.write_accesses 0 # DTB write accesses
285 system.cpu.dtb.hits 0 # DTB hits
286 system.cpu.dtb.misses 0 # DTB misses
287 system.cpu.dtb.accesses 0 # DTB accesses
288 system.cpu.itb.read_hits 0 # DTB read hits
289 system.cpu.itb.read_misses 0 # DTB read misses
290 system.cpu.itb.read_accesses 0 # DTB read accesses
291 system.cpu.itb.write_hits 0 # DTB write hits
292 system.cpu.itb.write_misses 0 # DTB write misses
293 system.cpu.itb.write_accesses 0 # DTB write accesses
294 system.cpu.itb.hits 0 # DTB hits
295 system.cpu.itb.misses 0 # DTB misses
296 system.cpu.itb.accesses 0 # DTB accesses
297 system.cpu.workload.numSyscalls 43 # Number of system calls
298 system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states
299 system.cpu.numCycles 334636 # number of cpu cycles simulated
300 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
301 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
302 system.cpu.committedInsts 113991 # Number of instructions committed
303 system.cpu.committedOps 114022 # Number of ops (including micro ops) committed
304 system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit
305 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
306 system.cpu.cpi 2.935635 # CPI: cycles per instruction
307 system.cpu.ipc 0.340642 # IPC: instructions per cycle
308 system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction
309 system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction
310 system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction
311 system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction
312 system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction
313 system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction
314 system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction
315 system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction
316 system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.68% # Class of committed instruction
317 system.cpu.op_class_0::FloatDiv 0 0.00% 61.68% # Class of committed instruction
318 system.cpu.op_class_0::FloatMisc 0 0.00% 61.68% # Class of committed instruction
319 system.cpu.op_class_0::FloatSqrt 0 0.00% 61.68% # Class of committed instruction
320 system.cpu.op_class_0::SimdAdd 0 0.00% 61.68% # Class of committed instruction
321 system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.68% # Class of committed instruction
322 system.cpu.op_class_0::SimdAlu 0 0.00% 61.68% # Class of committed instruction
323 system.cpu.op_class_0::SimdCmp 0 0.00% 61.68% # Class of committed instruction
324 system.cpu.op_class_0::SimdCvt 0 0.00% 61.68% # Class of committed instruction
325 system.cpu.op_class_0::SimdMisc 0 0.00% 61.68% # Class of committed instruction
326 system.cpu.op_class_0::SimdMult 0 0.00% 61.68% # Class of committed instruction
327 system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.68% # Class of committed instruction
328 system.cpu.op_class_0::SimdShift 0 0.00% 61.68% # Class of committed instruction
329 system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.68% # Class of committed instruction
330 system.cpu.op_class_0::SimdSqrt 0 0.00% 61.68% # Class of committed instruction
331 system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.68% # Class of committed instruction
332 system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.68% # Class of committed instruction
333 system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.68% # Class of committed instruction
334 system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.68% # Class of committed instruction
335 system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.68% # Class of committed instruction
336 system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.68% # Class of committed instruction
337 system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.68% # Class of committed instruction
338 system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.68% # Class of committed instruction
339 system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction
340 system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction
341 system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction
342 system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
343 system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
344 system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
345 system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
346 system.cpu.op_class_0::total 114022 # Class of committed instruction
347 system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked
348 system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped
349 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
350 system.cpu.dcache.tags.replacements 0 # number of replacements
351 system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use
352 system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks.
353 system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks.
354 system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks.
355 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
356 system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor
357 system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy
358 system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy
359 system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id
360 system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
361 system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
362 system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id
363 system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id
364 system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses
365 system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses
366 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
367 system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits
368 system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits
369 system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits
370 system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits
371 system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits
372 system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits
373 system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits
374 system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits
375 system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits
376 system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits
377 system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits
378 system.cpu.dcache.overall_hits::total 44057 # number of overall hits
379 system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses
380 system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses
381 system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
382 system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses
383 system.cpu.dcache.demand_misses::cpu.data 459 # number of demand (read+write) misses
384 system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses
385 system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses
386 system.cpu.dcache.overall_misses::total 459 # number of overall misses
387 system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles
388 system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles
389 system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles
390 system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles
391 system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles
392 system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles
393 system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles
394 system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles
395 system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses)
396 system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses)
397 system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses)
398 system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses)
399 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses)
400 system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses)
401 system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses)
402 system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses)
403 system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses
404 system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses
405 system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses
406 system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses
407 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses
408 system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses
409 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses
410 system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses
411 system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses
412 system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses
413 system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses
414 system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses
415 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency
416 system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency
417 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency
418 system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency
419 system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
420 system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency
421 system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
422 system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency
423 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
424 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
425 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
426 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
427 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
428 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
429 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
430 system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
431 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 185 # number of WriteReq MSHR hits
432 system.cpu.dcache.WriteReq_mshr_hits::total 185 # number of WriteReq MSHR hits
433 system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits
434 system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits
435 system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits
436 system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits
437 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses
438 system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
439 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses
440 system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses
441 system.cpu.dcache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses
442 system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
443 system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses
444 system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
445 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles
446 system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles
447 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles
448 system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles
449 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles
450 system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles
451 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles
452 system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles
453 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses
454 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses
455 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses
456 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009995 # mshr miss rate for WriteReq accesses
457 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for demand accesses
458 system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses
459 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses
460 system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses
461 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency
462 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency
463 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency
464 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency
465 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
466 system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
467 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
468 system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
469 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
470 system.cpu.icache.tags.replacements 18 # number of replacements
471 system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use
472 system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks.
473 system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks.
474 system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks.
475 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
476 system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor
477 system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy
478 system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy
479 system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id
480 system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
481 system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id
482 system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id
483 system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id
484 system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses
485 system.cpu.icache.tags.data_accesses 101789 # Number of data accesses
486 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
487 system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits
488 system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits
489 system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits
490 system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits
491 system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits
492 system.cpu.icache.overall_hits::total 49660 # number of overall hits
493 system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses
494 system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses
495 system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses
496 system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses
497 system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses
498 system.cpu.icache.overall_misses::total 823 # number of overall misses
499 system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles
500 system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles
501 system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles
502 system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles
503 system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles
504 system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles
505 system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses)
506 system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses)
507 system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses
508 system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses
509 system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses
510 system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses
511 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses
512 system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses
513 system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses
514 system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses
515 system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses
516 system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses
517 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency
518 system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency
519 system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
520 system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency
521 system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
522 system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency
523 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
524 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
525 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
526 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
527 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
528 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
529 system.cpu.icache.writebacks::writebacks 18 # number of writebacks
530 system.cpu.icache.writebacks::total 18 # number of writebacks
531 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses
532 system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses
533 system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses
534 system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses
535 system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses
536 system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses
537 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
538 system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles
539 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
540 system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles
541 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
542 system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles
543 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses
544 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses
545 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses
546 system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses
547 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses
548 system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses
549 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency
550 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency
551 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
552 system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
553 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
554 system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
555 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
556 system.cpu.l2cache.tags.replacements 0 # number of replacements
557 system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use
558 system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks.
559 system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks.
560 system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks.
561 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
562 system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor
563 system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor
564 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy
565 system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy
566 system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy
567 system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id
568 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
569 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id
570 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id
571 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id
572 system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses
573 system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses
574 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
575 system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits
576 system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits
577 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
578 system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
579 system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
580 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
581 system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
582 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
583 system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses
584 system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses
585 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 823 # number of ReadCleanReq misses
586 system.cpu.l2cache.ReadCleanReq_misses::total 823 # number of ReadCleanReq misses
587 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 68 # number of ReadSharedReq misses
588 system.cpu.l2cache.ReadSharedReq_misses::total 68 # number of ReadSharedReq misses
589 system.cpu.l2cache.demand_misses::cpu.inst 823 # number of demand (read+write) misses
590 system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses
591 system.cpu.l2cache.demand_misses::total 1090 # number of demand (read+write) misses
592 system.cpu.l2cache.overall_misses::cpu.inst 823 # number of overall misses
593 system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses
594 system.cpu.l2cache.overall_misses::total 1090 # number of overall misses
595 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles
596 system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles
597 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles
598 system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles
599 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles
600 system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles
601 system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles
602 system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles
603 system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles
604 system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles
605 system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles
606 system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles
607 system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses)
608 system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses)
609 system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses)
610 system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses)
611 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses)
612 system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses)
613 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 69 # number of ReadSharedReq accesses(hits+misses)
614 system.cpu.l2cache.ReadSharedReq_accesses::total 69 # number of ReadSharedReq accesses(hits+misses)
615 system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses
616 system.cpu.l2cache.demand_accesses::cpu.data 268 # number of demand (read+write) accesses
617 system.cpu.l2cache.demand_accesses::total 1091 # number of demand (read+write) accesses
618 system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses
619 system.cpu.l2cache.overall_accesses::cpu.data 268 # number of overall (read+write) accesses
620 system.cpu.l2cache.overall_accesses::total 1091 # number of overall (read+write) accesses
621 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
622 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
623 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
624 system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
625 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.985507 # miss rate for ReadSharedReq accesses
626 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.985507 # miss rate for ReadSharedReq accesses
627 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
628 system.cpu.l2cache.demand_miss_rate::cpu.data 0.996269 # miss rate for demand accesses
629 system.cpu.l2cache.demand_miss_rate::total 0.999083 # miss rate for demand accesses
630 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
631 system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 # miss rate for overall accesses
632 system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses
633 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency
634 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency
635 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency
636 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency
637 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency
638 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency
639 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
640 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
641 system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency
642 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
643 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
644 system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency
645 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
646 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
647 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
648 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
649 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
650 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
651 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses
652 system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses
653 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 823 # number of ReadCleanReq MSHR misses
654 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 823 # number of ReadCleanReq MSHR misses
655 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 68 # number of ReadSharedReq MSHR misses
656 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 68 # number of ReadSharedReq MSHR misses
657 system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses
658 system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses
659 system.cpu.l2cache.demand_mshr_misses::total 1090 # number of demand (read+write) MSHR misses
660 system.cpu.l2cache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses
661 system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses
662 system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses
663 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles
664 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles
665 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles
666 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles
667 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles
668 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles
669 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles
670 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles
671 system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles
672 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles
673 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles
674 system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles
675 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
676 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
677 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
678 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
679 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for ReadSharedReq accesses
680 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.985507 # mshr miss rate for ReadSharedReq accesses
681 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
682 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for demand accesses
683 system.cpu.l2cache.demand_mshr_miss_rate::total 0.999083 # mshr miss rate for demand accesses
684 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
685 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for overall accesses
686 system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses
687 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency
688 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency
689 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency
690 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency
691 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency
692 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency
693 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
694 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
695 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
696 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
697 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
698 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
699 system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter.
700 system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data.
701 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
702 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
703 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
704 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
705 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
706 system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution
707 system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution
708 system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution
709 system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution
710 system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution
711 system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution
712 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes)
713 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes)
714 system.cpu.toL2Bus.pkt_count::total 2200 # Packet count per connected master and slave (bytes)
715 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53824 # Cumulative packet size per connected master and slave (bytes)
716 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17152 # Cumulative packet size per connected master and slave (bytes)
717 system.cpu.toL2Bus.pkt_size::total 70976 # Cumulative packet size per connected master and slave (bytes)
718 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
719 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
720 system.cpu.toL2Bus.snoop_fanout::samples 1091 # Request fanout histogram
721 system.cpu.toL2Bus.snoop_fanout::mean 0.000917 # Request fanout histogram
722 system.cpu.toL2Bus.snoop_fanout::stdev 0.030275 # Request fanout histogram
723 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
724 system.cpu.toL2Bus.snoop_fanout::0 1090 99.91% 99.91% # Request fanout histogram
725 system.cpu.toL2Bus.snoop_fanout::1 1 0.09% 100.00% # Request fanout histogram
726 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
727 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
728 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
729 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
730 system.cpu.toL2Bus.snoop_fanout::total 1091 # Request fanout histogram
731 system.cpu.toL2Bus.reqLayer0.occupancy 572500 # Layer occupancy (ticks)
732 system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
733 system.cpu.toL2Bus.respLayer0.occupancy 1234500 # Layer occupancy (ticks)
734 system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
735 system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks)
736 system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
737 system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter.
738 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
739 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
740 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
741 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
742 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
743 system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
744 system.membus.trans_dist::ReadResp 891 # Transaction distribution
745 system.membus.trans_dist::ReadExReq 199 # Transaction distribution
746 system.membus.trans_dist::ReadExResp 199 # Transaction distribution
747 system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution
748 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes)
749 system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes)
750 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes)
751 system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes)
752 system.membus.snoops 0 # Total snoops (count)
753 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
754 system.membus.snoop_fanout::samples 1090 # Request fanout histogram
755 system.membus.snoop_fanout::mean 0 # Request fanout histogram
756 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
757 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
758 system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram
759 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
760 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
761 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
762 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
763 system.membus.snoop_fanout::total 1090 # Request fanout histogram
764 system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks)
765 system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
766 system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks)
767 system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
769 ---------- End Simulation Statistics ----------
projects / gem5.git / blob