sim: print --debug-flag Event execution and instance ID
[gem5.git] / tests / quick / se / 02.insttest / ref / riscv / linux-rv64c / o3-timing / simout
1 Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simout
2 Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simerr
3 gem5 Simulator System. http://gem5.org
4 gem5 is copyrighted software; use the --copyright option for details.
5
6 gem5 compiled Jul 13 2017 17:09:45
7 gem5 started Jul 13 2017 17:25:07
8 gem5 executing on boldrock, pid 6007
9 command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/o3-timing
10
11 Global frequency set at 1000000000000 ticks per second
12 c.lwsp: PASS
13 c.ldsp: PASS
14 c.fldsp: PASS
15 c.swsp: PASS
16 c.sdsp: PASS
17 c.fsdsp: PASS
18 c.lw, positive: PASS
19 c.lw, negative: PASS
20 c.ld: PASS
21 c.fld: PASS
22 c.sw: PASS
23 c.sd: PASS
24 c.fsd: PASS
25 c.j: PASS
26 c.jr: PASS
27 c.jalr: PASS
28 c.beqz, zero: PASS
29 c.beqz, not zero: PASS
30 c.bnez, not zero: PASS
31 c.bnez, zero: PASS
32 c.li: PASS
33 c.li, sign extend: PASS
34 c.lui: PASS
35 c.addi: PASS
36 c.addiw: PASS
37 c.addiw, overflow: PASS
38 c.addiw, truncate: PASS
39 c.addi16sp: PASS
40 c.addi4spn: PASS
41 c.slli: PASS
42 c.slli, overflow: PASS
43 c.srli: PASS
44 c.srli, overflow: PASS
45 c.srli, -1: PASS
46 c.srai: PASS
47 c.srai, overflow: PASS
48 c.srai, -1: PASS
49 c.andi (0): PASS
50 c.andi (1): PASS
51 c.mv: PASS
52 c.add: PASS
53 c.and (0): PASS
54 c.and (-1): PASS
55 c.or (1): PASS
56 c.or (A): PASS
57 c.xor (1): PASS
58 c.xor (0): PASS
59 c.sub: PASS
60 c.addw: PASS
61 c.addw, overflow: PASS
62 c.addw, truncate: PASS
63 c.subw: PASS
64 c.subw, "overflow": PASS
65 c.subw, truncate: PASS
66 Exiting @ tick 141034000 because exiting with last active thread context