tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=DerivO3CPU
  48 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  49 LFSTSize=1024
  50 LQEntries=32
  51 LSQCheckLoads=true
  52 LSQDepCheckShift=4
  53 SQEntries=32
  54 SSITSize=1024
  55 activity=0
  56 backComSize=5
  57 branchPred=system.cpu.branchPred
  58 cachePorts=200
  59 checker=Null
  60 clk_domain=system.cpu_clk_domain
  61 commitToDecodeDelay=1
  62 commitToFetchDelay=1
  63 commitToIEWDelay=1
  64 commitToRenameDelay=1
  65 commitWidth=8
  66 cpu_id=0
  67 decodeToFetchDelay=1
  68 decodeToRenameDelay=1
  69 decodeWidth=8
  70 dispatchWidth=8
  71 do_checkpoint_insts=true
  72 do_quiesce=true
  73 do_statistics_insts=true
  74 dtb=system.cpu.dtb
  75 eventq_index=0
  76 fetchBufferSize=64
  77 fetchQueueSize=32
  78 fetchToDecodeDelay=1
  79 fetchTrapLatency=1
  80 fetchWidth=8
  81 forwardComSize=5
  82 fuPool=system.cpu.fuPool
  83 function_trace=false
  84 function_trace_start=0
  85 iewToCommitDelay=1
  86 iewToDecodeDelay=1
  87 iewToFetchDelay=1
  88 iewToRenameDelay=1
  89 interrupts=system.cpu.interrupts
  90 isa=system.cpu.isa
  91 issueToExecuteDelay=1
  92 issueWidth=8
  93 itb=system.cpu.itb
  94 max_insts_all_threads=0
  95 max_insts_any_thread=0
  96 max_loads_all_threads=0
  97 max_loads_any_thread=0
  98 needsTSO=false
  99 numIQEntries=64
 100 numPhysCCRegs=0
 101 numPhysFloatRegs=256
 102 numPhysIntRegs=256
 103 numROBEntries=192
 104 numRobs=1
 105 numThreads=1
 106 profile=0
 107 progress_interval=0
 108 renameToDecodeDelay=1
 109 renameToFetchDelay=1
 110 renameToIEWDelay=2
 111 renameToROBDelay=1
 112 renameWidth=8
 113 simpoint_start_insts=
 114 smtCommitPolicy=RoundRobin
 115 smtFetchPolicy=SingleThread
 116 smtIQPolicy=Partitioned
 117 smtIQThreshold=100
 118 smtLSQPolicy=Partitioned
 119 smtLSQThreshold=100
 120 smtNumFetchingThreads=1
 121 smtROBPolicy=Partitioned
 122 smtROBThreshold=100
 123 socket_id=0
 124 squashWidth=8
 125 store_set_clear_period=250000
 126 switched_out=false
 127 system=system
 128 tracer=system.cpu.tracer
 129 trapLatency=13
 130 wbWidth=8
 131 workload=system.cpu.workload
 132 dcache_port=system.cpu.dcache.cpu_side
 133 icache_port=system.cpu.icache.cpu_side
 134
 135 [system.cpu.branchPred]
 136 type=BranchPredictor
 137 BTBEntries=4096
 138 BTBTagSize=16
 139 RASSize=16
 140 choiceCtrBits=2
 141 choicePredictorSize=8192
 142 eventq_index=0
 143 globalCtrBits=2
 144 globalPredictorSize=8192
 145 instShiftAmt=2
 146 localCtrBits=2
 147 localHistoryTableSize=2048
 148 localPredictorSize=2048
 149 numThreads=1
 150 predType=tournament
 151
 152 [system.cpu.dcache]
 153 type=BaseCache
 154 children=tags
 155 addr_ranges=0:18446744073709551615
 156 assoc=2
 157 clk_domain=system.cpu_clk_domain
 158 eventq_index=0
 159 forward_snoops=true
 160 hit_latency=2
 161 is_top_level=true
 162 max_miss_count=0
 163 mshrs=4
 164 prefetch_on_access=false
 165 prefetcher=Null
 166 response_latency=2
 167 sequential_access=false
 168 size=262144
 169 system=system
 170 tags=system.cpu.dcache.tags
 171 tgts_per_mshr=20
 172 two_queue=false
 173 write_buffers=8
 174 cpu_side=system.cpu.dcache_port
 175 mem_side=system.cpu.toL2Bus.slave[1]
 176
 177 [system.cpu.dcache.tags]
 178 type=LRU
 179 assoc=2
 180 block_size=64
 181 clk_domain=system.cpu_clk_domain
 182 eventq_index=0
 183 hit_latency=2
 184 sequential_access=false
 185 size=262144
 186
 187 [system.cpu.dtb]
 188 type=SparcTLB
 189 eventq_index=0
 190 size=64
 191
 192 [system.cpu.fuPool]
 193 type=FUPool
 194 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 195 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 196 eventq_index=0
 197
 198 [system.cpu.fuPool.FUList0]
 199 type=FUDesc
 200 children=opList
 201 count=6
 202 eventq_index=0
 203 opList=system.cpu.fuPool.FUList0.opList
 204
 205 [system.cpu.fuPool.FUList0.opList]
 206 type=OpDesc
 207 eventq_index=0
 208 issueLat=1
 209 opClass=IntAlu
 210 opLat=1
 211
 212 [system.cpu.fuPool.FUList1]
 213 type=FUDesc
 214 children=opList0 opList1
 215 count=2
 216 eventq_index=0
 217 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 218
 219 [system.cpu.fuPool.FUList1.opList0]
 220 type=OpDesc
 221 eventq_index=0
 222 issueLat=1
 223 opClass=IntMult
 224 opLat=3
 225
 226 [system.cpu.fuPool.FUList1.opList1]
 227 type=OpDesc
 228 eventq_index=0
 229 issueLat=19
 230 opClass=IntDiv
 231 opLat=20
 232
 233 [system.cpu.fuPool.FUList2]
 234 type=FUDesc
 235 children=opList0 opList1 opList2
 236 count=4
 237 eventq_index=0
 238 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 239
 240 [system.cpu.fuPool.FUList2.opList0]
 241 type=OpDesc
 242 eventq_index=0
 243 issueLat=1
 244 opClass=FloatAdd
 245 opLat=2
 246
 247 [system.cpu.fuPool.FUList2.opList1]
 248 type=OpDesc
 249 eventq_index=0
 250 issueLat=1
 251 opClass=FloatCmp
 252 opLat=2
 253
 254 [system.cpu.fuPool.FUList2.opList2]
 255 type=OpDesc
 256 eventq_index=0
 257 issueLat=1
 258 opClass=FloatCvt
 259 opLat=2
 260
 261 [system.cpu.fuPool.FUList3]
 262 type=FUDesc
 263 children=opList0 opList1 opList2
 264 count=2
 265 eventq_index=0
 266 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 267
 268 [system.cpu.fuPool.FUList3.opList0]
 269 type=OpDesc
 270 eventq_index=0
 271 issueLat=1
 272 opClass=FloatMult
 273 opLat=4
 274
 275 [system.cpu.fuPool.FUList3.opList1]
 276 type=OpDesc
 277 eventq_index=0
 278 issueLat=12
 279 opClass=FloatDiv
 280 opLat=12
 281
 282 [system.cpu.fuPool.FUList3.opList2]
 283 type=OpDesc
 284 eventq_index=0
 285 issueLat=24
 286 opClass=FloatSqrt
 287 opLat=24
 288
 289 [system.cpu.fuPool.FUList4]
 290 type=FUDesc
 291 children=opList
 292 count=0
 293 eventq_index=0
 294 opList=system.cpu.fuPool.FUList4.opList
 295
 296 [system.cpu.fuPool.FUList4.opList]
 297 type=OpDesc
 298 eventq_index=0
 299 issueLat=1
 300 opClass=MemRead
 301 opLat=1
 302
 303 [system.cpu.fuPool.FUList5]
 304 type=FUDesc
 305 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 306 count=4
 307 eventq_index=0
 308 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 309
 310 [system.cpu.fuPool.FUList5.opList00]
 311 type=OpDesc
 312 eventq_index=0
 313 issueLat=1
 314 opClass=SimdAdd
 315 opLat=1
 316
 317 [system.cpu.fuPool.FUList5.opList01]
 318 type=OpDesc
 319 eventq_index=0
 320 issueLat=1
 321 opClass=SimdAddAcc
 322 opLat=1
 323
 324 [system.cpu.fuPool.FUList5.opList02]
 325 type=OpDesc
 326 eventq_index=0
 327 issueLat=1
 328 opClass=SimdAlu
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList03]
 332 type=OpDesc
 333 eventq_index=0
 334 issueLat=1
 335 opClass=SimdCmp
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList04]
 339 type=OpDesc
 340 eventq_index=0
 341 issueLat=1
 342 opClass=SimdCvt
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList05]
 346 type=OpDesc
 347 eventq_index=0
 348 issueLat=1
 349 opClass=SimdMisc
 350 opLat=1
 351
 352 [system.cpu.fuPool.FUList5.opList06]
 353 type=OpDesc
 354 eventq_index=0
 355 issueLat=1
 356 opClass=SimdMult
 357 opLat=1
 358
 359 [system.cpu.fuPool.FUList5.opList07]
 360 type=OpDesc
 361 eventq_index=0
 362 issueLat=1
 363 opClass=SimdMultAcc
 364 opLat=1
 365
 366 [system.cpu.fuPool.FUList5.opList08]
 367 type=OpDesc
 368 eventq_index=0
 369 issueLat=1
 370 opClass=SimdShift
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList09]
 374 type=OpDesc
 375 eventq_index=0
 376 issueLat=1
 377 opClass=SimdShiftAcc
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList10]
 381 type=OpDesc
 382 eventq_index=0
 383 issueLat=1
 384 opClass=SimdSqrt
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList5.opList11]
 388 type=OpDesc
 389 eventq_index=0
 390 issueLat=1
 391 opClass=SimdFloatAdd
 392 opLat=1
 393
 394 [system.cpu.fuPool.FUList5.opList12]
 395 type=OpDesc
 396 eventq_index=0
 397 issueLat=1
 398 opClass=SimdFloatAlu
 399 opLat=1
 400
 401 [system.cpu.fuPool.FUList5.opList13]
 402 type=OpDesc
 403 eventq_index=0
 404 issueLat=1
 405 opClass=SimdFloatCmp
 406 opLat=1
 407
 408 [system.cpu.fuPool.FUList5.opList14]
 409 type=OpDesc
 410 eventq_index=0
 411 issueLat=1
 412 opClass=SimdFloatCvt
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList5.opList15]
 416 type=OpDesc
 417 eventq_index=0
 418 issueLat=1
 419 opClass=SimdFloatDiv
 420 opLat=1
 421
 422 [system.cpu.fuPool.FUList5.opList16]
 423 type=OpDesc
 424 eventq_index=0
 425 issueLat=1
 426 opClass=SimdFloatMisc
 427 opLat=1
 428
 429 [system.cpu.fuPool.FUList5.opList17]
 430 type=OpDesc
 431 eventq_index=0
 432 issueLat=1
 433 opClass=SimdFloatMult
 434 opLat=1
 435
 436 [system.cpu.fuPool.FUList5.opList18]
 437 type=OpDesc
 438 eventq_index=0
 439 issueLat=1
 440 opClass=SimdFloatMultAcc
 441 opLat=1
 442
 443 [system.cpu.fuPool.FUList5.opList19]
 444 type=OpDesc
 445 eventq_index=0
 446 issueLat=1
 447 opClass=SimdFloatSqrt
 448 opLat=1
 449
 450 [system.cpu.fuPool.FUList6]
 451 type=FUDesc
 452 children=opList
 453 count=0
 454 eventq_index=0
 455 opList=system.cpu.fuPool.FUList6.opList
 456
 457 [system.cpu.fuPool.FUList6.opList]
 458 type=OpDesc
 459 eventq_index=0
 460 issueLat=1
 461 opClass=MemWrite
 462 opLat=1
 463
 464 [system.cpu.fuPool.FUList7]
 465 type=FUDesc
 466 children=opList0 opList1
 467 count=4
 468 eventq_index=0
 469 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 470
 471 [system.cpu.fuPool.FUList7.opList0]
 472 type=OpDesc
 473 eventq_index=0
 474 issueLat=1
 475 opClass=MemRead
 476 opLat=1
 477
 478 [system.cpu.fuPool.FUList7.opList1]
 479 type=OpDesc
 480 eventq_index=0
 481 issueLat=1
 482 opClass=MemWrite
 483 opLat=1
 484
 485 [system.cpu.fuPool.FUList8]
 486 type=FUDesc
 487 children=opList
 488 count=1
 489 eventq_index=0
 490 opList=system.cpu.fuPool.FUList8.opList
 491
 492 [system.cpu.fuPool.FUList8.opList]
 493 type=OpDesc
 494 eventq_index=0
 495 issueLat=3
 496 opClass=IprAccess
 497 opLat=3
 498
 499 [system.cpu.icache]
 500 type=BaseCache
 501 children=tags
 502 addr_ranges=0:18446744073709551615
 503 assoc=2
 504 clk_domain=system.cpu_clk_domain
 505 eventq_index=0
 506 forward_snoops=true
 507 hit_latency=2
 508 is_top_level=true
 509 max_miss_count=0
 510 mshrs=4
 511 prefetch_on_access=false
 512 prefetcher=Null
 513 response_latency=2
 514 sequential_access=false
 515 size=131072
 516 system=system
 517 tags=system.cpu.icache.tags
 518 tgts_per_mshr=20
 519 two_queue=false
 520 write_buffers=8
 521 cpu_side=system.cpu.icache_port
 522 mem_side=system.cpu.toL2Bus.slave[0]
 523
 524 [system.cpu.icache.tags]
 525 type=LRU
 526 assoc=2
 527 block_size=64
 528 clk_domain=system.cpu_clk_domain
 529 eventq_index=0
 530 hit_latency=2
 531 sequential_access=false
 532 size=131072
 533
 534 [system.cpu.interrupts]
 535 type=SparcInterrupts
 536 eventq_index=0
 537
 538 [system.cpu.isa]
 539 type=SparcISA
 540 eventq_index=0
 541
 542 [system.cpu.itb]
 543 type=SparcTLB
 544 eventq_index=0
 545 size=64
 546
 547 [system.cpu.l2cache]
 548 type=BaseCache
 549 children=tags
 550 addr_ranges=0:18446744073709551615
 551 assoc=8
 552 clk_domain=system.cpu_clk_domain
 553 eventq_index=0
 554 forward_snoops=true
 555 hit_latency=20
 556 is_top_level=false
 557 max_miss_count=0
 558 mshrs=20
 559 prefetch_on_access=false
 560 prefetcher=Null
 561 response_latency=20
 562 sequential_access=false
 563 size=2097152
 564 system=system
 565 tags=system.cpu.l2cache.tags
 566 tgts_per_mshr=12
 567 two_queue=false
 568 write_buffers=8
 569 cpu_side=system.cpu.toL2Bus.master[0]
 570 mem_side=system.membus.slave[1]
 571
 572 [system.cpu.l2cache.tags]
 573 type=LRU
 574 assoc=8
 575 block_size=64
 576 clk_domain=system.cpu_clk_domain
 577 eventq_index=0
 578 hit_latency=20
 579 sequential_access=false
 580 size=2097152
 581
 582 [system.cpu.toL2Bus]
 583 type=CoherentXBar
 584 clk_domain=system.cpu_clk_domain
 585 eventq_index=0
 586 header_cycles=1
 587 snoop_filter=Null
 588 system=system
 589 use_default_range=false
 590 width=32
 591 master=system.cpu.l2cache.cpu_side
 592 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 593
 594 [system.cpu.tracer]
 595 type=ExeTracer
 596 eventq_index=0
 597
 598 [system.cpu.workload]
 599 type=LiveProcess
 600 cmd=insttest
 601 cwd=
 602 egid=100
 603 env=
 604 errout=cerr
 605 euid=100
 606 eventq_index=0
 607 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
 608 gid=100
 609 input=cin
 610 max_stack_size=67108864
 611 output=cout
 612 pid=100
 613 ppid=99
 614 simpoint=0
 615 system=system
 616 uid=100
 617 useArchPT=false
 618
 619 [system.cpu_clk_domain]
 620 type=SrcClockDomain
 621 clock=500
 622 domain_id=-1
 623 eventq_index=0
 624 init_perf_level=0
 625 voltage_domain=system.voltage_domain
 626
 627 [system.dvfs_handler]
 628 type=DVFSHandler
 629 domains=
 630 enable=false
 631 eventq_index=0
 632 sys_clk_domain=system.clk_domain
 633 transition_latency=100000000
 634
 635 [system.membus]
 636 type=CoherentXBar
 637 clk_domain=system.clk_domain
 638 eventq_index=0
 639 header_cycles=1
 640 snoop_filter=Null
 641 system=system
 642 use_default_range=false
 643 width=8
 644 master=system.physmem.port
 645 slave=system.system_port system.cpu.l2cache.mem_side
 646
 647 [system.physmem]
 648 type=DRAMCtrl
 649 IDD0=0.075000
 650 IDD02=0.000000
 651 IDD2N=0.050000
 652 IDD2N2=0.000000
 653 IDD2P0=0.000000
 654 IDD2P02=0.000000
 655 IDD2P1=0.000000
 656 IDD2P12=0.000000
 657 IDD3N=0.057000
 658 IDD3N2=0.000000
 659 IDD3P0=0.000000
 660 IDD3P02=0.000000
 661 IDD3P1=0.000000
 662 IDD3P12=0.000000
 663 IDD4R=0.187000
 664 IDD4R2=0.000000
 665 IDD4W=0.165000
 666 IDD4W2=0.000000
 667 IDD5=0.220000
 668 IDD52=0.000000
 669 IDD6=0.000000
 670 IDD62=0.000000
 671 VDD=1.500000
 672 VDD2=0.000000
 673 activation_limit=4
 674 addr_mapping=RoRaBaChCo
 675 bank_groups_per_rank=0
 676 banks_per_rank=8
 677 burst_length=8
 678 channels=1
 679 clk_domain=system.clk_domain
 680 conf_table_reported=true
 681 device_bus_width=8
 682 device_rowbuffer_size=1024
 683 devices_per_rank=8
 684 dll=true
 685 eventq_index=0
 686 in_addr_map=true
 687 max_accesses_per_row=16
 688 mem_sched_policy=frfcfs
 689 min_writes_per_switch=16
 690 null=false
 691 page_policy=open_adaptive
 692 range=0:134217727
 693 ranks_per_channel=2
 694 read_buffer_size=32
 695 static_backend_latency=10000
 696 static_frontend_latency=10000
 697 tBURST=5000
 698 tCCD_L=0
 699 tCK=1250
 700 tCL=13750
 701 tCS=2500
 702 tRAS=35000
 703 tRCD=13750
 704 tREFI=7800000
 705 tRFC=260000
 706 tRP=13750
 707 tRRD=6000
 708 tRRD_L=0
 709 tRTP=7500
 710 tRTW=2500
 711 tWR=15000
 712 tWTR=7500
 713 tXAW=30000
 714 tXP=0
 715 tXPDLL=0
 716 tXS=0
 717 tXSDLL=0
 718 write_buffer_size=64
 719 write_high_thresh_perc=85
 720 write_low_thresh_perc=50
 721 port=system.membus.master[0]
 722
 723 [system.voltage_domain]
 724 type=VoltageDomain
 725 eventq_index=0
 726 voltage=1.000000
 727