2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000020 # Number of seconds simulated
4 sim_ticks 19744500 # Number of ticks simulated
5 final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 52427 # Simulator instruction rate (inst/s)
8 host_op_rate 52424 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 71633039 # Simulator tick rate (ticks/s)
10 host_mem_usage 221536 # Number of bytes of host memory used
11 host_seconds 0.28 # Real time elapsed on the host
12 sim_insts 14449 # Number of instructions simulated
13 sim_ops 14449 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 30976 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 0 # Number of bytes written to this memory
17 system.physmem.num_reads 484 # Number of read requests responded to by this memory
18 system.physmem.num_writes 0 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s)
23 system.cpu.workload.num_syscalls 18 # Number of system calls
24 system.cpu.numCycles 39490 # number of cpu cycles simulated
25 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27 system.cpu.BPredUnit.lookups 6899 # Number of BP lookups
28 system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted
29 system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect
30 system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups
31 system.cpu.BPredUnit.BTBHits 2573 # Number of BTB hits
32 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
33 system.cpu.BPredUnit.usedRAS 464 # Number of times the RAS was used to get a target.
34 system.cpu.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions.
35 system.cpu.fetch.icacheStallCycles 11886 # Number of cycles fetch is stalled on an Icache miss
36 system.cpu.fetch.Insts 32156 # Number of instructions fetch has processed
37 system.cpu.fetch.Branches 6899 # Number of branches that fetch encountered
38 system.cpu.fetch.predictedBranches 3037 # Number of branches that fetch has predicted taken
39 system.cpu.fetch.Cycles 9512 # Number of cycles fetch has run and was not squashing or blocked
40 system.cpu.fetch.SquashCycles 3178 # Number of cycles fetch has spent squashing
41 system.cpu.fetch.BlockedCycles 6896 # Number of cycles fetch has spent blocked
42 system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
43 system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps
44 system.cpu.fetch.CacheLines 5506 # Number of cache lines fetched
45 system.cpu.fetch.IcacheSquashes 480 # Number of outstanding Icache misses that were squashed
46 system.cpu.fetch.rateDist::samples 30987 # Number of instructions fetched each cycle (Total)
47 system.cpu.fetch.rateDist::mean 1.037725 # Number of instructions fetched each cycle (Total)
48 system.cpu.fetch.rateDist::stdev 2.210162 # Number of instructions fetched each cycle (Total)
49 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
50 system.cpu.fetch.rateDist::0 21475 69.30% 69.30% # Number of instructions fetched each cycle (Total)
51 system.cpu.fetch.rateDist::1 4729 15.26% 84.56% # Number of instructions fetched each cycle (Total)
52 system.cpu.fetch.rateDist::2 477 1.54% 86.10% # Number of instructions fetched each cycle (Total)
53 system.cpu.fetch.rateDist::3 446 1.44% 87.54% # Number of instructions fetched each cycle (Total)
54 system.cpu.fetch.rateDist::4 688 2.22% 89.76% # Number of instructions fetched each cycle (Total)
55 system.cpu.fetch.rateDist::5 747 2.41% 92.17% # Number of instructions fetched each cycle (Total)
56 system.cpu.fetch.rateDist::6 238 0.77% 92.94% # Number of instructions fetched each cycle (Total)
57 system.cpu.fetch.rateDist::7 276 0.89% 93.83% # Number of instructions fetched each cycle (Total)
58 system.cpu.fetch.rateDist::8 1911 6.17% 100.00% # Number of instructions fetched each cycle (Total)
59 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
60 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
61 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
62 system.cpu.fetch.rateDist::total 30987 # Number of instructions fetched each cycle (Total)
63 system.cpu.fetch.branchRate 0.174702 # Number of branch fetches per cycle
64 system.cpu.fetch.rate 0.814282 # Number of inst fetches per cycle
65 system.cpu.decode.IdleCycles 12512 # Number of cycles decode is idle
66 system.cpu.decode.BlockedCycles 7643 # Number of cycles decode is blocked
67 system.cpu.decode.RunCycles 8680 # Number of cycles decode is running
68 system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking
69 system.cpu.decode.SquashCycles 1963 # Number of cycles decode is squashing
70 system.cpu.decode.DecodedInsts 29984 # Number of instructions handled by decode
71 system.cpu.rename.SquashCycles 1963 # Number of cycles rename is squashing
72 system.cpu.rename.IdleCycles 13183 # Number of cycles rename is idle
73 system.cpu.rename.BlockCycles 245 # Number of cycles rename is blocking
74 system.cpu.rename.serializeStallCycles 6907 # count of cycles rename stalled for serializing inst
75 system.cpu.rename.RunCycles 8245 # Number of cycles rename is running
76 system.cpu.rename.UnblockCycles 444 # Number of cycles rename is unblocking
77 system.cpu.rename.RenamedInsts 27285 # Number of instructions processed by rename
78 system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
79 system.cpu.rename.LSQFullEvents 121 # Number of times rename has blocked due to LSQ full
80 system.cpu.rename.RenamedOperands 24368 # Number of destination operands rename has renamed
81 system.cpu.rename.RenameLookups 50732 # Number of register rename lookups that rename has made
82 system.cpu.rename.int_rename_lookups 50732 # Number of integer rename lookups
83 system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
84 system.cpu.rename.UndoneMaps 10536 # Number of HB maps that are undone due to squashing
85 system.cpu.rename.serializingInsts 705 # count of serializing insts renamed
86 system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed
87 system.cpu.rename.skidInsts 2853 # count of insts added to the skid buffer
88 system.cpu.memDep0.insertedLoads 3628 # Number of loads inserted to the mem dependence unit.
89 system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit.
90 system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
91 system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
92 system.cpu.iq.iqInstsAdded 23083 # Number of instructions added to the IQ (excludes non-spec)
93 system.cpu.iq.iqNonSpecInstsAdded 663 # Number of non-speculative instructions added to the IQ
94 system.cpu.iq.iqInstsIssued 21701 # Number of instructions issued
95 system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
96 system.cpu.iq.iqSquashedInstsExamined 8350 # Number of squashed instructions iterated over during squash; mainly for profiling
97 system.cpu.iq.iqSquashedOperandsExamined 5831 # Number of squashed operands that are examined and possibly removed from graph
98 system.cpu.iq.iqSquashedNonSpecRemoved 188 # Number of squashed non-spec instructions that were removed
99 system.cpu.iq.issued_per_cycle::samples 30987 # Number of insts issued each cycle
100 system.cpu.iq.issued_per_cycle::mean 0.700326 # Number of insts issued each cycle
101 system.cpu.iq.issued_per_cycle::stdev 1.316293 # Number of insts issued each cycle
102 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
103 system.cpu.iq.issued_per_cycle::0 21563 69.59% 69.59% # Number of insts issued each cycle
104 system.cpu.iq.issued_per_cycle::1 3594 11.60% 81.19% # Number of insts issued each cycle
105 system.cpu.iq.issued_per_cycle::2 2382 7.69% 88.87% # Number of insts issued each cycle
106 system.cpu.iq.issued_per_cycle::3 1729 5.58% 94.45% # Number of insts issued each cycle
107 system.cpu.iq.issued_per_cycle::4 896 2.89% 97.34% # Number of insts issued each cycle
108 system.cpu.iq.issued_per_cycle::5 479 1.55% 98.89% # Number of insts issued each cycle
109 system.cpu.iq.issued_per_cycle::6 250 0.81% 99.70% # Number of insts issued each cycle
110 system.cpu.iq.issued_per_cycle::7 75 0.24% 99.94% # Number of insts issued each cycle
111 system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle
112 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
113 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
114 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
115 system.cpu.iq.issued_per_cycle::total 30987 # Number of insts issued each cycle
116 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
117 system.cpu.iq.fu_full::IntAlu 54 30.17% 30.17% # attempts to use FU when none available
118 system.cpu.iq.fu_full::IntMult 0 0.00% 30.17% # attempts to use FU when none available
119 system.cpu.iq.fu_full::IntDiv 0 0.00% 30.17% # attempts to use FU when none available
120 system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.17% # attempts to use FU when none available
121 system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.17% # attempts to use FU when none available
122 system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.17% # attempts to use FU when none available
123 system.cpu.iq.fu_full::FloatMult 0 0.00% 30.17% # attempts to use FU when none available
124 system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.17% # attempts to use FU when none available
125 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.17% # attempts to use FU when none available
126 system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.17% # attempts to use FU when none available
127 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.17% # attempts to use FU when none available
128 system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.17% # attempts to use FU when none available
129 system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.17% # attempts to use FU when none available
130 system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.17% # attempts to use FU when none available
131 system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.17% # attempts to use FU when none available
132 system.cpu.iq.fu_full::SimdMult 0 0.00% 30.17% # attempts to use FU when none available
133 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.17% # attempts to use FU when none available
134 system.cpu.iq.fu_full::SimdShift 0 0.00% 30.17% # attempts to use FU when none available
135 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.17% # attempts to use FU when none available
136 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.17% # attempts to use FU when none available
137 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.17% # attempts to use FU when none available
138 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.17% # attempts to use FU when none available
139 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.17% # attempts to use FU when none available
140 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.17% # attempts to use FU when none available
141 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.17% # attempts to use FU when none available
142 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.17% # attempts to use FU when none available
143 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.17% # attempts to use FU when none available
144 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.17% # attempts to use FU when none available
145 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.17% # attempts to use FU when none available
146 system.cpu.iq.fu_full::MemRead 26 14.53% 44.69% # attempts to use FU when none available
147 system.cpu.iq.fu_full::MemWrite 99 55.31% 100.00% # attempts to use FU when none available
148 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
149 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
150 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
151 system.cpu.iq.FU_type_0::IntAlu 16032 73.88% 73.88% # Type of FU issued
152 system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued
153 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued
154 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued
155 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued
156 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued
157 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued
158 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued
159 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued
160 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued
161 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued
162 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued
163 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued
164 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued
165 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued
166 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued
167 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued
168 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued
169 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued
170 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued
171 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued
172 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued
173 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued
174 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued
175 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued
176 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued
177 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued
178 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued
179 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued
180 system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.69% # Type of FU issued
181 system.cpu.iq.FU_type_0::MemWrite 2237 10.31% 100.00% # Type of FU issued
182 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
183 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
184 system.cpu.iq.FU_type_0::total 21701 # Type of FU issued
185 system.cpu.iq.rate 0.549532 # Inst issue rate
186 system.cpu.iq.fu_busy_cnt 179 # FU busy when requested
187 system.cpu.iq.fu_busy_rate 0.008248 # FU busy rate (busy events/executed inst)
188 system.cpu.iq.int_inst_queue_reads 74673 # Number of integer instruction queue reads
189 system.cpu.iq.int_inst_queue_writes 32122 # Number of integer instruction queue writes
190 system.cpu.iq.int_inst_queue_wakeup_accesses 19916 # Number of integer instruction queue wakeup accesses
191 system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
192 system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
193 system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
194 system.cpu.iq.int_alu_accesses 21880 # Number of integer alu accesses
195 system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
196 system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
197 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
198 system.cpu.iew.lsq.thread0.squashedLoads 1402 # Number of loads squashed
199 system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
200 system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
201 system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed
202 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
203 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
204 system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
205 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
206 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
207 system.cpu.iew.iewSquashCycles 1963 # Number of cycles IEW is squashing
208 system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking
209 system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
210 system.cpu.iew.iewDispatchedInsts 24909 # Number of instructions dispatched to IQ
211 system.cpu.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
212 system.cpu.iew.iewDispLoadInsts 3628 # Number of dispatched load instructions
213 system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions
214 system.cpu.iew.iewDispNonSpecInsts 663 # Number of dispatched non-speculative instructions
215 system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
216 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
217 system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
218 system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly
219 system.cpu.iew.predictedNotTakenIncorrect 956 # Number of branches that were predicted not taken incorrectly
220 system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute
221 system.cpu.iew.iewExecutedInsts 20511 # Number of executed instructions
222 system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed
223 system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute
224 system.cpu.iew.exec_swp 0 # number of swp insts executed
225 system.cpu.iew.exec_nop 1163 # number of nop insts executed
226 system.cpu.iew.exec_refs 5392 # number of memory reference insts executed
227 system.cpu.iew.exec_branches 4300 # Number of branches executed
228 system.cpu.iew.exec_stores 2114 # Number of stores executed
229 system.cpu.iew.exec_rate 0.519397 # Inst execution rate
230 system.cpu.iew.wb_sent 20186 # cumulative count of insts sent to commit
231 system.cpu.iew.wb_count 19916 # cumulative count of insts written-back
232 system.cpu.iew.wb_producers 9270 # num instructions producing a value
233 system.cpu.iew.wb_consumers 11399 # num instructions consuming a value
234 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
235 system.cpu.iew.wb_rate 0.504330 # insts written-back per cycle
236 system.cpu.iew.wb_fanout 0.813229 # average fanout of values written-back
237 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
238 system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
239 system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions
240 system.cpu.commit.commitSquashedInsts 9652 # The number of squashed insts skipped by commit
241 system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
242 system.cpu.commit.branchMispredicts 1119 # The number of times a branch was mispredicted
243 system.cpu.commit.committed_per_cycle::samples 29041 # Number of insts commited each cycle
244 system.cpu.commit.committed_per_cycle::mean 0.522537 # Number of insts commited each cycle
245 system.cpu.commit.committed_per_cycle::stdev 1.206609 # Number of insts commited each cycle
246 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
247 system.cpu.commit.committed_per_cycle::0 21661 74.59% 74.59% # Number of insts commited each cycle
248 system.cpu.commit.committed_per_cycle::1 4067 14.00% 88.59% # Number of insts commited each cycle
249 system.cpu.commit.committed_per_cycle::2 1430 4.92% 93.52% # Number of insts commited each cycle
250 system.cpu.commit.committed_per_cycle::3 794 2.73% 96.25% # Number of insts commited each cycle
251 system.cpu.commit.committed_per_cycle::4 339 1.17% 97.42% # Number of insts commited each cycle
252 system.cpu.commit.committed_per_cycle::5 260 0.90% 98.31% # Number of insts commited each cycle
253 system.cpu.commit.committed_per_cycle::6 321 1.11% 99.42% # Number of insts commited each cycle
254 system.cpu.commit.committed_per_cycle::7 68 0.23% 99.65% # Number of insts commited each cycle
255 system.cpu.commit.committed_per_cycle::8 101 0.35% 100.00% # Number of insts commited each cycle
256 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
257 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
258 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
259 system.cpu.commit.committed_per_cycle::total 29041 # Number of insts commited each cycle
260 system.cpu.commit.committedInsts 15175 # Number of instructions committed
261 system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed
262 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
263 system.cpu.commit.refs 3674 # Number of memory references committed
264 system.cpu.commit.loads 2226 # Number of loads committed
265 system.cpu.commit.membars 0 # Number of memory barriers committed
266 system.cpu.commit.branches 3359 # Number of branches committed
267 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
268 system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
269 system.cpu.commit.function_calls 187 # Number of function calls committed.
270 system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
271 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
272 system.cpu.rob.rob_reads 52944 # The number of ROB reads
273 system.cpu.rob.rob_writes 51625 # The number of ROB writes
274 system.cpu.timesIdled 185 # Number of times that the entire CPU went into an idle state and unscheduled itself
275 system.cpu.idleCycles 8503 # Total number of cycles that the CPU has spent unscheduled due to idling
276 system.cpu.committedInsts 14449 # Number of Instructions Simulated
277 system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated
278 system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
279 system.cpu.cpi 2.733061 # CPI: Cycles Per Instruction
280 system.cpu.cpi_total 2.733061 # CPI: Total CPI of All Threads
281 system.cpu.ipc 0.365890 # IPC: Instructions Per Cycle
282 system.cpu.ipc_total 0.365890 # IPC: Total IPC of All Threads
283 system.cpu.int_regfile_reads 32680 # number of integer regfile reads
284 system.cpu.int_regfile_writes 18187 # number of integer regfile writes
285 system.cpu.misc_regfile_reads 7045 # number of misc regfile reads
286 system.cpu.misc_regfile_writes 569 # number of misc regfile writes
287 system.cpu.icache.replacements 0 # number of replacements
288 system.cpu.icache.tagsinuse 200.774248 # Cycle average of tags in use
289 system.cpu.icache.total_refs 5020 # Total number of references to valid blocks.
290 system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks.
291 system.cpu.icache.avg_refs 14.764706 # Average number of references to valid blocks.
292 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
293 system.cpu.icache.occ_blocks::cpu.inst 200.774248 # Average occupied blocks per requestor
294 system.cpu.icache.occ_percent::cpu.inst 0.098034 # Average percentage of cache occupancy
295 system.cpu.icache.occ_percent::total 0.098034 # Average percentage of cache occupancy
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309 system.cpu.icache.ReadReq_miss_latency::total 16725500 # number of ReadReq miss cycles
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311 system.cpu.icache.demand_miss_latency::total 16725500 # number of demand (read+write) miss cycles
312 system.cpu.icache.overall_miss_latency::cpu.inst 16725500 # number of overall miss cycles
313 system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles
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315 system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses)
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319 system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses
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324 system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency
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331 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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337 system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits
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339 system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits
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341 system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
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343 system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses
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345 system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses
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347 system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles
348 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles
349 system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles
350 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles
351 system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles
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353 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses
354 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses
355 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency
356 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
357 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
358 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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361 system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks.
362 system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
363 system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks.
364 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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369 system.cpu.dcache.ReadReq_hits::total 3043 # number of ReadReq hits
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389 system.cpu.dcache.WriteReq_miss_latency::total 14593500 # number of WriteReq miss cycles
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391 system.cpu.dcache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles
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393 system.cpu.dcache.overall_miss_latency::total 18686000 # number of overall miss cycles
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395 system.cpu.dcache.ReadReq_accesses::total 3161 # number of ReadReq accesses(hits+misses)
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397 system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
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403 system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses
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417 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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423 system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits
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427 system.cpu.dcache.overall_mshr_hits::total 380 # number of overall MSHR hits
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429 system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
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431 system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
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439 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2979500 # number of WriteReq MSHR miss cycles
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443 system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles
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449 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency
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451 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency
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457 system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks.
458 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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502 system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses
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511 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency
512 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency
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515 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency
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534 system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
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539 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles
540 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles
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544 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles
545 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles
546 system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles
547 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses
548 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
549 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
550 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses
551 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
552 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses
553 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
554 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency
555 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency
556 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency
557 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency
558 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency
559 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency
560 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency
561 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
563 ---------- End Simulation Statistics ----------
projects / gem5.git / blob