2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000045 # Number of seconds simulated
4 sim_ticks 44698500 # Number of ticks simulated
5 final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 357665 # Simulator instruction rate (inst/s)
8 host_op_rate 357507 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1053539740 # Simulator tick rate (ticks/s)
10 host_mem_usage 250236 # Number of bytes of host memory used
11 host_seconds 0.04 # Real time elapsed on the host
12 sim_insts 15162 # Number of instructions simulated
13 sim_ops 15162 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s)
33 system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
34 system.cpu_clk_domain.clock 500 # Clock period in ticks
35 system.cpu.workload.numSyscalls 18 # Number of system calls
36 system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states
37 system.cpu.numCycles 89397 # number of cpu cycles simulated
38 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
39 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
40 system.cpu.committedInsts 15162 # Number of instructions committed
41 system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
42 system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
43 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
44 system.cpu.num_func_calls 385 # number of times a function call or return occured
45 system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
46 system.cpu.num_int_insts 12219 # number of integer instructions
47 system.cpu.num_fp_insts 0 # number of float instructions
48 system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
49 system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
50 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
51 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
52 system.cpu.num_mem_refs 3683 # number of memory refs
53 system.cpu.num_load_insts 2231 # Number of load instructions
54 system.cpu.num_store_insts 1452 # Number of store instructions
55 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
56 system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles
57 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
58 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
59 system.cpu.Branches 3363 # Number of branches fetched
60 system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
61 system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
62 system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
63 system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
64 system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
65 system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction
66 system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction
67 system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction
68 system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction
69 system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction
70 system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction
71 system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction
72 system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction
73 system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction
74 system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction
75 system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction
76 system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction
77 system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction
78 system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction
79 system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction
80 system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction
81 system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction
82 system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction
83 system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction
84 system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction
85 system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction
86 system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction
87 system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction
88 system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction
89 system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
90 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
91 system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
92 system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
93 system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
94 system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
95 system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
96 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
97 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
98 system.cpu.op_class::total 15207 # Class of executed instruction
99 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
100 system.cpu.dcache.tags.replacements 0 # number of replacements
101 system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use
102 system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
103 system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
104 system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
105 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
106 system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor
107 system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy
108 system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy
109 system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
110 system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
111 system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
112 system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
113 system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
114 system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
115 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
116 system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
117 system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
118 system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
119 system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
120 system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
121 system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
122 system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
123 system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
124 system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
125 system.cpu.dcache.overall_hits::total 3529 # number of overall hits
126 system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
127 system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
128 system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
129 system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
130 system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
131 system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
132 system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
133 system.cpu.dcache.overall_misses::total 138 # number of overall misses
134 system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles
135 system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles
136 system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles
137 system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles
138 system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles
139 system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles
140 system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles
141 system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles
142 system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
143 system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
144 system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
145 system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
146 system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
147 system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
148 system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
149 system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
150 system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
151 system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
152 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
153 system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
154 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
155 system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
156 system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
157 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
158 system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
159 system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
160 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
161 system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
162 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
163 system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
164 system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
165 system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
166 system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
167 system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
168 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
169 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
170 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
171 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
172 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
173 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
174 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
175 system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
176 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
177 system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
178 system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
179 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
180 system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
181 system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
182 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles
183 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles
184 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles
185 system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles
186 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles
187 system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles
188 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles
189 system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles
190 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
191 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
192 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
193 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
194 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
195 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
196 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
197 system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
198 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
199 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
200 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
201 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
202 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
203 system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
204 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
205 system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
206 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
207 system.cpu.icache.tags.replacements 0 # number of replacements
208 system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use
209 system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
210 system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
211 system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
212 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
213 system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor
214 system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy
215 system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy
216 system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
217 system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
218 system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
219 system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
220 system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
221 system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
222 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
223 system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
224 system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
225 system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
226 system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
227 system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
228 system.cpu.icache.overall_hits::total 14928 # number of overall hits
229 system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
230 system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
231 system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
232 system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
233 system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
234 system.cpu.icache.overall_misses::total 280 # number of overall misses
235 system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles
236 system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles
237 system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles
238 system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles
239 system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles
240 system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles
241 system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
242 system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
243 system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
244 system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
245 system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
246 system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
247 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
248 system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
249 system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
250 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
251 system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
252 system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
253 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency
254 system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency
255 system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency
256 system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency
257 system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency
258 system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency
259 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
260 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
261 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
262 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
263 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
264 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
265 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
266 system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
267 system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
268 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
269 system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
270 system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
271 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles
272 system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles
273 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles
274 system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles
275 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles
276 system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles
277 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
278 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
279 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
280 system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
281 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
282 system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
283 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency
284 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency
285 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency
286 system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency
287 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency
288 system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency
289 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
290 system.cpu.l2cache.tags.replacements 0 # number of replacements
291 system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use
292 system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
293 system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks.
294 system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks.
295 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
296 system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor
297 system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor
298 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy
299 system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy
300 system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy
301 system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id
302 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
303 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
304 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id
305 system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
306 system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
307 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
308 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
309 system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
310 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
311 system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
312 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
313 system.cpu.l2cache.overall_hits::total 2 # number of overall hits
314 system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
315 system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
316 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
317 system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
318 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses
319 system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses
320 system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
321 system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
322 system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
323 system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
324 system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
325 system.cpu.l2cache.overall_misses::total 416 # number of overall misses
326 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles
327 system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles
328 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles
329 system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles
330 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles
331 system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles
332 system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles
333 system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles
334 system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles
335 system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles
336 system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles
337 system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles
338 system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
339 system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
340 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses)
341 system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses)
342 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses)
343 system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses)
344 system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
345 system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
346 system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
347 system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
348 system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
349 system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
350 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
351 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
352 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses
353 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses
354 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
355 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
356 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
357 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
358 system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
359 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
360 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
361 system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
362 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
363 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
364 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency
365 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency
366 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
367 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
368 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
369 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
370 system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency
371 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
372 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
373 system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency
374 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
375 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
376 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
377 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
378 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
379 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
380 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
381 system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
382 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
383 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses
384 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses
385 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses
386 system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
387 system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
388 system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
390 system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
391 system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
392 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles
393 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles
394 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles
395 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles
396 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles
397 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles
398 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles
399 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles
400 system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles
401 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles
402 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles
403 system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles
404 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
405 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
406 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses
407 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses
408 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
409 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
410 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
411 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
412 system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
413 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
414 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
415 system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
416 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
417 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
418 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency
419 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency
420 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
421 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
422 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
423 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
424 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency
425 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
426 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
427 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency
428 system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
429 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
430 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
431 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
432 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
433 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
434 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
435 system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
436 system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
437 system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
438 system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution
439 system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution
440 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
441 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
442 system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
443 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
444 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
445 system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
446 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
447 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
448 system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
449 system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram
450 system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram
451 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
452 system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram
453 system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram
454 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
455 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
456 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
457 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
458 system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
459 system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
460 system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
461 system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
462 system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
463 system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
464 system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
465 system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter.
466 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
467 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
468 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
469 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
470 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
471 system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
472 system.membus.trans_dist::ReadResp 331 # Transaction distribution
473 system.membus.trans_dist::ReadExReq 85 # Transaction distribution
474 system.membus.trans_dist::ReadExResp 85 # Transaction distribution
475 system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution
476 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
477 system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
478 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
479 system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
480 system.membus.snoops 0 # Total snoops (count)
481 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
482 system.membus.snoop_fanout::samples 416 # Request fanout histogram
483 system.membus.snoop_fanout::mean 0 # Request fanout histogram
484 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
485 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
486 system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
487 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
488 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
489 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
490 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
491 system.membus.snoop_fanout::total 416 # Request fanout histogram
492 system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
493 system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
494 system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks)
495 system.membus.respLayer1.utilization 4.7 # Layer utilization (%)
497 ---------- End Simulation Statistics ----------
projects / gem5.git / blob