2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000041 # Number of seconds simulated
4 sim_ticks 41368000 # Number of ticks simulated
5 final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 479032 # Simulator instruction rate (inst/s)
8 host_op_rate 478642 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1304958787 # Simulator tick rate (ticks/s)
10 host_mem_usage 231320 # Number of bytes of host memory used
11 host_seconds 0.03 # Real time elapsed on the host
12 sim_insts 15162 # Number of instructions simulated
13 sim_ops 15162 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
30 system.membus.throughput 643589248 # Throughput (bytes/s)
31 system.membus.trans_dist::ReadReq 331 # Transaction distribution
32 system.membus.trans_dist::ReadResp 331 # Transaction distribution
33 system.membus.trans_dist::ReadExReq 85 # Transaction distribution
34 system.membus.trans_dist::ReadExResp 85 # Transaction distribution
35 system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes)
36 system.membus.pkt_count 832 # Packet count per connected master and slave (bytes)
37 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes)
38 system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes)
39 system.membus.data_through_bus 26624 # Total data (bytes)
40 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41 system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
42 system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
43 system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
44 system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
45 system.cpu.workload.num_syscalls 18 # Number of system calls
46 system.cpu.numCycles 82736 # number of cpu cycles simulated
47 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
48 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
49 system.cpu.committedInsts 15162 # Number of instructions committed
50 system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
51 system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
52 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
53 system.cpu.num_func_calls 385 # number of times a function call or return occured
54 system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
55 system.cpu.num_int_insts 12219 # number of integer instructions
56 system.cpu.num_fp_insts 0 # number of float instructions
57 system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
58 system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
59 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
60 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
61 system.cpu.num_mem_refs 3683 # number of memory refs
62 system.cpu.num_load_insts 2231 # Number of load instructions
63 system.cpu.num_store_insts 1452 # Number of store instructions
64 system.cpu.num_idle_cycles 0 # Number of idle cycles
65 system.cpu.num_busy_cycles 82736 # Number of busy cycles
66 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
67 system.cpu.idle_fraction 0 # Percentage of idle cycles
68 system.cpu.icache.replacements 0 # number of replacements
69 system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use
70 system.cpu.icache.total_refs 14928 # Total number of references to valid blocks.
71 system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
72 system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks.
73 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
74 system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
75 system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
76 system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy
77 system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
78 system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
79 system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
80 system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
81 system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
82 system.cpu.icache.overall_hits::total 14928 # number of overall hits
83 system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
84 system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
85 system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
86 system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
87 system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
88 system.cpu.icache.overall_misses::total 280 # number of overall misses
89 system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
90 system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
91 system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
92 system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
93 system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
94 system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
95 system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
96 system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
97 system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
98 system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
99 system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
100 system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
101 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
102 system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
103 system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
104 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
105 system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
106 system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
107 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
108 system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
109 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
110 system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
111 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
112 system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
113 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
114 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
115 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
116 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
117 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
118 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
119 system.cpu.icache.fast_writes 0 # number of fast writes performed
120 system.cpu.icache.cache_copies 0 # number of cache copies performed
121 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
122 system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
123 system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
124 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
125 system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
126 system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
127 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
128 system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
129 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
130 system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
131 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
132 system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
133 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
134 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
135 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
136 system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
137 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
138 system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
139 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
140 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
141 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
142 system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
143 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
144 system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
145 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
146 system.cpu.l2cache.replacements 0 # number of replacements
147 system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use
148 system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
149 system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
150 system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
151 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
152 system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
153 system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
154 system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
155 system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
156 system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy
157 system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
158 system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
159 system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
160 system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
161 system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
162 system.cpu.l2cache.overall_hits::total 2 # number of overall hits
163 system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
164 system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
165 system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses
166 system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
167 system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
168 system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
169 system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
170 system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
171 system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
172 system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
173 system.cpu.l2cache.overall_misses::total 416 # number of overall misses
174 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
175 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
176 system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
177 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
178 system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
179 system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
180 system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
181 system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
182 system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
183 system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
184 system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
185 system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
186 system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
187 system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses)
188 system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
189 system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
190 system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
191 system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
192 system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
193 system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
194 system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
195 system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
196 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses
197 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
198 system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses
199 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
200 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
201 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
202 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
203 system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
204 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
205 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
206 system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
207 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
208 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
209 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
210 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
211 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
212 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
213 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
214 system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
215 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
216 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
217 system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
218 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
219 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
220 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
221 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
222 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
223 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
224 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
225 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
226 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
227 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
228 system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
229 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
230 system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
231 system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
232 system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
233 system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
234 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
235 system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
236 system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
237 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
238 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
239 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
240 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
241 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
242 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
243 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
244 system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
245 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
246 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
247 system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
248 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
249 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
250 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
251 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
252 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
253 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
254 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
255 system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
256 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
257 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
258 system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
259 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
260 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
261 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
262 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
263 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
264 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
265 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
266 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
267 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
268 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
269 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
270 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
271 system.cpu.dcache.replacements 0 # number of replacements
272 system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
273 system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
274 system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
275 system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
276 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
277 system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
278 system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
279 system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
280 system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
281 system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
282 system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
283 system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
284 system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
285 system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
286 system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
287 system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
288 system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
289 system.cpu.dcache.overall_hits::total 3529 # number of overall hits
290 system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
291 system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
292 system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
293 system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
294 system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
295 system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
296 system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
297 system.cpu.dcache.overall_misses::total 138 # number of overall misses
298 system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
299 system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
300 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
301 system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
302 system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
303 system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
304 system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
305 system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
306 system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
307 system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
308 system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
309 system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
310 system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
311 system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
312 system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
313 system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
314 system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
315 system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
316 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
317 system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
318 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
319 system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
320 system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
321 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
322 system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
323 system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
324 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
325 system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
326 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
327 system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
328 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
329 system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
330 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
331 system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
332 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
333 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
334 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
335 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
336 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
337 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
338 system.cpu.dcache.fast_writes 0 # number of fast writes performed
339 system.cpu.dcache.cache_copies 0 # number of cache copies performed
340 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
341 system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
342 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
343 system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
344 system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
345 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
346 system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
347 system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
348 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
349 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
350 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
351 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
352 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
353 system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
354 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
355 system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
356 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
357 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
358 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
359 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
360 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
361 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
362 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
363 system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
364 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
365 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
366 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
367 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
368 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
369 system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
370 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
371 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
372 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
373 system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s)
374 system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
375 system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
376 system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
377 system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
378 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes)
379 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
380 system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes)
381 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes)
382 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
383 system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
384 system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
385 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
386 system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
387 system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
388 system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
389 system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
390 system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
391 system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
393 ---------- End Simulation Statistics ----------
projects / gem5.git / blob